1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
17 * PCI controller operations
19 struct pci_controller_ops
{
20 void (*dma_dev_setup
)(struct pci_dev
*pdev
);
21 void (*dma_bus_setup
)(struct pci_bus
*bus
);
23 int (*probe_mode
)(struct pci_bus
*bus
);
25 /* Called when pci_enable_device() is called. Returns true to
26 * allow assignment/enabling of the device. */
27 bool (*enable_device_hook
)(struct pci_dev
*pdev
);
29 void (*disable_device
)(struct pci_dev
*pdev
);
31 void (*release_device
)(struct pci_dev
*pdev
);
33 /* Called during PCI resource reassignment */
34 resource_size_t (*window_alignment
)(struct pci_bus
*bus
,
36 void (*setup_bridge
)(struct pci_bus
*bus
,
38 void (*reset_secondary_bus
)(struct pci_dev
*pdev
);
41 int (*setup_msi_irqs
)(struct pci_dev
*pdev
,
43 void (*teardown_msi_irqs
)(struct pci_dev
*pdev
);
46 int (*dma_set_mask
)(struct pci_dev
*pdev
, u64 dma_mask
);
47 u64 (*dma_get_required_mask
)(struct pci_dev
*pdev
);
49 void (*shutdown
)(struct pci_controller
*hose
);
53 * Structure of a PCI controller (host bridge)
55 struct pci_controller
{
61 struct device_node
*dn
;
62 struct list_head list_node
;
63 struct device
*parent
;
70 void __iomem
*io_base_virt
;
74 resource_size_t io_base_phys
;
75 resource_size_t pci_io_size
;
77 /* Some machines have a special region to forward the ISA
78 * "memory" cycles such as VGA memory regions. Left to 0
81 resource_size_t isa_mem_phys
;
82 resource_size_t isa_mem_size
;
84 struct pci_controller_ops controller_ops
;
86 unsigned int __iomem
*cfg_addr
;
87 void __iomem
*cfg_data
;
90 * Used for variants of PCI indirect handling and possible quirks:
91 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
92 * EXT_REG - provides access to PCI-e extended registers
93 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
94 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
95 * to determine which bus number to match on when generating type0
97 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
98 * hanging if we don't have link and try to do config cycles to
99 * anything but the PHB. Only allow talking to the PHB if this is
101 * BIG_ENDIAN - cfg_addr is a big endian register
102 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
103 * the PLB4. Effectively disable MRM commands by setting this.
104 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
105 * link status is in a RC PCIe cfg register (vs being a SoC register)
107 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
108 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
109 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
110 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
111 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
112 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
113 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
115 /* Currently, we limit ourselves to 1 IO range and 3 mem
116 * ranges since the common pci_bus structure can't handle more
118 struct resource io_resource
;
119 struct resource mem_resources
[3];
120 resource_size_t mem_offset
[3];
121 int global_number
; /* PCI domain number */
123 resource_size_t dma_window_base_cur
;
124 resource_size_t dma_window_size
;
128 struct pci_dn
*pci_data
;
129 #endif /* CONFIG_PPC64 */
135 /* These are used for config access before all the PCI probing
137 extern int early_read_config_byte(struct pci_controller
*hose
, int bus
,
138 int dev_fn
, int where
, u8
*val
);
139 extern int early_read_config_word(struct pci_controller
*hose
, int bus
,
140 int dev_fn
, int where
, u16
*val
);
141 extern int early_read_config_dword(struct pci_controller
*hose
, int bus
,
142 int dev_fn
, int where
, u32
*val
);
143 extern int early_write_config_byte(struct pci_controller
*hose
, int bus
,
144 int dev_fn
, int where
, u8 val
);
145 extern int early_write_config_word(struct pci_controller
*hose
, int bus
,
146 int dev_fn
, int where
, u16 val
);
147 extern int early_write_config_dword(struct pci_controller
*hose
, int bus
,
148 int dev_fn
, int where
, u32 val
);
150 extern int early_find_capability(struct pci_controller
*hose
, int bus
,
151 int dev_fn
, int cap
);
153 extern void setup_indirect_pci(struct pci_controller
* hose
,
154 resource_size_t cfg_addr
,
155 resource_size_t cfg_data
, u32 flags
);
157 extern int indirect_read_config(struct pci_bus
*bus
, unsigned int devfn
,
158 int offset
, int len
, u32
*val
);
160 extern int __indirect_read_config(struct pci_controller
*hose
,
161 unsigned char bus_number
, unsigned int devfn
,
162 int offset
, int len
, u32
*val
);
164 extern int indirect_write_config(struct pci_bus
*bus
, unsigned int devfn
,
165 int offset
, int len
, u32 val
);
167 static inline struct pci_controller
*pci_bus_to_host(const struct pci_bus
*bus
)
174 extern int pci_device_from_OF_node(struct device_node
*node
,
176 extern void pci_create_OF_bus_map(void);
178 #else /* CONFIG_PPC64 */
181 * PCI stuff, for nodes representing PCI devices, pointed to
182 * by device_node->data.
188 #define PCI_DN_FLAG_IOV_VF 0x01
190 int busno
; /* pci bus number */
191 int devfn
; /* pci device and function number */
192 int vendor_id
; /* Vendor ID */
193 int device_id
; /* Device ID */
194 int class_code
; /* Device class code */
196 struct pci_dn
*parent
;
197 struct pci_controller
*phb
; /* for pci devices */
198 struct iommu_table_group
*table_group
; /* for phb's or bridges */
200 int pci_ext_config_space
; /* for pci devices */
202 struct eeh_dev
*edev
; /* eeh device */
204 #define IODA_INVALID_PE 0xFFFFFFFF
205 unsigned int pe_number
;
206 #ifdef CONFIG_PCI_IOV
207 int vf_index
; /* VF index in the PF */
208 u16 vfs_expanded
; /* number of VFs IOV BAR expanded */
209 u16 num_vfs
; /* number of VFs enabled*/
210 unsigned int *pe_num_map
; /* PE# for the first VF PE or array */
211 bool m64_single_mode
; /* Use M64 BAR in Single Mode */
212 #define IODA_INVALID_M64 (-1)
213 int (*m64_map
)[PCI_SRIOV_NUM_BARS
]; /* Only used on powernv */
214 int last_allow_rc
; /* Only used on pseries */
215 #endif /* CONFIG_PCI_IOV */
216 int mps
; /* Maximum Payload Size */
217 struct list_head child_list
;
218 struct list_head list
;
219 struct resource holes
[PCI_SRIOV_NUM_BARS
];
222 /* Get the pointer to a device_node's pci_dn */
223 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
225 extern struct pci_dn
*pci_get_pdn_by_devfn(struct pci_bus
*bus
,
227 extern struct pci_dn
*pci_get_pdn(struct pci_dev
*pdev
);
228 extern struct pci_dn
*add_dev_pci_data(struct pci_dev
*pdev
);
229 extern void remove_dev_pci_data(struct pci_dev
*pdev
);
230 extern struct pci_dn
*pci_add_device_node_info(struct pci_controller
*hose
,
231 struct device_node
*dn
);
232 extern void pci_remove_device_node_info(struct device_node
*dn
);
234 static inline int pci_device_from_OF_node(struct device_node
*np
,
239 *bus
= PCI_DN(np
)->busno
;
240 *devfn
= PCI_DN(np
)->devfn
;
244 #if defined(CONFIG_EEH)
245 static inline struct eeh_dev
*pdn_to_eeh_dev(struct pci_dn
*pdn
)
247 return pdn
? pdn
->edev
: NULL
;
250 #define pdn_to_eeh_dev(x) (NULL)
253 /** Find the bus corresponding to the indicated device node */
254 extern struct pci_bus
*pci_find_bus_by_node(struct device_node
*dn
);
256 /** Remove all of the PCI devices under this bus */
257 extern void pci_hp_remove_devices(struct pci_bus
*bus
);
259 /** Discover new pci devices under this bus, and add them */
260 extern void pci_hp_add_devices(struct pci_bus
*bus
);
262 extern int pcibios_unmap_io_space(struct pci_bus
*bus
);
263 extern int pcibios_map_io_space(struct pci_bus
*bus
);
266 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
268 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
271 #endif /* CONFIG_PPC64 */
273 /* Get the PCI host controller for an OF device */
274 extern struct pci_controller
*pci_find_hose_for_OF_device(
275 struct device_node
* node
);
277 /* Fill up host controller resources from the OF node */
278 extern void pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
279 struct device_node
*dev
, int primary
);
281 /* Allocate & free a PCI host bridge structure */
282 extern struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
);
283 extern void pcibios_free_controller(struct pci_controller
*phb
);
284 extern void pcibios_free_controller_deferred(struct pci_host_bridge
*bridge
);
287 extern int pcibios_vaddr_is_ioport(void __iomem
*address
);
289 static inline int pcibios_vaddr_is_ioport(void __iomem
*address
)
293 #endif /* CONFIG_PCI */
295 #endif /* __KERNEL__ */
296 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */