arch/powerpc/include/asm/pci-bridge.h

   1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
   2 #define _ASM_POWERPC_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/list.h>
  12 #include <linux/ioport.h>
  13 #include <asm-generic/pci-bridge.h>
  14
  15 struct device_node;
  16
  17 /*
  18  * PCI controller operations
  19  */
  20 struct pci_controller_ops {
  21         void            (*dma_dev_setup)(struct pci_dev *dev);
  22         void            (*dma_bus_setup)(struct pci_bus *bus);
  23 };
  24
  25 /*
  26  * Structure of a PCI controller (host bridge)
  27  */
  28 struct pci_controller {
  29         struct pci_bus *bus;
  30         char is_dynamic;
  31 #ifdef CONFIG_PPC64
  32         int node;
  33 #endif
  34         struct device_node *dn;
  35         struct list_head list_node;
  36         struct device *parent;
  37
  38         int first_busno;
  39         int last_busno;
  40         int self_busno;
  41         struct resource busn;
  42
  43         void __iomem *io_base_virt;
  44 #ifdef CONFIG_PPC64
  45         void *io_base_alloc;
  46 #endif
  47         resource_size_t io_base_phys;
  48         resource_size_t pci_io_size;
  49
  50         /* Some machines have a special region to forward the ISA
  51          * "memory" cycles such as VGA memory regions. Left to 0
  52          * if unsupported
  53          */
  54         resource_size_t isa_mem_phys;
  55         resource_size_t isa_mem_size;
  56
  57         struct pci_controller_ops controller_ops;
  58         struct pci_ops *ops;
  59         unsigned int __iomem *cfg_addr;
  60         void __iomem *cfg_data;
  61
  62         /*
  63          * Used for variants of PCI indirect handling and possible quirks:
  64          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  65          *  EXT_REG - provides access to PCI-e extended registers
  66          *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  67          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  68          *   to determine which bus number to match on when generating type0
  69          *   config cycles
  70          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  71          *   hanging if we don't have link and try to do config cycles to
  72          *   anything but the PHB.  Only allow talking to the PHB if this is
  73          *   set.
  74          *  BIG_ENDIAN - cfg_addr is a big endian register
  75          *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
  76          *   the PLB4.  Effectively disable MRM commands by setting this.
  77          *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
  78          *   link status is in a RC PCIe cfg register (vs being a SoC register)
  79          */
  80 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
  81 #define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
  82 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
  83 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
  84 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
  85 #define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
  86 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK      0x00000040
  87         u32 indirect_type;
  88         /* Currently, we limit ourselves to 1 IO range and 3 mem
  89          * ranges since the common pci_bus structure can't handle more
  90          */
  91         struct resource io_resource;
  92         struct resource mem_resources[3];
  93         resource_size_t mem_offset[3];
  94         int global_number;              /* PCI domain number */
  95
  96         resource_size_t dma_window_base_cur;
  97         resource_size_t dma_window_size;
  98
  99 #ifdef CONFIG_PPC64
 100         unsigned long buid;
 101         struct pci_dn *pci_data;
 102 #endif  /* CONFIG_PPC64 */
 103
 104         void *private_data;
 105 };
 106
 107 /* These are used for config access before all the PCI probing
 108    has been done. */
 109 extern int early_read_config_byte(struct pci_controller *hose, int bus,
 110                         int dev_fn, int where, u8 *val);
 111 extern int early_read_config_word(struct pci_controller *hose, int bus,
 112                         int dev_fn, int where, u16 *val);
 113 extern int early_read_config_dword(struct pci_controller *hose, int bus,
 114                         int dev_fn, int where, u32 *val);
 115 extern int early_write_config_byte(struct pci_controller *hose, int bus,
 116                         int dev_fn, int where, u8 val);
 117 extern int early_write_config_word(struct pci_controller *hose, int bus,
 118                         int dev_fn, int where, u16 val);
 119 extern int early_write_config_dword(struct pci_controller *hose, int bus,
 120                         int dev_fn, int where, u32 val);
 121
 122 extern int early_find_capability(struct pci_controller *hose, int bus,
 123                                  int dev_fn, int cap);
 124
 125 extern void setup_indirect_pci(struct pci_controller* hose,
 126                                resource_size_t cfg_addr,
 127                                resource_size_t cfg_data, u32 flags);
 128
 129 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
 130                                 int offset, int len, u32 *val);
 131
 132 extern int __indirect_read_config(struct pci_controller *hose,
 133                                   unsigned char bus_number, unsigned int devfn,
 134                                   int offset, int len, u32 *val);
 135
 136 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
 137                                  int offset, int len, u32 val);
 138
 139 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 140 {
 141         return bus->sysdata;
 142 }
 143
 144 #ifndef CONFIG_PPC64
 145
 146 extern int pci_device_from_OF_node(struct device_node *node,
 147                                    u8 *bus, u8 *devfn);
 148 extern void pci_create_OF_bus_map(void);
 149
 150 static inline int isa_vaddr_is_ioport(void __iomem *address)
 151 {
 152         /* No specific ISA handling on ppc32 at this stage, it
 153          * all goes through PCI
 154          */
 155         return 0;
 156 }
 157
 158 #else   /* CONFIG_PPC64 */
 159
 160 /*
 161  * PCI stuff, for nodes representing PCI devices, pointed to
 162  * by device_node->data.
 163  */
 164 struct iommu_table;
 165
 166 struct pci_dn {
 167         int     flags;
 168
 169         int     busno;                  /* pci bus number */
 170         int     devfn;                  /* pci device and function number */
 171         int     vendor_id;              /* Vendor ID */
 172         int     device_id;              /* Device ID */
 173         int     class_code;             /* Device class code */
 174
 175         struct  pci_dn *parent;
 176         struct  pci_controller *phb;    /* for pci devices */
 177         struct  iommu_table *iommu_table;       /* for phb's or bridges */
 178         struct  device_node *node;      /* back-pointer to the device_node */
 179
 180         int     pci_ext_config_space;   /* for pci devices */
 181
 182         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 183 #ifdef CONFIG_EEH
 184         struct eeh_dev *edev;           /* eeh device */
 185 #endif
 186 #define IODA_INVALID_PE         (-1)
 187 #ifdef CONFIG_PPC_POWERNV
 188         int     pe_number;
 189 #endif
 190         struct list_head child_list;
 191         struct list_head list;
 192 };
 193
 194 /* Get the pointer to a device_node's pci_dn */
 195 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 196
 197 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
 198                                            int devfn);
 199 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
 200 extern void *update_dn_pci_info(struct device_node *dn, void *data);
 201
 202 static inline int pci_device_from_OF_node(struct device_node *np,
 203                                           u8 *bus, u8 *devfn)
 204 {
 205         if (!PCI_DN(np))
 206                 return -ENODEV;
 207         *bus = PCI_DN(np)->busno;
 208         *devfn = PCI_DN(np)->devfn;
 209         return 0;
 210 }
 211
 212 #if defined(CONFIG_EEH)
 213 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
 214 {
 215         return pdn ? pdn->edev : NULL;
 216 }
 217 #else
 218 #define pdn_to_eeh_dev(x)       (NULL)
 219 #endif
 220
 221 /** Find the bus corresponding to the indicated device node */
 222 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 223
 224 /** Remove all of the PCI devices under this bus */
 225 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
 226
 227 /** Discover new pci devices under this bus, and add them */
 228 extern void pcibios_add_pci_devices(struct pci_bus *bus);
 229
 230
 231 extern void isa_bridge_find_early(struct pci_controller *hose);
 232
 233 static inline int isa_vaddr_is_ioport(void __iomem *address)
 234 {
 235         /* Check if address hits the reserved legacy IO range */
 236         unsigned long ea = (unsigned long)address;
 237         return ea >= ISA_IO_BASE && ea < ISA_IO_END;
 238 }
 239
 240 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 241 extern int pcibios_map_io_space(struct pci_bus *bus);
 242
 243 #ifdef CONFIG_NUMA
 244 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 245 #else
 246 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
 247 #endif
 248
 249 #endif  /* CONFIG_PPC64 */
 250
 251 /* Get the PCI host controller for an OF device */
 252 extern struct pci_controller *pci_find_hose_for_OF_device(
 253                         struct device_node* node);
 254
 255 /* Fill up host controller resources from the OF node */
 256 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 257                         struct device_node *dev, int primary);
 258
 259 /* Allocate & free a PCI host bridge structure */
 260 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 261 extern void pcibios_free_controller(struct pci_controller *phb);
 262
 263 #ifdef CONFIG_PCI
 264 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 265 #else
 266 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 267 {
 268         return 0;
 269 }
 270 #endif  /* CONFIG_PCI */
 271
 272 /*
 273  * Shims to prefer pci_controller version over ppc_md where available.
 274  */
 275 static inline void pci_dma_dev_setup(struct pci_dev *dev)
 276 {
 277         struct pci_controller *phb = pci_bus_to_host(dev->bus);
 278
 279         if (phb->controller_ops.dma_dev_setup)
 280                 phb->controller_ops.dma_dev_setup(dev);
 281         else if (ppc_md.pci_dma_dev_setup)
 282                 ppc_md.pci_dma_dev_setup(dev);
 283 }
 284
 285 static inline void pci_dma_bus_setup(struct pci_bus *bus)
 286 {
 287         struct pci_controller *phb = pci_bus_to_host(bus);
 288
 289         if (phb->controller_ops.dma_bus_setup)
 290                 phb->controller_ops.dma_bus_setup(bus);
 291         else if (ppc_md.pci_dma_bus_setup)
 292                 ppc_md.pci_dma_bus_setup(bus);
 293 }
 294
 295 #endif  /* __KERNEL__ */
 296 #endif  /* _ASM_POWERPC_PCI_BRIDGE_H */