1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
13 #include <asm-generic/pci-bridge.h>
18 * PCI controller operations
20 struct pci_controller_ops
{
21 void (*dma_dev_setup
)(struct pci_dev
*dev
);
22 void (*dma_bus_setup
)(struct pci_bus
*bus
);
24 int (*probe_mode
)(struct pci_bus
*);
26 /* Called when pci_enable_device() is called. Returns true to
27 * allow assignment/enabling of the device. */
28 bool (*enable_device_hook
)(struct pci_dev
*);
30 /* Called during PCI resource reassignment */
31 resource_size_t (*window_alignment
)(struct pci_bus
*, unsigned long type
);
32 void (*reset_secondary_bus
)(struct pci_dev
*dev
);
36 * Structure of a PCI controller (host bridge)
38 struct pci_controller
{
44 struct device_node
*dn
;
45 struct list_head list_node
;
46 struct device
*parent
;
53 void __iomem
*io_base_virt
;
57 resource_size_t io_base_phys
;
58 resource_size_t pci_io_size
;
60 /* Some machines have a special region to forward the ISA
61 * "memory" cycles such as VGA memory regions. Left to 0
64 resource_size_t isa_mem_phys
;
65 resource_size_t isa_mem_size
;
67 struct pci_controller_ops controller_ops
;
69 unsigned int __iomem
*cfg_addr
;
70 void __iomem
*cfg_data
;
73 * Used for variants of PCI indirect handling and possible quirks:
74 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
75 * EXT_REG - provides access to PCI-e extended registers
76 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
77 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
78 * to determine which bus number to match on when generating type0
80 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
81 * hanging if we don't have link and try to do config cycles to
82 * anything but the PHB. Only allow talking to the PHB if this is
84 * BIG_ENDIAN - cfg_addr is a big endian register
85 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
86 * the PLB4. Effectively disable MRM commands by setting this.
87 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
88 * link status is in a RC PCIe cfg register (vs being a SoC register)
90 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
91 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
92 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
93 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
94 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
95 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
96 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
98 /* Currently, we limit ourselves to 1 IO range and 3 mem
99 * ranges since the common pci_bus structure can't handle more
101 struct resource io_resource
;
102 struct resource mem_resources
[3];
103 resource_size_t mem_offset
[3];
104 int global_number
; /* PCI domain number */
106 resource_size_t dma_window_base_cur
;
107 resource_size_t dma_window_size
;
111 struct pci_dn
*pci_data
;
112 #endif /* CONFIG_PPC64 */
117 /* These are used for config access before all the PCI probing
119 extern int early_read_config_byte(struct pci_controller
*hose
, int bus
,
120 int dev_fn
, int where
, u8
*val
);
121 extern int early_read_config_word(struct pci_controller
*hose
, int bus
,
122 int dev_fn
, int where
, u16
*val
);
123 extern int early_read_config_dword(struct pci_controller
*hose
, int bus
,
124 int dev_fn
, int where
, u32
*val
);
125 extern int early_write_config_byte(struct pci_controller
*hose
, int bus
,
126 int dev_fn
, int where
, u8 val
);
127 extern int early_write_config_word(struct pci_controller
*hose
, int bus
,
128 int dev_fn
, int where
, u16 val
);
129 extern int early_write_config_dword(struct pci_controller
*hose
, int bus
,
130 int dev_fn
, int where
, u32 val
);
132 extern int early_find_capability(struct pci_controller
*hose
, int bus
,
133 int dev_fn
, int cap
);
135 extern void setup_indirect_pci(struct pci_controller
* hose
,
136 resource_size_t cfg_addr
,
137 resource_size_t cfg_data
, u32 flags
);
139 extern int indirect_read_config(struct pci_bus
*bus
, unsigned int devfn
,
140 int offset
, int len
, u32
*val
);
142 extern int __indirect_read_config(struct pci_controller
*hose
,
143 unsigned char bus_number
, unsigned int devfn
,
144 int offset
, int len
, u32
*val
);
146 extern int indirect_write_config(struct pci_bus
*bus
, unsigned int devfn
,
147 int offset
, int len
, u32 val
);
149 static inline struct pci_controller
*pci_bus_to_host(const struct pci_bus
*bus
)
156 extern int pci_device_from_OF_node(struct device_node
*node
,
158 extern void pci_create_OF_bus_map(void);
160 static inline int isa_vaddr_is_ioport(void __iomem
*address
)
162 /* No specific ISA handling on ppc32 at this stage, it
163 * all goes through PCI
168 #else /* CONFIG_PPC64 */
171 * PCI stuff, for nodes representing PCI devices, pointed to
172 * by device_node->data.
178 #define PCI_DN_FLAG_IOV_VF 0x01
180 int busno
; /* pci bus number */
181 int devfn
; /* pci device and function number */
182 int vendor_id
; /* Vendor ID */
183 int device_id
; /* Device ID */
184 int class_code
; /* Device class code */
186 struct pci_dn
*parent
;
187 struct pci_controller
*phb
; /* for pci devices */
188 struct iommu_table
*iommu_table
; /* for phb's or bridges */
189 struct device_node
*node
; /* back-pointer to the device_node */
191 int pci_ext_config_space
; /* for pci devices */
194 struct eeh_dev
*edev
; /* eeh device */
196 #define IODA_INVALID_PE (-1)
197 #ifdef CONFIG_PPC_POWERNV
199 #ifdef CONFIG_PCI_IOV
200 u16 vfs_expanded
; /* number of VFs IOV BAR expanded */
201 u16 num_vfs
; /* number of VFs enabled*/
202 int offset
; /* PE# for the first VF PE */
203 #define M64_PER_IOV 4
205 #define IODA_INVALID_M64 (-1)
206 int m64_wins
[PCI_SRIOV_NUM_BARS
][M64_PER_IOV
];
207 #endif /* CONFIG_PCI_IOV */
209 struct list_head child_list
;
210 struct list_head list
;
213 /* Get the pointer to a device_node's pci_dn */
214 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
216 extern struct pci_dn
*pci_get_pdn_by_devfn(struct pci_bus
*bus
,
218 extern struct pci_dn
*pci_get_pdn(struct pci_dev
*pdev
);
219 extern struct pci_dn
*add_dev_pci_data(struct pci_dev
*pdev
);
220 extern void remove_dev_pci_data(struct pci_dev
*pdev
);
221 extern void *update_dn_pci_info(struct device_node
*dn
, void *data
);
223 static inline int pci_device_from_OF_node(struct device_node
*np
,
228 *bus
= PCI_DN(np
)->busno
;
229 *devfn
= PCI_DN(np
)->devfn
;
233 #if defined(CONFIG_EEH)
234 static inline struct eeh_dev
*pdn_to_eeh_dev(struct pci_dn
*pdn
)
236 return pdn
? pdn
->edev
: NULL
;
239 #define pdn_to_eeh_dev(x) (NULL)
242 /** Find the bus corresponding to the indicated device node */
243 extern struct pci_bus
*pcibios_find_pci_bus(struct device_node
*dn
);
245 /** Remove all of the PCI devices under this bus */
246 extern void pcibios_remove_pci_devices(struct pci_bus
*bus
);
248 /** Discover new pci devices under this bus, and add them */
249 extern void pcibios_add_pci_devices(struct pci_bus
*bus
);
252 extern void isa_bridge_find_early(struct pci_controller
*hose
);
254 static inline int isa_vaddr_is_ioport(void __iomem
*address
)
256 /* Check if address hits the reserved legacy IO range */
257 unsigned long ea
= (unsigned long)address
;
258 return ea
>= ISA_IO_BASE
&& ea
< ISA_IO_END
;
261 extern int pcibios_unmap_io_space(struct pci_bus
*bus
);
262 extern int pcibios_map_io_space(struct pci_bus
*bus
);
265 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
267 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
270 #endif /* CONFIG_PPC64 */
272 /* Get the PCI host controller for an OF device */
273 extern struct pci_controller
*pci_find_hose_for_OF_device(
274 struct device_node
* node
);
276 /* Fill up host controller resources from the OF node */
277 extern void pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
278 struct device_node
*dev
, int primary
);
280 /* Allocate & free a PCI host bridge structure */
281 extern struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
);
282 extern void pcibios_free_controller(struct pci_controller
*phb
);
285 extern int pcibios_vaddr_is_ioport(void __iomem
*address
);
287 static inline int pcibios_vaddr_is_ioport(void __iomem
*address
)
291 #endif /* CONFIG_PCI */
293 #endif /* __KERNEL__ */
294 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */