1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
13 #include <asm-generic/pci-bridge.h>
18 * Structure of a PCI controller (host bridge)
20 struct pci_controller
{
26 struct device_node
*dn
;
27 struct list_head list_node
;
28 struct device
*parent
;
35 void __iomem
*io_base_virt
;
39 resource_size_t io_base_phys
;
40 resource_size_t pci_io_size
;
42 /* Some machines have a special region to forward the ISA
43 * "memory" cycles such as VGA memory regions. Left to 0
46 resource_size_t isa_mem_phys
;
47 resource_size_t isa_mem_size
;
50 unsigned int __iomem
*cfg_addr
;
51 void __iomem
*cfg_data
;
54 * Used for variants of PCI indirect handling and possible quirks:
55 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
56 * EXT_REG - provides access to PCI-e extended registers
57 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
58 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
59 * to determine which bus number to match on when generating type0
61 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
62 * hanging if we don't have link and try to do config cycles to
63 * anything but the PHB. Only allow talking to the PHB if this is
65 * BIG_ENDIAN - cfg_addr is a big endian register
66 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
67 * the PLB4. Effectively disable MRM commands by setting this.
68 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
69 * link status is in a RC PCIe cfg register (vs being a SoC register)
71 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
72 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
73 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
74 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
75 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
76 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
77 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
79 /* Currently, we limit ourselves to 1 IO range and 3 mem
80 * ranges since the common pci_bus structure can't handle more
82 struct resource io_resource
;
83 struct resource mem_resources
[3];
84 resource_size_t mem_offset
[3];
85 int global_number
; /* PCI domain number */
87 resource_size_t dma_window_base_cur
;
88 resource_size_t dma_window_size
;
92 struct pci_dn
*pci_data
;
93 #endif /* CONFIG_PPC64 */
98 /* These are used for config access before all the PCI probing
100 extern int early_read_config_byte(struct pci_controller
*hose
, int bus
,
101 int dev_fn
, int where
, u8
*val
);
102 extern int early_read_config_word(struct pci_controller
*hose
, int bus
,
103 int dev_fn
, int where
, u16
*val
);
104 extern int early_read_config_dword(struct pci_controller
*hose
, int bus
,
105 int dev_fn
, int where
, u32
*val
);
106 extern int early_write_config_byte(struct pci_controller
*hose
, int bus
,
107 int dev_fn
, int where
, u8 val
);
108 extern int early_write_config_word(struct pci_controller
*hose
, int bus
,
109 int dev_fn
, int where
, u16 val
);
110 extern int early_write_config_dword(struct pci_controller
*hose
, int bus
,
111 int dev_fn
, int where
, u32 val
);
113 extern int early_find_capability(struct pci_controller
*hose
, int bus
,
114 int dev_fn
, int cap
);
116 extern void setup_indirect_pci(struct pci_controller
* hose
,
117 resource_size_t cfg_addr
,
118 resource_size_t cfg_data
, u32 flags
);
120 extern int indirect_read_config(struct pci_bus
*bus
, unsigned int devfn
,
121 int offset
, int len
, u32
*val
);
123 extern int __indirect_read_config(struct pci_controller
*hose
,
124 unsigned char bus_number
, unsigned int devfn
,
125 int offset
, int len
, u32
*val
);
127 extern int indirect_write_config(struct pci_bus
*bus
, unsigned int devfn
,
128 int offset
, int len
, u32 val
);
130 static inline struct pci_controller
*pci_bus_to_host(const struct pci_bus
*bus
)
137 extern int pci_device_from_OF_node(struct device_node
*node
,
139 extern void pci_create_OF_bus_map(void);
141 static inline int isa_vaddr_is_ioport(void __iomem
*address
)
143 /* No specific ISA handling on ppc32 at this stage, it
144 * all goes through PCI
149 #else /* CONFIG_PPC64 */
152 * PCI stuff, for nodes representing PCI devices, pointed to
153 * by device_node->data.
159 #define PCI_DN_FLAG_IOV_VF 0x01
161 int busno
; /* pci bus number */
162 int devfn
; /* pci device and function number */
163 int vendor_id
; /* Vendor ID */
164 int device_id
; /* Device ID */
165 int class_code
; /* Device class code */
167 struct pci_dn
*parent
;
168 struct pci_controller
*phb
; /* for pci devices */
169 struct iommu_table
*iommu_table
; /* for phb's or bridges */
170 struct device_node
*node
; /* back-pointer to the device_node */
172 int pci_ext_config_space
; /* for pci devices */
174 struct pci_dev
*pcidev
; /* back-pointer to the pci device */
176 struct eeh_dev
*edev
; /* eeh device */
178 #define IODA_INVALID_PE (-1)
179 #ifdef CONFIG_PPC_POWERNV
182 struct list_head child_list
;
183 struct list_head list
;
186 /* Get the pointer to a device_node's pci_dn */
187 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
189 extern struct pci_dn
*pci_get_pdn_by_devfn(struct pci_bus
*bus
,
191 extern struct pci_dn
*pci_get_pdn(struct pci_dev
*pdev
);
192 extern struct pci_dn
*add_dev_pci_data(struct pci_dev
*pdev
);
193 extern void remove_dev_pci_data(struct pci_dev
*pdev
);
194 extern void *update_dn_pci_info(struct device_node
*dn
, void *data
);
196 static inline int pci_device_from_OF_node(struct device_node
*np
,
201 *bus
= PCI_DN(np
)->busno
;
202 *devfn
= PCI_DN(np
)->devfn
;
206 #if defined(CONFIG_EEH)
207 static inline struct eeh_dev
*pdn_to_eeh_dev(struct pci_dn
*pdn
)
209 return pdn
? pdn
->edev
: NULL
;
212 #define pdn_to_eeh_dev(x) (NULL)
215 /** Find the bus corresponding to the indicated device node */
216 extern struct pci_bus
*pcibios_find_pci_bus(struct device_node
*dn
);
218 /** Remove all of the PCI devices under this bus */
219 extern void pcibios_remove_pci_devices(struct pci_bus
*bus
);
221 /** Discover new pci devices under this bus, and add them */
222 extern void pcibios_add_pci_devices(struct pci_bus
*bus
);
225 extern void isa_bridge_find_early(struct pci_controller
*hose
);
227 static inline int isa_vaddr_is_ioport(void __iomem
*address
)
229 /* Check if address hits the reserved legacy IO range */
230 unsigned long ea
= (unsigned long)address
;
231 return ea
>= ISA_IO_BASE
&& ea
< ISA_IO_END
;
234 extern int pcibios_unmap_io_space(struct pci_bus
*bus
);
235 extern int pcibios_map_io_space(struct pci_bus
*bus
);
238 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
240 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
243 #endif /* CONFIG_PPC64 */
245 /* Get the PCI host controller for an OF device */
246 extern struct pci_controller
*pci_find_hose_for_OF_device(
247 struct device_node
* node
);
249 /* Fill up host controller resources from the OF node */
250 extern void pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
251 struct device_node
*dev
, int primary
);
253 /* Allocate & free a PCI host bridge structure */
254 extern struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
);
255 extern void pcibios_free_controller(struct pci_controller
*phb
);
258 extern int pcibios_vaddr_is_ioport(void __iomem
*address
);
260 static inline int pcibios_vaddr_is_ioport(void __iomem
*address
)
264 #endif /* CONFIG_PCI */
266 #endif /* __KERNEL__ */
267 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */