arch/powerpc/include/asm/pci-bridge.h

   1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
   2 #define _ASM_POWERPC_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/list.h>
  12 #include <linux/ioport.h>
  13 #include <asm-generic/pci-bridge.h>
  14
  15 /* Return values for pci_controller_ops.probe_mode function */
  16 #define PCI_PROBE_NONE          -1      /* Don't look at this bus at all */
  17 #define PCI_PROBE_NORMAL        0       /* Do normal PCI probing */
  18 #define PCI_PROBE_DEVTREE       1       /* Instantiate from device tree */
  19
  20 struct device_node;
  21
  22 /*
  23  * PCI controller operations
  24  */
  25 struct pci_controller_ops {
  26         void            (*dma_dev_setup)(struct pci_dev *dev);
  27         void            (*dma_bus_setup)(struct pci_bus *bus);
  28
  29         int             (*probe_mode)(struct pci_bus *);
  30
  31         /* Called when pci_enable_device() is called. Returns true to
  32          * allow assignment/enabling of the device. */
  33         bool            (*enable_device_hook)(struct pci_dev *);
  34
  35         /* Called during PCI resource reassignment */
  36         resource_size_t (*window_alignment)(struct pci_bus *, unsigned long type);
  37         void            (*reset_secondary_bus)(struct pci_dev *dev);
  38 };
  39
  40 /*
  41  * Structure of a PCI controller (host bridge)
  42  */
  43 struct pci_controller {
  44         struct pci_bus *bus;
  45         char is_dynamic;
  46 #ifdef CONFIG_PPC64
  47         int node;
  48 #endif
  49         struct device_node *dn;
  50         struct list_head list_node;
  51         struct device *parent;
  52
  53         int first_busno;
  54         int last_busno;
  55         int self_busno;
  56         struct resource busn;
  57
  58         void __iomem *io_base_virt;
  59 #ifdef CONFIG_PPC64
  60         void *io_base_alloc;
  61 #endif
  62         resource_size_t io_base_phys;
  63         resource_size_t pci_io_size;
  64
  65         /* Some machines have a special region to forward the ISA
  66          * "memory" cycles such as VGA memory regions. Left to 0
  67          * if unsupported
  68          */
  69         resource_size_t isa_mem_phys;
  70         resource_size_t isa_mem_size;
  71
  72         struct pci_controller_ops controller_ops;
  73         struct pci_ops *ops;
  74         unsigned int __iomem *cfg_addr;
  75         void __iomem *cfg_data;
  76
  77         /*
  78          * Used for variants of PCI indirect handling and possible quirks:
  79          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  80          *  EXT_REG - provides access to PCI-e extended registers
  81          *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  82          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  83          *   to determine which bus number to match on when generating type0
  84          *   config cycles
  85          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  86          *   hanging if we don't have link and try to do config cycles to
  87          *   anything but the PHB.  Only allow talking to the PHB if this is
  88          *   set.
  89          *  BIG_ENDIAN - cfg_addr is a big endian register
  90          *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
  91          *   the PLB4.  Effectively disable MRM commands by setting this.
  92          *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
  93          *   link status is in a RC PCIe cfg register (vs being a SoC register)
  94          */
  95 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
  96 #define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
  97 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
  98 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
  99 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
 100 #define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
 101 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK      0x00000040
 102         u32 indirect_type;
 103         /* Currently, we limit ourselves to 1 IO range and 3 mem
 104          * ranges since the common pci_bus structure can't handle more
 105          */
 106         struct resource io_resource;
 107         struct resource mem_resources[3];
 108         resource_size_t mem_offset[3];
 109         int global_number;              /* PCI domain number */
 110
 111         resource_size_t dma_window_base_cur;
 112         resource_size_t dma_window_size;
 113
 114 #ifdef CONFIG_PPC64
 115         unsigned long buid;
 116         struct pci_dn *pci_data;
 117 #endif  /* CONFIG_PPC64 */
 118
 119         void *private_data;
 120 };
 121
 122 /* These are used for config access before all the PCI probing
 123    has been done. */
 124 extern int early_read_config_byte(struct pci_controller *hose, int bus,
 125                         int dev_fn, int where, u8 *val);
 126 extern int early_read_config_word(struct pci_controller *hose, int bus,
 127                         int dev_fn, int where, u16 *val);
 128 extern int early_read_config_dword(struct pci_controller *hose, int bus,
 129                         int dev_fn, int where, u32 *val);
 130 extern int early_write_config_byte(struct pci_controller *hose, int bus,
 131                         int dev_fn, int where, u8 val);
 132 extern int early_write_config_word(struct pci_controller *hose, int bus,
 133                         int dev_fn, int where, u16 val);
 134 extern int early_write_config_dword(struct pci_controller *hose, int bus,
 135                         int dev_fn, int where, u32 val);
 136
 137 extern int early_find_capability(struct pci_controller *hose, int bus,
 138                                  int dev_fn, int cap);
 139
 140 extern void setup_indirect_pci(struct pci_controller* hose,
 141                                resource_size_t cfg_addr,
 142                                resource_size_t cfg_data, u32 flags);
 143
 144 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
 145                                 int offset, int len, u32 *val);
 146
 147 extern int __indirect_read_config(struct pci_controller *hose,
 148                                   unsigned char bus_number, unsigned int devfn,
 149                                   int offset, int len, u32 *val);
 150
 151 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
 152                                  int offset, int len, u32 val);
 153
 154 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 155 {
 156         return bus->sysdata;
 157 }
 158
 159 #ifndef CONFIG_PPC64
 160
 161 extern int pci_device_from_OF_node(struct device_node *node,
 162                                    u8 *bus, u8 *devfn);
 163 extern void pci_create_OF_bus_map(void);
 164
 165 static inline int isa_vaddr_is_ioport(void __iomem *address)
 166 {
 167         /* No specific ISA handling on ppc32 at this stage, it
 168          * all goes through PCI
 169          */
 170         return 0;
 171 }
 172
 173 #else   /* CONFIG_PPC64 */
 174
 175 /*
 176  * PCI stuff, for nodes representing PCI devices, pointed to
 177  * by device_node->data.
 178  */
 179 struct iommu_table;
 180
 181 struct pci_dn {
 182         int     flags;
 183
 184         int     busno;                  /* pci bus number */
 185         int     devfn;                  /* pci device and function number */
 186         int     vendor_id;              /* Vendor ID */
 187         int     device_id;              /* Device ID */
 188         int     class_code;             /* Device class code */
 189
 190         struct  pci_dn *parent;
 191         struct  pci_controller *phb;    /* for pci devices */
 192         struct  iommu_table *iommu_table;       /* for phb's or bridges */
 193         struct  device_node *node;      /* back-pointer to the device_node */
 194
 195         int     pci_ext_config_space;   /* for pci devices */
 196
 197         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 198 #ifdef CONFIG_EEH
 199         struct eeh_dev *edev;           /* eeh device */
 200 #endif
 201 #define IODA_INVALID_PE         (-1)
 202 #ifdef CONFIG_PPC_POWERNV
 203         int     pe_number;
 204 #endif
 205         struct list_head child_list;
 206         struct list_head list;
 207 };
 208
 209 /* Get the pointer to a device_node's pci_dn */
 210 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 211
 212 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
 213                                            int devfn);
 214 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
 215 extern void *update_dn_pci_info(struct device_node *dn, void *data);
 216
 217 static inline int pci_device_from_OF_node(struct device_node *np,
 218                                           u8 *bus, u8 *devfn)
 219 {
 220         if (!PCI_DN(np))
 221                 return -ENODEV;
 222         *bus = PCI_DN(np)->busno;
 223         *devfn = PCI_DN(np)->devfn;
 224         return 0;
 225 }
 226
 227 #if defined(CONFIG_EEH)
 228 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
 229 {
 230         return pdn ? pdn->edev : NULL;
 231 }
 232 #else
 233 #define pdn_to_eeh_dev(x)       (NULL)
 234 #endif
 235
 236 /** Find the bus corresponding to the indicated device node */
 237 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 238
 239 /** Remove all of the PCI devices under this bus */
 240 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
 241
 242 /** Discover new pci devices under this bus, and add them */
 243 extern void pcibios_add_pci_devices(struct pci_bus *bus);
 244
 245
 246 extern void isa_bridge_find_early(struct pci_controller *hose);
 247
 248 static inline int isa_vaddr_is_ioport(void __iomem *address)
 249 {
 250         /* Check if address hits the reserved legacy IO range */
 251         unsigned long ea = (unsigned long)address;
 252         return ea >= ISA_IO_BASE && ea < ISA_IO_END;
 253 }
 254
 255 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 256 extern int pcibios_map_io_space(struct pci_bus *bus);
 257
 258 #ifdef CONFIG_NUMA
 259 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 260 #else
 261 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
 262 #endif
 263
 264 #endif  /* CONFIG_PPC64 */
 265
 266 /* Get the PCI host controller for an OF device */
 267 extern struct pci_controller *pci_find_hose_for_OF_device(
 268                         struct device_node* node);
 269
 270 /* Fill up host controller resources from the OF node */
 271 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 272                         struct device_node *dev, int primary);
 273
 274 /* Allocate & free a PCI host bridge structure */
 275 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 276 extern void pcibios_free_controller(struct pci_controller *phb);
 277
 278 #ifdef CONFIG_PCI
 279 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 280 #else
 281 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 282 {
 283         return 0;
 284 }
 285 #endif  /* CONFIG_PCI */
 286
 287 /*
 288  * Shims to prefer pci_controller version over ppc_md where available.
 289  */
 290 static inline void pci_dma_dev_setup(struct pci_dev *dev)
 291 {
 292         struct pci_controller *phb = pci_bus_to_host(dev->bus);
 293
 294         if (phb->controller_ops.dma_dev_setup)
 295                 phb->controller_ops.dma_dev_setup(dev);
 296         else if (ppc_md.pci_dma_dev_setup)
 297                 ppc_md.pci_dma_dev_setup(dev);
 298 }
 299
 300 static inline void pci_dma_bus_setup(struct pci_bus *bus)
 301 {
 302         struct pci_controller *phb = pci_bus_to_host(bus);
 303
 304         if (phb->controller_ops.dma_bus_setup)
 305                 phb->controller_ops.dma_bus_setup(bus);
 306         else if (ppc_md.pci_dma_bus_setup)
 307                 ppc_md.pci_dma_bus_setup(bus);
 308 }
 309
 310 static inline int pci_probe_mode(struct pci_bus *bus)
 311 {
 312         struct pci_controller *phb = pci_bus_to_host(bus);
 313
 314         if (phb->controller_ops.probe_mode)
 315                 return phb->controller_ops.probe_mode(bus);
 316         if (ppc_md.pci_probe_mode)
 317                 return ppc_md.pci_probe_mode(bus);
 318         return PCI_PROBE_NORMAL;
 319 }
 320
 321 static inline bool pcibios_enable_device_hook(struct pci_dev *dev)
 322 {
 323         struct pci_controller *phb = pci_bus_to_host(dev->bus);
 324
 325         if (phb->controller_ops.enable_device_hook)
 326                 return phb->controller_ops.enable_device_hook(dev);
 327         if (ppc_md.pcibios_enable_device_hook)
 328                 return ppc_md.pcibios_enable_device_hook(dev);
 329         return true;
 330 }
 331
 332 static inline resource_size_t pci_window_alignment(struct pci_bus *bus,
 333                                                    unsigned long type)
 334 {
 335         struct pci_controller *phb = pci_bus_to_host(bus);
 336
 337         if (phb->controller_ops.window_alignment)
 338                 return phb->controller_ops.window_alignment(bus, type);
 339         if (ppc_md.pcibios_window_alignment)
 340                 return ppc_md.pcibios_window_alignment(bus, type);
 341
 342         /*
 343          * PCI core will figure out the default
 344          * alignment: 4KiB for I/O and 1MiB for
 345          * memory window.
 346          */
 347         return 1;
 348 }
 349
 350 static inline void pcibios_reset_secondary_bus_shim(struct pci_dev *dev)
 351 {
 352         struct pci_controller *phb = pci_bus_to_host(dev->bus);
 353
 354         if (phb->controller_ops.reset_secondary_bus)
 355                 phb->controller_ops.reset_secondary_bus(dev);
 356         else if (ppc_md.pcibios_reset_secondary_bus)
 357                 ppc_md.pcibios_reset_secondary_bus(dev);
 358         else
 359                 /*
 360                  * Fallback to the generic function if no
 361                  * platform-specific one is provided
 362                  */
 363                 pci_reset_secondary_bus(dev);
 364 }
 365
 366 #endif  /* __KERNEL__ */
 367 #endif  /* _ASM_POWERPC_PCI_BRIDGE_H */