arch/powerpc/include/asm/processor.h

   1 #ifndef _ASM_POWERPC_PROCESSOR_H
   2 #define _ASM_POWERPC_PROCESSOR_H
   3
   4 /*
   5  * Copyright (C) 2001 PPC 64 Team, IBM Corp
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12
  13 #include <asm/reg.h>
  14
  15 #ifdef CONFIG_VSX
  16 #define TS_FPRWIDTH 2
  17
  18 #ifdef __BIG_ENDIAN__
  19 #define TS_FPROFFSET 0
  20 #define TS_VSRLOWOFFSET 1
  21 #else
  22 #define TS_FPROFFSET 1
  23 #define TS_VSRLOWOFFSET 0
  24 #endif
  25
  26 #else
  27 #define TS_FPRWIDTH 1
  28 #define TS_FPROFFSET 0
  29 #endif
  30
  31 #ifdef CONFIG_PPC64
  32 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
  33 #define PPR_PRIORITY 3
  34 #ifdef __ASSEMBLY__
  35 #define INIT_PPR (PPR_PRIORITY << 50)
  36 #else
  37 #define INIT_PPR ((u64)PPR_PRIORITY << 50)
  38 #endif /* __ASSEMBLY__ */
  39 #endif /* CONFIG_PPC64 */
  40
  41 #ifndef __ASSEMBLY__
  42 #include <linux/compiler.h>
  43 #include <linux/cache.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/types.h>
  46 #include <asm/hw_breakpoint.h>
  47
  48 /* We do _not_ want to define new machine types at all, those must die
  49  * in favor of using the device-tree
  50  * -- BenH.
  51  */
  52
  53 /* PREP sub-platform types. Unused */
  54 #define _PREP_Motorola  0x01    /* motorola prep */
  55 #define _PREP_Firm      0x02    /* firmworks prep */
  56 #define _PREP_IBM       0x00    /* ibm prep */
  57 #define _PREP_Bull      0x03    /* bull prep */
  58
  59 /* CHRP sub-platform types. These are arbitrary */
  60 #define _CHRP_Motorola  0x04    /* motorola chrp, the cobra */
  61 #define _CHRP_IBM       0x05    /* IBM chrp, the longtrail and longtrail 2 */
  62 #define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
  63 #define _CHRP_briq      0x07    /* TotalImpact's briQ */
  64
  65 #if defined(__KERNEL__) && defined(CONFIG_PPC32)
  66
  67 extern int _chrp_type;
  68
  69 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
  70
  71 /*
  72  * Default implementation of macro that returns current
  73  * instruction pointer ("program counter").
  74  */
  75 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  76
  77 /* Macros for adjusting thread priority (hardware multi-threading) */
  78 #define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
  79 #define HMT_low()        asm volatile("or 1,1,1      # low priority")
  80 #define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
  81 #define HMT_medium()     asm volatile("or 2,2,2      # medium priority")
  82 #define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
  83 #define HMT_high()       asm volatile("or 3,3,3      # high priority")
  84
  85 #ifdef __KERNEL__
  86
  87 struct task_struct;
  88 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
  89 void release_thread(struct task_struct *);
  90
  91 #ifdef CONFIG_PPC32
  92
  93 #if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
  94 #error User TASK_SIZE overlaps with KERNEL_START address
  95 #endif
  96 #define TASK_SIZE       (CONFIG_TASK_SIZE)
  97
  98 /* This decides where the kernel will search for a free chunk of vm
  99  * space during mmap's.
 100  */
 101 #define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
 102 #endif
 103
 104 #ifdef CONFIG_PPC64
 105 /*
 106  * 64-bit user address space can have multiple limits
 107  * For now supported values are:
 108  */
 109 #define TASK_SIZE_64TB  (0x0000400000000000UL)
 110 #define TASK_SIZE_128TB (0x0000800000000000UL)
 111 #define TASK_SIZE_512TB (0x0002000000000000UL)
 112
 113 #ifdef CONFIG_PPC_BOOK3S_64
 114 /*
 115  * Max value currently used:
 116  */
 117 #define TASK_SIZE_USER64        TASK_SIZE_512TB
 118 #else
 119 #define TASK_SIZE_USER64        TASK_SIZE_64TB
 120 #endif
 121
 122 /*
 123  * 32-bit user address space is 4GB - 1 page
 124  * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 125  */
 126 #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
 127
 128 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
 129                 TASK_SIZE_USER32 : TASK_SIZE_USER64)
 130 #define TASK_SIZE         TASK_SIZE_OF(current)
 131 /* This decides where the kernel will search for a free chunk of vm
 132  * space during mmap's.
 133  */
 134 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
 135 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_128TB / 4))
 136
 137 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
 138                 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
 139 #endif
 140
 141 /*
 142  * Initial task size value for user applications. For book3s 64 we start
 143  * with 128TB and conditionally enable upto 512TB
 144  */
 145 #ifdef CONFIG_PPC_BOOK3S_64
 146 #define DEFAULT_MAP_WINDOW      ((is_32bit_task()) ? \
 147                                  TASK_SIZE_USER32 : TASK_SIZE_128TB)
 148 #else
 149 #define DEFAULT_MAP_WINDOW      TASK_SIZE
 150 #endif
 151
 152 #ifdef __powerpc64__
 153
 154 #ifdef CONFIG_PPC_BOOK3S_64
 155 /* Limit stack to 128TB */
 156 #define STACK_TOP_USER64 TASK_SIZE_128TB
 157 #else
 158 #define STACK_TOP_USER64 TASK_SIZE_USER64
 159 #endif
 160
 161 #define STACK_TOP_USER32 TASK_SIZE_USER32
 162
 163 #define STACK_TOP (is_32bit_task() ? \
 164                    STACK_TOP_USER32 : STACK_TOP_USER64)
 165
 166 #define STACK_TOP_MAX TASK_SIZE_USER64
 167
 168 #else /* __powerpc64__ */
 169
 170 #define STACK_TOP TASK_SIZE
 171 #define STACK_TOP_MAX   STACK_TOP
 172
 173 #endif /* __powerpc64__ */
 174
 175 typedef struct {
 176         unsigned long seg;
 177 } mm_segment_t;
 178
 179 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
 180 #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
 181
 182 /* FP and VSX 0-31 register set */
 183 struct thread_fp_state {
 184         u64     fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
 185         u64     fpscr;          /* Floating point status */
 186 };
 187
 188 /* Complete AltiVec register set including VSCR */
 189 struct thread_vr_state {
 190         vector128       vr[32] __attribute__((aligned(16)));
 191         vector128       vscr __attribute__((aligned(16)));
 192 };
 193
 194 struct debug_reg {
 195 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 196         /*
 197          * The following help to manage the use of Debug Control Registers
 198          * om the BookE platforms.
 199          */
 200         uint32_t        dbcr0;
 201         uint32_t        dbcr1;
 202 #ifdef CONFIG_BOOKE
 203         uint32_t        dbcr2;
 204 #endif
 205         /*
 206          * The stored value of the DBSR register will be the value at the
 207          * last debug interrupt. This register can only be read from the
 208          * user (will never be written to) and has value while helping to
 209          * describe the reason for the last debug trap.  Torez
 210          */
 211         uint32_t        dbsr;
 212         /*
 213          * The following will contain addresses used by debug applications
 214          * to help trace and trap on particular address locations.
 215          * The bits in the Debug Control Registers above help define which
 216          * of the following registers will contain valid data and/or addresses.
 217          */
 218         unsigned long   iac1;
 219         unsigned long   iac2;
 220 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 221         unsigned long   iac3;
 222         unsigned long   iac4;
 223 #endif
 224         unsigned long   dac1;
 225         unsigned long   dac2;
 226 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 227         unsigned long   dvc1;
 228         unsigned long   dvc2;
 229 #endif
 230 #endif
 231 };
 232
 233 struct thread_struct {
 234         unsigned long   ksp;            /* Kernel stack pointer */
 235
 236 #ifdef CONFIG_PPC64
 237         unsigned long   ksp_vsid;
 238 #endif
 239         struct pt_regs  *regs;          /* Pointer to saved register state */
 240         mm_segment_t    fs;             /* for get_fs() validation */
 241 #ifdef CONFIG_BOOKE
 242         /* BookE base exception scratch space; align on cacheline */
 243         unsigned long   normsave[8] ____cacheline_aligned;
 244 #endif
 245 #ifdef CONFIG_PPC32
 246         void            *pgdir;         /* root of page-table tree */
 247         unsigned long   ksp_limit;      /* if ksp <= ksp_limit stack overflow */
 248 #endif
 249         /* Debug Registers */
 250         struct debug_reg debug;
 251         struct thread_fp_state  fp_state;
 252         struct thread_fp_state  *fp_save_area;
 253         int             fpexc_mode;     /* floating-point exception mode */
 254         unsigned int    align_ctl;      /* alignment handling control */
 255 #ifdef CONFIG_PPC64
 256         unsigned long   start_tb;       /* Start purr when proc switched in */
 257         unsigned long   accum_tb;       /* Total accumulated purr for process */
 258 #endif
 259 #ifdef CONFIG_HAVE_HW_BREAKPOINT
 260         struct perf_event *ptrace_bps[HBP_NUM];
 261         /*
 262          * Helps identify source of single-step exception and subsequent
 263          * hw-breakpoint enablement
 264          */
 265         struct perf_event *last_hit_ubp;
 266 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 267         struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
 268         unsigned long   trap_nr;        /* last trap # on this thread */
 269         u8 load_fp;
 270 #ifdef CONFIG_ALTIVEC
 271         u8 load_vec;
 272         struct thread_vr_state vr_state;
 273         struct thread_vr_state *vr_save_area;
 274         unsigned long   vrsave;
 275         int             used_vr;        /* set if process has used altivec */
 276 #endif /* CONFIG_ALTIVEC */
 277 #ifdef CONFIG_VSX
 278         /* VSR status */
 279         int             used_vsr;       /* set if process has used VSX */
 280 #endif /* CONFIG_VSX */
 281 #ifdef CONFIG_SPE
 282         unsigned long   evr[32];        /* upper 32-bits of SPE regs */
 283         u64             acc;            /* Accumulator */
 284         unsigned long   spefscr;        /* SPE & eFP status */
 285         unsigned long   spefscr_last;   /* SPEFSCR value on last prctl
 286                                            call or trap return */
 287         int             used_spe;       /* set if process has used spe */
 288 #endif /* CONFIG_SPE */
 289 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 290         u8      load_tm;
 291         u64             tm_tfhar;       /* Transaction fail handler addr */
 292         u64             tm_texasr;      /* Transaction exception & summary */
 293         u64             tm_tfiar;       /* Transaction fail instr address reg */
 294         struct pt_regs  ckpt_regs;      /* Checkpointed registers */
 295
 296         unsigned long   tm_tar;
 297         unsigned long   tm_ppr;
 298         unsigned long   tm_dscr;
 299
 300         /*
 301          * Checkpointed FP and VSX 0-31 register set.
 302          *
 303          * When a transaction is active/signalled/scheduled etc., *regs is the
 304          * most recent set of/speculated GPRs with ckpt_regs being the older
 305          * checkpointed regs to which we roll back if transaction aborts.
 306          *
 307          * These are analogous to how ckpt_regs and pt_regs work
 308          */
 309         struct thread_fp_state ckfp_state; /* Checkpointed FP state */
 310         struct thread_vr_state ckvr_state; /* Checkpointed VR state */
 311         unsigned long   ckvrsave; /* Checkpointed VRSAVE */
 312 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 313 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
 314         void*           kvm_shadow_vcpu; /* KVM internal data */
 315 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
 316 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
 317         struct kvm_vcpu *kvm_vcpu;
 318 #endif
 319 #ifdef CONFIG_PPC64
 320         unsigned long   dscr;
 321         unsigned long   fscr;
 322         /*
 323          * This member element dscr_inherit indicates that the process
 324          * has explicitly attempted and changed the DSCR register value
 325          * for itself. Hence kernel wont use the default CPU DSCR value
 326          * contained in the PACA structure anymore during process context
 327          * switch. Once this variable is set, this behaviour will also be
 328          * inherited to all the children of this process from that point
 329          * onwards.
 330          */
 331         int             dscr_inherit;
 332         unsigned long   ppr;    /* used to save/restore SMT priority */
 333 #endif
 334 #ifdef CONFIG_PPC_BOOK3S_64
 335         unsigned long   tar;
 336         unsigned long   ebbrr;
 337         unsigned long   ebbhr;
 338         unsigned long   bescr;
 339         unsigned long   siar;
 340         unsigned long   sdar;
 341         unsigned long   sier;
 342         unsigned long   mmcr2;
 343         unsigned        mmcr0;
 344         unsigned        used_ebb;
 345 #endif
 346 };
 347
 348 #define ARCH_MIN_TASKALIGN 16
 349
 350 #define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 351 #define INIT_SP_LIMIT \
 352         (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
 353
 354 #ifdef CONFIG_SPE
 355 #define SPEFSCR_INIT \
 356         .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
 357         .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
 358 #else
 359 #define SPEFSCR_INIT
 360 #endif
 361
 362 #ifdef CONFIG_PPC32
 363 #define INIT_THREAD { \
 364         .ksp = INIT_SP, \
 365         .ksp_limit = INIT_SP_LIMIT, \
 366         .fs = KERNEL_DS, \
 367         .pgdir = swapper_pg_dir, \
 368         .fpexc_mode = MSR_FE0 | MSR_FE1, \
 369         SPEFSCR_INIT \
 370 }
 371 #else
 372 #define INIT_THREAD  { \
 373         .ksp = INIT_SP, \
 374         .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
 375         .fs = KERNEL_DS, \
 376         .fpexc_mode = 0, \
 377         .ppr = INIT_PPR, \
 378         .fscr = FSCR_TAR | FSCR_EBB \
 379 }
 380 #endif
 381
 382 /*
 383  * Return saved PC of a blocked thread. For now, this is the "user" PC
 384  */
 385 #define thread_saved_pc(tsk)    \
 386         ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 387
 388 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.regs)
 389
 390 unsigned long get_wchan(struct task_struct *p);
 391
 392 #define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 393 #define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 394
 395 /* Get/set floating-point exception mode */
 396 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
 397 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
 398
 399 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 400 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
 401
 402 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
 403 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
 404
 405 extern int get_endian(struct task_struct *tsk, unsigned long adr);
 406 extern int set_endian(struct task_struct *tsk, unsigned int val);
 407
 408 #define GET_UNALIGN_CTL(tsk, adr)       get_unalign_ctl((tsk), (adr))
 409 #define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
 410
 411 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
 412 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
 413
 414 extern void load_fp_state(struct thread_fp_state *fp);
 415 extern void store_fp_state(struct thread_fp_state *fp);
 416 extern void load_vr_state(struct thread_vr_state *vr);
 417 extern void store_vr_state(struct thread_vr_state *vr);
 418
 419 static inline unsigned int __unpack_fe01(unsigned long msr_bits)
 420 {
 421         return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
 422 }
 423
 424 static inline unsigned long __pack_fe01(unsigned int fpmode)
 425 {
 426         return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
 427 }
 428
 429 #ifdef CONFIG_PPC64
 430 #define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
 431 #else
 432 #define cpu_relax()     barrier()
 433 #endif
 434
 435 /* Check that a certain kernel stack pointer is valid in task_struct p */
 436 int validate_sp(unsigned long sp, struct task_struct *p,
 437                        unsigned long nbytes);
 438
 439 /*
 440  * Prefetch macros.
 441  */
 442 #define ARCH_HAS_PREFETCH
 443 #define ARCH_HAS_PREFETCHW
 444 #define ARCH_HAS_SPINLOCK_PREFETCH
 445
 446 static inline void prefetch(const void *x)
 447 {
 448         if (unlikely(!x))
 449                 return;
 450
 451         __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 452 }
 453
 454 static inline void prefetchw(const void *x)
 455 {
 456         if (unlikely(!x))
 457                 return;
 458
 459         __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 460 }
 461
 462 #define spin_lock_prefetch(x)   prefetchw(x)
 463
 464 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 465
 466 #ifdef CONFIG_PPC64
 467 static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
 468 {
 469         if (is_32)
 470                 return sp & 0x0ffffffffUL;
 471         return sp;
 472 }
 473 #else
 474 static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
 475 {
 476         return sp;
 477 }
 478 #endif
 479
 480 extern unsigned long cpuidle_disable;
 481 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 482
 483 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 484 extern unsigned long power7_nap(int check_irq);
 485 extern unsigned long power7_sleep(void);
 486 extern unsigned long power7_winkle(void);
 487 extern unsigned long power9_idle_stop(unsigned long stop_psscr_val,
 488                                       unsigned long stop_psscr_mask);
 489
 490 extern void flush_instruction_cache(void);
 491 extern void hard_reset_now(void);
 492 extern void poweroff_now(void);
 493 extern int fix_alignment(struct pt_regs *);
 494 extern void cvt_fd(float *from, double *to);
 495 extern void cvt_df(double *from, float *to);
 496 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 497
 498 #ifdef CONFIG_PPC64
 499 /*
 500  * We handle most unaligned accesses in hardware. On the other hand
 501  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 502  * powers of 2 writes until it reaches sufficient alignment).
 503  *
 504  * Based on this we disable the IP header alignment in network drivers.
 505  */
 506 #define NET_IP_ALIGN    0
 507 #endif
 508
 509 #endif /* __KERNEL__ */
 510 #endif /* __ASSEMBLY__ */
 511 #endif /* _ASM_POWERPC_PROCESSOR_H */