arch/powerpc/include/asm/smu.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _SMU_H
   3 #define _SMU_H
   4
   5 /*
   6  * Definitions for talking to the SMU chip in newer G5 PowerMacs
   7  */
   8 #ifdef __KERNEL__
   9 #include <linux/list.h>
  10 #endif
  11 #include <linux/types.h>
  12
  13 /*
  14  * Known SMU commands
  15  *
  16  * Most of what is below comes from looking at the Open Firmware driver,
  17  * though this is still incomplete and could use better documentation here
  18  * or there...
  19  */
  20
  21
  22 /*
  23  * Partition info commands
  24  *
  25  * These commands are used to retrieve the sdb-partition-XX datas from
  26  * the SMU. The length is always 2. First byte is the subcommand code
  27  * and second byte is the partition ID.
  28  *
  29  * The reply is 6 bytes:
  30  *
  31  *  - 0..1 : partition address
  32  *  - 2    : a byte containing the partition ID
  33  *  - 3    : length (maybe other bits are rest of header ?)
  34  *
  35  * The data must then be obtained with calls to another command:
  36  * SMU_CMD_MISC_ee_GET_DATABLOCK_REC (described below).
  37  */
  38 #define SMU_CMD_PARTITION_COMMAND               0x3e
  39 #define   SMU_CMD_PARTITION_LATEST              0x01
  40 #define   SMU_CMD_PARTITION_BASE                0x02
  41 #define   SMU_CMD_PARTITION_UPDATE              0x03
  42
  43
  44 /*
  45  * Fan control
  46  *
  47  * This is a "mux" for fan control commands. The command seem to
  48  * act differently based on the number of arguments. With 1 byte
  49  * of argument, this seem to be queries for fans status, setpoint,
  50  * etc..., while with 0xe arguments, we will set the fans speeds.
  51  *
  52  * Queries (1 byte arg):
  53  * ---------------------
  54  *
  55  * arg=0x01: read RPM fans status
  56  * arg=0x02: read RPM fans setpoint
  57  * arg=0x11: read PWM fans status
  58  * arg=0x12: read PWM fans setpoint
  59  *
  60  * the "status" queries return the current speed while the "setpoint" ones
  61  * return the programmed/target speed. It _seems_ that the result is a bit
  62  * mask in the first byte of active/available fans, followed by 6 words (16
  63  * bits) containing the requested speed.
  64  *
  65  * Setpoint (14 bytes arg):
  66  * ------------------------
  67  *
  68  * first arg byte is 0 for RPM fans and 0x10 for PWM. Second arg byte is the
  69  * mask of fans affected by the command. Followed by 6 words containing the
  70  * setpoint value for selected fans in the mask (or 0 if mask value is 0)
  71  */
  72 #define SMU_CMD_FAN_COMMAND                     0x4a
  73
  74
  75 /*
  76  * Battery access
  77  *
  78  * Same command number as the PMU, could it be same syntax ?
  79  */
  80 #define SMU_CMD_BATTERY_COMMAND                 0x6f
  81 #define   SMU_CMD_GET_BATTERY_INFO              0x00
  82
  83 /*
  84  * Real time clock control
  85  *
  86  * This is a "mux", first data byte contains the "sub" command.
  87  * The "RTC" part of the SMU controls the date, time, powerup
  88  * timer, but also a PRAM
  89  *
  90  * Dates are in BCD format on 7 bytes:
  91  * [sec] [min] [hour] [weekday] [month day] [month] [year]
  92  * with month being 1 based and year minus 100
  93  */
  94 #define SMU_CMD_RTC_COMMAND                     0x8e
  95 #define   SMU_CMD_RTC_SET_PWRUP_TIMER           0x00 /* i: 7 bytes date */
  96 #define   SMU_CMD_RTC_GET_PWRUP_TIMER           0x01 /* o: 7 bytes date */
  97 #define   SMU_CMD_RTC_STOP_PWRUP_TIMER          0x02
  98 #define   SMU_CMD_RTC_SET_PRAM_BYTE_ACC         0x20 /* i: 1 byte (address?) */
  99 #define   SMU_CMD_RTC_SET_PRAM_AUTOINC          0x21 /* i: 1 byte (data?) */
 100 #define   SMU_CMD_RTC_SET_PRAM_LO_BYTES         0x22 /* i: 10 bytes */
 101 #define   SMU_CMD_RTC_SET_PRAM_HI_BYTES         0x23 /* i: 10 bytes */
 102 #define   SMU_CMD_RTC_GET_PRAM_BYTE             0x28 /* i: 1 bytes (address?) */
 103 #define   SMU_CMD_RTC_GET_PRAM_LO_BYTES         0x29 /* o: 10 bytes */
 104 #define   SMU_CMD_RTC_GET_PRAM_HI_BYTES         0x2a /* o: 10 bytes */
 105 #define   SMU_CMD_RTC_SET_DATETIME              0x80 /* i: 7 bytes date */
 106 #define   SMU_CMD_RTC_GET_DATETIME              0x81 /* o: 7 bytes date */
 107
 108  /*
 109   * i2c commands
 110   *
 111   * To issue an i2c command, first is to send a parameter block to the
 112   * the SMU. This is a command of type 0x9a with 9 bytes of header
 113   * eventually followed by data for a write:
 114   *
 115   * 0: bus number (from device-tree usually, SMU has lots of busses !)
 116   * 1: transfer type/format (see below)
 117   * 2: device address. For combined and combined4 type transfers, this
 118   *    is the "write" version of the address (bit 0x01 cleared)
 119   * 3: subaddress length (0..3)
 120   * 4: subaddress byte 0 (or only byte for subaddress length 1)
 121   * 5: subaddress byte 1
 122   * 6: subaddress byte 2
 123   * 7: combined address (device address for combined mode data phase)
 124   * 8: data length
 125   *
 126   * The transfer types are the same good old Apple ones it seems,
 127   * that is:
 128   *   - 0x00: Simple transfer
 129   *   - 0x01: Subaddress transfer (addr write + data tx, no restart)
 130   *   - 0x02: Combined transfer (addr write + restart + data tx)
 131   *
 132   * This is then followed by actual data for a write.
 133   *
 134   * At this point, the OF driver seems to have a limitation on transfer
 135   * sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know
 136   * whether this is just an OF limit due to some temporary buffer size
 137   * or if this is an SMU imposed limit. This driver has the same limitation
 138   * for now as I use a 0x10 bytes temporary buffer as well
 139   *
 140   * Once that is completed, a response is expected from the SMU. This is
 141   * obtained via a command of type 0x9a with a length of 1 byte containing
 142   * 0 as the data byte. OF also fills the rest of the data buffer with 0xff's
 143   * though I can't tell yet if this is actually necessary. Once this command
 144   * is complete, at this point, all I can tell is what OF does. OF tests
 145   * byte 0 of the reply:
 146   *   - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ?
 147   *   - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0)
 148   *   - on write, < 0 -> failure (immediate exit)
 149   *   - else, OF just exists (without error, weird)
 150   *
 151   * So on read, there is this wait-for-busy thing when getting a 0xfc or
 152   * 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and
 153   * doing the above again until either the retries expire or the result
 154   * is no longer 0xfe or 0xfc
 155   *
 156   * The Darwin I2C driver is less subtle though. On any non-success status
 157   * from the response command, it waits 5ms and tries again up to 20 times,
 158   * it doesn't differentiate between fatal errors or "busy" status.
 159   *
 160   * This driver provides an asynchronous paramblock based i2c command
 161   * interface to be used either directly by low level code or by a higher
 162   * level driver interfacing to the linux i2c layer. The current
 163   * implementation of this relies on working timers & timer interrupts
 164   * though, so be careful of calling context for now. This may be "fixed"
 165   * in the future by adding a polling facility.
 166   */
 167 #define SMU_CMD_I2C_COMMAND                     0x9a
 168           /* transfer types */
 169 #define   SMU_I2C_TRANSFER_SIMPLE       0x00
 170 #define   SMU_I2C_TRANSFER_STDSUB       0x01
 171 #define   SMU_I2C_TRANSFER_COMBINED     0x02
 172
 173 /*
 174  * Power supply control
 175  *
 176  * The "sub" command is an ASCII string in the data, the
 177  * data length is that of the string.
 178  *
 179  * The VSLEW command can be used to get or set the voltage slewing.
 180  *  - length 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
 181  *    reply at data offset 6, 7 and 8.
 182  *  - length 8 ("VSLEWxyz") has 3 additional bytes appended, and is
 183  *    used to set the voltage slewing point. The SMU replies with "DONE"
 184  * I yet have to figure out their exact meaning of those 3 bytes in
 185  * both cases. They seem to be:
 186  *  x = processor mask
 187  *  y = op. point index
 188  *  z = processor freq. step index
 189  * I haven't yet deciphered result codes
 190  *
 191  */
 192 #define SMU_CMD_POWER_COMMAND                   0xaa
 193 #define   SMU_CMD_POWER_RESTART                 "RESTART"
 194 #define   SMU_CMD_POWER_SHUTDOWN                "SHUTDOWN"
 195 #define   SMU_CMD_POWER_VOLTAGE_SLEW            "VSLEW"
 196
 197 /*
 198  * Read ADC sensors
 199  *
 200  * This command takes one byte of parameter: the sensor ID (or "reg"
 201  * value in the device-tree) and returns a 16 bits value
 202  */
 203 #define SMU_CMD_READ_ADC                        0xd8
 204
 205
 206 /* Misc commands
 207  *
 208  * This command seem to be a grab bag of various things
 209  *
 210  * Parameters:
 211  *   1: subcommand
 212  */
 213 #define SMU_CMD_MISC_df_COMMAND                 0xdf
 214
 215 /*
 216  * Sets "system ready" status
 217  *
 218  * I did not yet understand how it exactly works or what it does.
 219  *
 220  * Guessing from OF code, 0x02 activates the display backlight. Apple uses/used
 221  * the same codebase for all OF versions. On PowerBooks, this command would
 222  * enable the backlight. For the G5s, it only activates the front LED. However,
 223  * don't take this for granted.
 224  *
 225  * Parameters:
 226  *   2: status [0x00, 0x01 or 0x02]
 227  */
 228 #define   SMU_CMD_MISC_df_SET_DISPLAY_LIT       0x02
 229
 230 /*
 231  * Sets mode of power switch.
 232  *
 233  * What this actually does is not yet known. Maybe it enables some interrupt.
 234  *
 235  * Parameters:
 236  *   2: enable power switch? [0x00 or 0x01]
 237  *   3 (optional): enable nmi? [0x00 or 0x01]
 238  *
 239  * Returns:
 240  *   If parameter 2 is 0x00 and parameter 3 is not specified, returns whether
 241  *   NMI is enabled. Otherwise unknown.
 242  */
 243 #define   SMU_CMD_MISC_df_NMI_OPTION            0x04
 244
 245 /* Sets LED dimm offset.
 246  *
 247  * The front LED dimms itself during sleep. Its brightness (or, well, the PWM
 248  * frequency) depends on current time. Therefore, the SMU needs to know the
 249  * timezone.
 250  *
 251  * Parameters:
 252  *   2-8: unknown (BCD coding)
 253  */
 254 #define   SMU_CMD_MISC_df_DIMM_OFFSET           0x99
 255
 256
 257 /*
 258  * Version info commands
 259  *
 260  * Parameters:
 261  *   1 (optional): Specifies version part to retrieve
 262  *
 263  * Returns:
 264  *   Version value
 265  */
 266 #define SMU_CMD_VERSION_COMMAND                 0xea
 267 #define   SMU_VERSION_RUNNING                   0x00
 268 #define   SMU_VERSION_BASE                      0x01
 269 #define   SMU_VERSION_UPDATE                    0x02
 270
 271
 272 /*
 273  * Switches
 274  *
 275  * These are switches whose status seems to be known to the SMU.
 276  *
 277  * Parameters:
 278  *   none
 279  *
 280  * Result:
 281  *   Switch bits (ORed, see below)
 282  */
 283 #define SMU_CMD_SWITCHES                        0xdc
 284
 285 /* Switches bits */
 286 #define SMU_SWITCH_CASE_CLOSED                  0x01
 287 #define SMU_SWITCH_AC_POWER                     0x04
 288 #define SMU_SWITCH_POWER_SWITCH                 0x08
 289
 290
 291 /*
 292  * Misc commands
 293  *
 294  * This command seem to be a grab bag of various things
 295  *
 296  * SMU_CMD_MISC_ee_GET_DATABLOCK_REC is used, among others, to
 297  * transfer blocks of data from the SMU. So far, I've decrypted it's
 298  * usage to retrieve partition data. In order to do that, you have to
 299  * break your transfer in "chunks" since that command cannot transfer
 300  * more than a chunk at a time. The chunk size used by OF is 0xe bytes,
 301  * but it seems that the darwin driver will let you do 0x1e bytes if
 302  * your "PMU" version is >= 0x30. You can get the "PMU" version apparently
 303  * either in the last 16 bits of property "smu-version-pmu" or as the 16
 304  * bytes at offset 1 of "smu-version-info"
 305  *
 306  * For each chunk, the command takes 7 bytes of arguments:
 307  *  byte 0: subcommand code (0x02)
 308  *  byte 1: 0x04 (always, I don't know what it means, maybe the address
 309  *                space to use or some other nicety. It's hard coded in OF)
 310  *  byte 2..5: SMU address of the chunk (big endian 32 bits)
 311  *  byte 6: size to transfer (up to max chunk size)
 312  *
 313  * The data is returned directly
 314  */
 315 #define SMU_CMD_MISC_ee_COMMAND                 0xee
 316 #define   SMU_CMD_MISC_ee_GET_DATABLOCK_REC     0x02
 317
 318 /* Retrieves currently used watts.
 319  *
 320  * Parameters:
 321  *   1: 0x03 (Meaning unknown)
 322  */
 323 #define   SMU_CMD_MISC_ee_GET_WATTS             0x03
 324
 325 #define   SMU_CMD_MISC_ee_LEDS_CTRL             0x04 /* i: 00 (00,01) [00] */
 326 #define   SMU_CMD_MISC_ee_GET_DATA              0x05 /* i: 00 , o: ?? */
 327
 328
 329 /*
 330  * Power related commands
 331  *
 332  * Parameters:
 333  *   1: subcommand
 334  */
 335 #define SMU_CMD_POWER_EVENTS_COMMAND            0x8f
 336
 337 /* SMU_POWER_EVENTS subcommands */
 338 enum {
 339         SMU_PWR_GET_POWERUP_EVENTS      = 0x00,
 340         SMU_PWR_SET_POWERUP_EVENTS      = 0x01,
 341         SMU_PWR_CLR_POWERUP_EVENTS      = 0x02,
 342         SMU_PWR_GET_WAKEUP_EVENTS       = 0x03,
 343         SMU_PWR_SET_WAKEUP_EVENTS       = 0x04,
 344         SMU_PWR_CLR_WAKEUP_EVENTS       = 0x05,
 345
 346         /*
 347          * Get last shutdown cause
 348          *
 349          * Returns:
 350          *   1 byte (signed char): Last shutdown cause. Exact meaning unknown.
 351          */
 352         SMU_PWR_LAST_SHUTDOWN_CAUSE     = 0x07,
 353
 354         /*
 355          * Sets or gets server ID. Meaning or use is unknown.
 356          *
 357          * Parameters:
 358          *   2 (optional): Set server ID (1 byte)
 359          *
 360          * Returns:
 361          *   1 byte (server ID?)
 362          */
 363         SMU_PWR_SERVER_ID               = 0x08,
 364 };
 365
 366 /* Power events wakeup bits */
 367 enum {
 368         SMU_PWR_WAKEUP_KEY              = 0x01, /* Wake on key press */
 369         SMU_PWR_WAKEUP_AC_INSERT        = 0x02, /* Wake on AC adapter plug */
 370         SMU_PWR_WAKEUP_AC_CHANGE        = 0x04,
 371         SMU_PWR_WAKEUP_LID_OPEN         = 0x08,
 372         SMU_PWR_WAKEUP_RING             = 0x10,
 373 };
 374
 375
 376 /*
 377  * - Kernel side interface -
 378  */
 379
 380 #ifdef __KERNEL__
 381
 382 /*
 383  * Asynchronous SMU commands
 384  *
 385  * Fill up this structure and submit it via smu_queue_command(),
 386  * and get notified by the optional done() callback, or because
 387  * status becomes != 1
 388  */
 389
 390 struct smu_cmd;
 391
 392 struct smu_cmd
 393 {
 394         /* public */
 395         u8                      cmd;            /* command */
 396         int                     data_len;       /* data len */
 397         int                     reply_len;      /* reply len */
 398         void                    *data_buf;      /* data buffer */
 399         void                    *reply_buf;     /* reply buffer */
 400         int                     status;         /* command status */
 401         void                    (*done)(struct smu_cmd *cmd, void *misc);
 402         void                    *misc;
 403
 404         /* private */
 405         struct list_head        link;
 406 };
 407
 408 /*
 409  * Queues an SMU command, all fields have to be initialized
 410  */
 411 extern int smu_queue_cmd(struct smu_cmd *cmd);
 412
 413 /*
 414  * Simple command wrapper. This structure embeds a small buffer
 415  * to ease sending simple SMU commands from the stack
 416  */
 417 struct smu_simple_cmd
 418 {
 419         struct smu_cmd  cmd;
 420         u8              buffer[16];
 421 };
 422
 423 /*
 424  * Queues a simple command. All fields will be initialized by that
 425  * function
 426  */
 427 extern int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command,
 428                             unsigned int data_len,
 429                             void (*done)(struct smu_cmd *cmd, void *misc),
 430                             void *misc,
 431                             ...);
 432
 433 /*
 434  * Completion helper. Pass it to smu_queue_simple or as 'done'
 435  * member to smu_queue_cmd, it will call complete() on the struct
 436  * completion passed in the "misc" argument
 437  */
 438 extern void smu_done_complete(struct smu_cmd *cmd, void *misc);
 439
 440 /*
 441  * Synchronous helpers. Will spin-wait for completion of a command
 442  */
 443 extern void smu_spinwait_cmd(struct smu_cmd *cmd);
 444
 445 static inline void smu_spinwait_simple(struct smu_simple_cmd *scmd)
 446 {
 447         smu_spinwait_cmd(&scmd->cmd);
 448 }
 449
 450 /*
 451  * Poll routine to call if blocked with irqs off
 452  */
 453 extern void smu_poll(void);
 454
 455
 456 /*
 457  * Init routine, presence check....
 458  */
 459 extern int smu_init(void);
 460 extern int smu_present(void);
 461 struct platform_device;
 462 extern struct platform_device *smu_get_ofdev(void);
 463
 464
 465 /*
 466  * Common command wrappers
 467  */
 468 extern void smu_shutdown(void);
 469 extern void smu_restart(void);
 470 struct rtc_time;
 471 extern int smu_get_rtc_time(struct rtc_time *time, int spinwait);
 472 extern int smu_set_rtc_time(struct rtc_time *time, int spinwait);
 473
 474 /*
 475  * Kernel asynchronous i2c interface
 476  */
 477
 478 #define SMU_I2C_READ_MAX        0x1d
 479 #define SMU_I2C_WRITE_MAX       0x15
 480
 481 /* SMU i2c header, exactly matches i2c header on wire */
 482 struct smu_i2c_param
 483 {
 484         u8      bus;            /* SMU bus ID (from device tree) */
 485         u8      type;           /* i2c transfer type */
 486         u8      devaddr;        /* device address (includes direction) */
 487         u8      sublen;         /* subaddress length */
 488         u8      subaddr[3];     /* subaddress */
 489         u8      caddr;          /* combined address, filled by SMU driver */
 490         u8      datalen;        /* length of transfer */
 491         u8      data[SMU_I2C_READ_MAX]; /* data */
 492 };
 493
 494 struct smu_i2c_cmd
 495 {
 496         /* public */
 497         struct smu_i2c_param    info;
 498         void                    (*done)(struct smu_i2c_cmd *cmd, void *misc);
 499         void                    *misc;
 500         int                     status; /* 1 = pending, 0 = ok, <0 = fail */
 501
 502         /* private */
 503         struct smu_cmd          scmd;
 504         int                     read;
 505         int                     stage;
 506         int                     retries;
 507         u8                      pdata[32];
 508         struct list_head        link;
 509 };
 510
 511 /*
 512  * Call this to queue an i2c command to the SMU. You must fill info,
 513  * including info.data for a write, done and misc.
 514  * For now, no polling interface is provided so you have to use completion
 515  * callback.
 516  */
 517 extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
 518
 519
 520 #endif /* __KERNEL__ */
 521
 522
 523 /*
 524  * - SMU "sdb" partitions informations -
 525  */
 526
 527
 528 /*
 529  * Partition header format
 530  */
 531 struct smu_sdbp_header {
 532         __u8    id;
 533         __u8    len;
 534         __u8    version;
 535         __u8    flags;
 536 };
 537
 538
 539  /*
 540  * demangle 16 and 32 bits integer in some SMU partitions
 541  * (currently, afaik, this concerns only the FVT partition
 542  * (0x12)
 543  */
 544 #define SMU_U16_MIX(x)  le16_to_cpu(x)
 545 #define SMU_U32_MIX(x)  ((((x) & 0xff00ff00u) >> 8)|(((x) & 0x00ff00ffu) << 8))
 546
 547
 548 /* This is the definition of the SMU sdb-partition-0x12 table (called
 549  * CPU F/V/T operating points in Darwin). The definition for all those
 550  * SMU tables should be moved to some separate file
 551  */
 552 #define SMU_SDB_FVT_ID                  0x12
 553
 554 struct smu_sdbp_fvt {
 555         __u32   sysclk;                 /* Base SysClk frequency in Hz for
 556                                          * this operating point. Value need to
 557                                          * be unmixed with SMU_U32_MIX()
 558                                          */
 559         __u8    pad;
 560         __u8    maxtemp;                /* Max temp. supported by this
 561                                          * operating point
 562                                          */
 563
 564         __u16   volts[3];               /* CPU core voltage for the 3
 565                                          * PowerTune modes, a mode with
 566                                          * 0V = not supported. Value need
 567                                          * to be unmixed with SMU_U16_MIX()
 568                                          */
 569 };
 570
 571 /* This partition contains voltage & current sensor calibration
 572  * informations
 573  */
 574 #define SMU_SDB_CPUVCP_ID               0x21
 575
 576 struct smu_sdbp_cpuvcp {
 577         __u16   volt_scale;             /* u4.12 fixed point */
 578         __s16   volt_offset;            /* s4.12 fixed point */
 579         __u16   curr_scale;             /* u4.12 fixed point */
 580         __s16   curr_offset;            /* s4.12 fixed point */
 581         __s32   power_quads[3];         /* s4.28 fixed point */
 582 };
 583
 584 /* This partition contains CPU thermal diode calibration
 585  */
 586 #define SMU_SDB_CPUDIODE_ID             0x18
 587
 588 struct smu_sdbp_cpudiode {
 589         __u16   m_value;                /* u1.15 fixed point */
 590         __s16   b_value;                /* s10.6 fixed point */
 591
 592 };
 593
 594 /* This partition contains Slots power calibration
 595  */
 596 #define SMU_SDB_SLOTSPOW_ID             0x78
 597
 598 struct smu_sdbp_slotspow {
 599         __u16   pow_scale;              /* u4.12 fixed point */
 600         __s16   pow_offset;             /* s4.12 fixed point */
 601 };
 602
 603 /* This partition contains machine specific version information about
 604  * the sensor/control layout
 605  */
 606 #define SMU_SDB_SENSORTREE_ID           0x25
 607
 608 struct smu_sdbp_sensortree {
 609         __u8    model_id;
 610         __u8    unknown[3];
 611 };
 612
 613 /* This partition contains CPU thermal control PID informations. So far
 614  * only single CPU machines have been seen with an SMU, so we assume this
 615  * carries only informations for those
 616  */
 617 #define SMU_SDB_CPUPIDDATA_ID           0x17
 618
 619 struct smu_sdbp_cpupiddata {
 620         __u8    unknown1;
 621         __u8    target_temp_delta;
 622         __u8    unknown2;
 623         __u8    history_len;
 624         __s16   power_adj;
 625         __u16   max_power;
 626         __s32   gp,gr,gd;
 627 };
 628
 629
 630 /* Other partitions without known structures */
 631 #define SMU_SDB_DEBUG_SWITCHES_ID       0x05
 632
 633 #ifdef __KERNEL__
 634 /*
 635  * This returns the pointer to an SMU "sdb" partition data or NULL
 636  * if not found. The data format is described below
 637  */
 638 extern const struct smu_sdbp_header *smu_get_sdb_partition(int id,
 639                                         unsigned int *size);
 640
 641 /* Get "sdb" partition data from an SMU satellite */
 642 extern struct smu_sdbp_header *smu_sat_get_sdb_partition(unsigned int sat_id,
 643                                         int id, unsigned int *size);
 644
 645
 646 #endif /* __KERNEL__ */
 647
 648
 649 /*
 650  * - Userland interface -
 651  */
 652
 653 /*
 654  * A given instance of the device can be configured for 2 different
 655  * things at the moment:
 656  *
 657  *  - sending SMU commands (default at open() time)
 658  *  - receiving SMU events (not yet implemented)
 659  *
 660  * Commands are written with write() of a command block. They can be
 661  * "driver" commands (for example to switch to event reception mode)
 662  * or real SMU commands. They are made of a header followed by command
 663  * data if any.
 664  *
 665  * For SMU commands (not for driver commands), you can then read() back
 666  * a reply. The reader will be blocked or not depending on how the device
 667  * file is opened. poll() isn't implemented yet. The reply will consist
 668  * of a header as well, followed by the reply data if any. You should
 669  * always provide a buffer large enough for the maximum reply data, I
 670  * recommand one page.
 671  *
 672  * It is illegal to send SMU commands through a file descriptor configured
 673  * for events reception
 674  *
 675  */
 676 struct smu_user_cmd_hdr
 677 {
 678         __u32           cmdtype;
 679 #define SMU_CMDTYPE_SMU                 0       /* SMU command */
 680 #define SMU_CMDTYPE_WANTS_EVENTS        1       /* switch fd to events mode */
 681 #define SMU_CMDTYPE_GET_PARTITION       2       /* retrieve an sdb partition */
 682
 683         __u8            cmd;                    /* SMU command byte */
 684         __u8            pad[3];                 /* padding */
 685         __u32           data_len;               /* Length of data following */
 686 };
 687
 688 struct smu_user_reply_hdr
 689 {
 690         __u32           status;                 /* Command status */
 691         __u32           reply_len;              /* Length of data follwing */
 692 };
 693
 694 #endif /*  _SMU_H */