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2 * Copyright 2016,2017 IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
9 #ifndef _ASM_POWERPC_XIVE_H
10 #define _ASM_POWERPC_XIVE_H
12 #define XIVE_INVALID_VP 0xffffffff
14 #ifdef CONFIG_PPC_XIVE
17 * Thread Interrupt Management Area (TIMA)
19 * This is a global MMIO region divided in 4 pages of varying access
20 * permissions, providing access to per-cpu interrupt management
21 * functions. It always identifies the CPU doing the access based
22 * on the PowerBus initiator ID, thus we always access via the
23 * same offset regardless of where the code is executing
25 extern void __iomem
*xive_tima
;
28 * Offset in the TM area of our current execution level (provided by
31 extern u32 xive_tima_offset
;
34 * Per-irq data (irq_get_handler_data for normal IRQs), IPIs
35 * have it stored in the xive_cpu structure. We also cache
36 * for normal interrupts the current target CPU.
38 * This structure is setup by the backend for each interrupt.
40 struct xive_irq_data
{
43 void __iomem
*eoi_mmio
;
45 void __iomem
*trig_mmio
;
50 /* Setup/used by frontend */
54 #define XIVE_IRQ_FLAG_STORE_EOI 0x01
55 #define XIVE_IRQ_FLAG_LSI 0x02
56 #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04
57 #define XIVE_IRQ_FLAG_MASK_FW 0x08
58 #define XIVE_IRQ_FLAG_EOI_FW 0x10
59 #define XIVE_IRQ_FLAG_H_INT_ESB 0x20
61 /* Special flag set by KVM for excalation interrupts */
62 #define XIVE_IRQ_NO_EOI 0x80
64 #define XIVE_INVALID_CHIP_ID -1
66 /* A queue tracking structure in a CPU */
75 atomic_t pending_count
;
78 /* Global enable flags for the XIVE support */
79 extern bool __xive_enabled
;
81 static inline bool xive_enabled(void) { return __xive_enabled
; }
83 extern bool xive_spapr_init(void);
84 extern bool xive_native_init(void);
85 extern void xive_smp_probe(void);
86 extern int xive_smp_prepare_cpu(unsigned int cpu
);
87 extern void xive_smp_setup_cpu(void);
88 extern void xive_smp_disable_cpu(void);
89 extern void xive_teardown_cpu(void);
90 extern void xive_shutdown(void);
91 extern void xive_flush_interrupt(void);
94 extern void xmon_xive_do_dump(int cpu
);
96 /* APIs used by KVM */
97 extern u32
xive_native_default_eq_shift(void);
98 extern u32
xive_native_alloc_vp_block(u32 max_vcpus
);
99 extern void xive_native_free_vp_block(u32 vp_base
);
100 extern int xive_native_populate_irq_data(u32 hw_irq
,
101 struct xive_irq_data
*data
);
102 extern void xive_cleanup_irq_data(struct xive_irq_data
*xd
);
103 extern u32
xive_native_alloc_irq(void);
104 extern void xive_native_free_irq(u32 irq
);
105 extern int xive_native_configure_irq(u32 hw_irq
, u32 target
, u8 prio
, u32 sw_irq
);
107 extern int xive_native_configure_queue(u32 vp_id
, struct xive_q
*q
, u8 prio
,
108 __be32
*qpage
, u32 order
, bool can_escalate
);
109 extern void xive_native_disable_queue(u32 vp_id
, struct xive_q
*q
, u8 prio
);
111 extern void xive_native_sync_source(u32 hw_irq
);
112 extern void xive_native_sync_queue(u32 hw_irq
);
113 extern bool is_xive_irq(struct irq_chip
*chip
);
114 extern int xive_native_enable_vp(u32 vp_id
, bool single_escalation
);
115 extern int xive_native_disable_vp(u32 vp_id
);
116 extern int xive_native_get_vp_info(u32 vp_id
, u32
*out_cam_id
, u32
*out_chip_id
);
117 extern bool xive_native_has_single_escalation(void);
119 extern int xive_native_get_queue_info(u32 vp_id
, uint32_t prio
,
123 u32
*out_escalate_irq
,
126 extern int xive_native_get_queue_state(u32 vp_id
, uint32_t prio
, u32
*qtoggle
,
128 extern int xive_native_set_queue_state(u32 vp_id
, uint32_t prio
, u32 qtoggle
,
130 extern int xive_native_get_vp_state(u32 vp_id
, u64
*out_state
);
134 static inline bool xive_enabled(void) { return false; }
136 static inline bool xive_spapr_init(void) { return false; }
137 static inline bool xive_native_init(void) { return false; }
138 static inline void xive_smp_probe(void) { }
139 static inline int xive_smp_prepare_cpu(unsigned int cpu
) { return -EINVAL
; }
140 static inline void xive_smp_setup_cpu(void) { }
141 static inline void xive_smp_disable_cpu(void) { }
142 static inline void xive_kexec_teardown_cpu(int secondary
) { }
143 static inline void xive_shutdown(void) { }
144 static inline void xive_flush_interrupt(void) { }
146 static inline u32
xive_native_alloc_vp_block(u32 max_vcpus
) { return XIVE_INVALID_VP
; }
147 static inline void xive_native_free_vp_block(u32 vp_base
) { }
151 #endif /* _ASM_POWERPC_XIVE_H */