arch/powerpc/include/asm/xive.h

   1 /*
   2  * Copyright 2016,2017 IBM Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9 #ifndef _ASM_POWERPC_XIVE_H
  10 #define _ASM_POWERPC_XIVE_H
  11
  12 #define XIVE_INVALID_VP 0xffffffff
  13
  14 #ifdef CONFIG_PPC_XIVE
  15
  16 /*
  17  * Thread Interrupt Management Area (TIMA)
  18  *
  19  * This is a global MMIO region divided in 4 pages of varying access
  20  * permissions, providing access to per-cpu interrupt management
  21  * functions. It always identifies the CPU doing the access based
  22  * on the PowerBus initiator ID, thus we always access via the
  23  * same offset regardless of where the code is executing
  24  */
  25 extern void __iomem *xive_tima;
  26
  27 /*
  28  * Offset in the TM area of our current execution level (provided by
  29  * the backend)
  30  */
  31 extern u32 xive_tima_offset;
  32
  33 /*
  34  * Per-irq data (irq_get_handler_data for normal IRQs), IPIs
  35  * have it stored in the xive_cpu structure. We also cache
  36  * for normal interrupts the current target CPU.
  37  *
  38  * This structure is setup by the backend for each interrupt.
  39  */
  40 struct xive_irq_data {
  41         u64 flags;
  42         u64 eoi_page;
  43         void __iomem *eoi_mmio;
  44         u64 trig_page;
  45         void __iomem *trig_mmio;
  46         u32 esb_shift;
  47         int src_chip;
  48
  49         /* Setup/used by frontend */
  50         int target;
  51         bool saved_p;
  52 };
  53 #define XIVE_IRQ_FLAG_STORE_EOI 0x01
  54 #define XIVE_IRQ_FLAG_LSI       0x02
  55 #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04
  56 #define XIVE_IRQ_FLAG_MASK_FW   0x08
  57 #define XIVE_IRQ_FLAG_EOI_FW    0x10
  58
  59 #define XIVE_INVALID_CHIP_ID    -1
  60
  61 /* A queue tracking structure in a CPU */
  62 struct xive_q {
  63         __be32                  *qpage;
  64         u32                     msk;
  65         u32                     idx;
  66         u32                     toggle;
  67         u64                     eoi_phys;
  68         u32                     esc_irq;
  69         atomic_t                count;
  70         atomic_t                pending_count;
  71 };
  72
  73 /*
  74  * "magic" Event State Buffer (ESB) MMIO offsets.
  75  *
  76  * Each interrupt source has a 2-bit state machine called ESB
  77  * which can be controlled by MMIO. It's made of 2 bits, P and
  78  * Q. P indicates that an interrupt is pending (has been sent
  79  * to a queue and is waiting for an EOI). Q indicates that the
  80  * interrupt has been triggered while pending.
  81  *
  82  * This acts as a coalescing mechanism in order to guarantee
  83  * that a given interrupt only occurs at most once in a queue.
  84  *
  85  * When doing an EOI, the Q bit will indicate if the interrupt
  86  * needs to be re-triggered.
  87  *
  88  * The following offsets into the ESB MMIO allow to read or
  89  * manipulate the PQ bits. They must be used with an 8-bytes
  90  * load instruction. They all return the previous state of the
  91  * interrupt (atomically).
  92  *
  93  * Additionally, some ESB pages support doing an EOI via a
  94  * store at 0 and some ESBs support doing a trigger via a
  95  * separate trigger page.
  96  */
  97 #define XIVE_ESB_STORE_EOI      0x400 /* Store */
  98 #define XIVE_ESB_LOAD_EOI       0x000 /* Load */
  99 #define XIVE_ESB_GET            0x800 /* Load */
 100 #define XIVE_ESB_SET_PQ_00      0xc00 /* Load */
 101 #define XIVE_ESB_SET_PQ_01      0xd00 /* Load */
 102 #define XIVE_ESB_SET_PQ_10      0xe00 /* Load */
 103 #define XIVE_ESB_SET_PQ_11      0xf00 /* Load */
 104
 105 #define XIVE_ESB_VAL_P          0x2
 106 #define XIVE_ESB_VAL_Q          0x1
 107
 108 /* Global enable flags for the XIVE support */
 109 extern bool __xive_enabled;
 110
 111 static inline bool xive_enabled(void) { return __xive_enabled; }
 112
 113 extern bool xive_native_init(void);
 114 extern void xive_smp_probe(void);
 115 extern int  xive_smp_prepare_cpu(unsigned int cpu);
 116 extern void xive_smp_setup_cpu(void);
 117 extern void xive_smp_disable_cpu(void);
 118 extern void xive_kexec_teardown_cpu(int secondary);
 119 extern void xive_shutdown(void);
 120 extern void xive_flush_interrupt(void);
 121
 122 /* xmon hook */
 123 extern void xmon_xive_do_dump(int cpu);
 124
 125 /* APIs used by KVM */
 126 extern u32 xive_native_default_eq_shift(void);
 127 extern u32 xive_native_alloc_vp_block(u32 max_vcpus);
 128 extern void xive_native_free_vp_block(u32 vp_base);
 129 extern int xive_native_populate_irq_data(u32 hw_irq,
 130                                          struct xive_irq_data *data);
 131 extern void xive_cleanup_irq_data(struct xive_irq_data *xd);
 132 extern u32 xive_native_alloc_irq(void);
 133 extern void xive_native_free_irq(u32 irq);
 134 extern int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
 135
 136 extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
 137                                        __be32 *qpage, u32 order, bool can_escalate);
 138 extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
 139
 140 extern void xive_native_sync_source(u32 hw_irq);
 141 extern bool is_xive_irq(struct irq_chip *chip);
 142 extern int xive_native_enable_vp(u32 vp_id);
 143 extern int xive_native_disable_vp(u32 vp_id);
 144 extern int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id);
 145
 146 #else
 147
 148 static inline bool xive_enabled(void) { return false; }
 149
 150 static inline bool xive_native_init(void) { return false; }
 151 static inline void xive_smp_probe(void) { }
 152 extern inline int  xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; }
 153 static inline void xive_smp_setup_cpu(void) { }
 154 static inline void xive_smp_disable_cpu(void) { }
 155 static inline void xive_kexec_teardown_cpu(int secondary) { }
 156 static inline void xive_shutdown(void) { }
 157 static inline void xive_flush_interrupt(void) { }
 158
 159 static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; }
 160 static inline void xive_native_free_vp_block(u32 vp_base) { }
 161
 162 #endif
 163
 164 #endif /* _ASM_POWERPC_XIVE_H */