arch/powerpc/include/uapi/asm/kvm.h

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, write to the Free Software
  13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  14  *
  15  * Copyright IBM Corp. 2007
  16  *
  17  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
  18  */
  19
  20 #ifndef __LINUX_KVM_POWERPC_H
  21 #define __LINUX_KVM_POWERPC_H
  22
  23 #include <linux/types.h>
  24
  25 /* Select powerpc specific features in <linux/kvm.h> */
  26 #define __KVM_HAVE_SPAPR_TCE
  27 #define __KVM_HAVE_PPC_SMT
  28
  29 struct kvm_regs {
  30         __u64 pc;
  31         __u64 cr;
  32         __u64 ctr;
  33         __u64 lr;
  34         __u64 xer;
  35         __u64 msr;
  36         __u64 srr0;
  37         __u64 srr1;
  38         __u64 pid;
  39
  40         __u64 sprg0;
  41         __u64 sprg1;
  42         __u64 sprg2;
  43         __u64 sprg3;
  44         __u64 sprg4;
  45         __u64 sprg5;
  46         __u64 sprg6;
  47         __u64 sprg7;
  48
  49         __u64 gpr[32];
  50 };
  51
  52 #define KVM_SREGS_E_IMPL_NONE   0
  53 #define KVM_SREGS_E_IMPL_FSL    1
  54
  55 #define KVM_SREGS_E_FSL_PIDn    (1 << 0) /* PID1/PID2 */
  56
  57 /*
  58  * Feature bits indicate which sections of the sregs struct are valid,
  59  * both in KVM_GET_SREGS and KVM_SET_SREGS.  On KVM_SET_SREGS, registers
  60  * corresponding to unset feature bits will not be modified.  This allows
  61  * restoring a checkpoint made without that feature, while keeping the
  62  * default values of the new registers.
  63  *
  64  * KVM_SREGS_E_BASE contains:
  65  * CSRR0/1 (refers to SRR2/3 on 40x)
  66  * ESR
  67  * DEAR
  68  * MCSR
  69  * TSR
  70  * TCR
  71  * DEC
  72  * TB
  73  * VRSAVE (USPRG0)
  74  */
  75 #define KVM_SREGS_E_BASE                (1 << 0)
  76
  77 /*
  78  * KVM_SREGS_E_ARCH206 contains:
  79  *
  80  * PIR
  81  * MCSRR0/1
  82  * DECAR
  83  * IVPR
  84  */
  85 #define KVM_SREGS_E_ARCH206             (1 << 1)
  86
  87 /*
  88  * Contains EPCR, plus the upper half of 64-bit registers
  89  * that are 32-bit on 32-bit implementations.
  90  */
  91 #define KVM_SREGS_E_64                  (1 << 2)
  92
  93 #define KVM_SREGS_E_SPRG8               (1 << 3)
  94 #define KVM_SREGS_E_MCIVPR              (1 << 4)
  95
  96 /*
  97  * IVORs are used -- contains IVOR0-15, plus additional IVORs
  98  * in combination with an appropriate feature bit.
  99  */
 100 #define KVM_SREGS_E_IVOR                (1 << 5)
 101
 102 /*
 103  * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
 104  * Also TLBnPS if MMUCFG[MAVN] = 1.
 105  */
 106 #define KVM_SREGS_E_ARCH206_MMU         (1 << 6)
 107
 108 /* DBSR, DBCR, IAC, DAC, DVC */
 109 #define KVM_SREGS_E_DEBUG               (1 << 7)
 110
 111 /* Enhanced debug -- DSRR0/1, SPRG9 */
 112 #define KVM_SREGS_E_ED                  (1 << 8)
 113
 114 /* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
 115 #define KVM_SREGS_E_SPE                 (1 << 9)
 116
 117 /*
 118  * DEPRECATED! USE ONE_REG FOR THIS ONE!
 119  * External Proxy (EXP) -- EPR
 120  */
 121 #define KVM_SREGS_EXP                   (1 << 10)
 122
 123 /* External PID (E.PD) -- EPSC/EPLC */
 124 #define KVM_SREGS_E_PD                  (1 << 11)
 125
 126 /* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */
 127 #define KVM_SREGS_E_PC                  (1 << 12)
 128
 129 /* Page table (E.PT) -- EPTCFG */
 130 #define KVM_SREGS_E_PT                  (1 << 13)
 131
 132 /* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */
 133 #define KVM_SREGS_E_PM                  (1 << 14)
 134
 135 /*
 136  * Special updates:
 137  *
 138  * Some registers may change even while a vcpu is not running.
 139  * To avoid losing these changes, by default these registers are
 140  * not updated by KVM_SET_SREGS.  To force an update, set the bit
 141  * in u.e.update_special corresponding to the register to be updated.
 142  *
 143  * The update_special field is zero on return from KVM_GET_SREGS.
 144  *
 145  * When restoring a checkpoint, the caller can set update_special
 146  * to 0xffffffff to ensure that everything is restored, even new features
 147  * that the caller doesn't know about.
 148  */
 149 #define KVM_SREGS_E_UPDATE_MCSR         (1 << 0)
 150 #define KVM_SREGS_E_UPDATE_TSR          (1 << 1)
 151 #define KVM_SREGS_E_UPDATE_DEC          (1 << 2)
 152 #define KVM_SREGS_E_UPDATE_DBSR         (1 << 3)
 153
 154 /*
 155  * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a
 156  * previous KVM_GET_REGS.
 157  *
 158  * Unless otherwise indicated, setting any register with KVM_SET_SREGS
 159  * directly sets its value.  It does not trigger any special semantics such
 160  * as write-one-to-clear.  Calling KVM_SET_SREGS on an unmodified struct
 161  * just received from KVM_GET_SREGS is always a no-op.
 162  */
 163 struct kvm_sregs {
 164         __u32 pvr;
 165         union {
 166                 struct {
 167                         __u64 sdr1;
 168                         struct {
 169                                 struct {
 170                                         __u64 slbe;
 171                                         __u64 slbv;
 172                                 } slb[64];
 173                         } ppc64;
 174                         struct {
 175                                 __u32 sr[16];
 176                                 __u64 ibat[8];
 177                                 __u64 dbat[8];
 178                         } ppc32;
 179                 } s;
 180                 struct {
 181                         union {
 182                                 struct { /* KVM_SREGS_E_IMPL_FSL */
 183                                         __u32 features; /* KVM_SREGS_E_FSL_ */
 184                                         __u32 svr;
 185                                         __u64 mcar;
 186                                         __u32 hid0;
 187
 188                                         /* KVM_SREGS_E_FSL_PIDn */
 189                                         __u32 pid1, pid2;
 190                                 } fsl;
 191                                 __u8 pad[256];
 192                         } impl;
 193
 194                         __u32 features; /* KVM_SREGS_E_ */
 195                         __u32 impl_id;  /* KVM_SREGS_E_IMPL_ */
 196                         __u32 update_special; /* KVM_SREGS_E_UPDATE_ */
 197                         __u32 pir;      /* read-only */
 198                         __u64 sprg8;
 199                         __u64 sprg9;    /* E.ED */
 200                         __u64 csrr0;
 201                         __u64 dsrr0;    /* E.ED */
 202                         __u64 mcsrr0;
 203                         __u32 csrr1;
 204                         __u32 dsrr1;    /* E.ED */
 205                         __u32 mcsrr1;
 206                         __u32 esr;
 207                         __u64 dear;
 208                         __u64 ivpr;
 209                         __u64 mcivpr;
 210                         __u64 mcsr;     /* KVM_SREGS_E_UPDATE_MCSR */
 211
 212                         __u32 tsr;      /* KVM_SREGS_E_UPDATE_TSR */
 213                         __u32 tcr;
 214                         __u32 decar;
 215                         __u32 dec;      /* KVM_SREGS_E_UPDATE_DEC */
 216
 217                         /*
 218                          * Userspace can read TB directly, but the
 219                          * value reported here is consistent with "dec".
 220                          *
 221                          * Read-only.
 222                          */
 223                         __u64 tb;
 224
 225                         __u32 dbsr;     /* KVM_SREGS_E_UPDATE_DBSR */
 226                         __u32 dbcr[3];
 227                         /*
 228                          * iac/dac registers are 64bit wide, while this API
 229                          * interface provides only lower 32 bits on 64 bit
 230                          * processors. ONE_REG interface is added for 64bit
 231                          * iac/dac registers.
 232                          */
 233                         __u32 iac[4];
 234                         __u32 dac[2];
 235                         __u32 dvc[2];
 236                         __u8 num_iac;   /* read-only */
 237                         __u8 num_dac;   /* read-only */
 238                         __u8 num_dvc;   /* read-only */
 239                         __u8 pad;
 240
 241                         __u32 epr;      /* EXP */
 242                         __u32 vrsave;   /* a.k.a. USPRG0 */
 243                         __u32 epcr;     /* KVM_SREGS_E_64 */
 244
 245                         __u32 mas0;
 246                         __u32 mas1;
 247                         __u64 mas2;
 248                         __u64 mas7_3;
 249                         __u32 mas4;
 250                         __u32 mas6;
 251
 252                         __u32 ivor_low[16]; /* IVOR0-15 */
 253                         __u32 ivor_high[18]; /* IVOR32+, plus room to expand */
 254
 255                         __u32 mmucfg;   /* read-only */
 256                         __u32 eptcfg;   /* E.PT, read-only */
 257                         __u32 tlbcfg[4];/* read-only */
 258                         __u32 tlbps[4]; /* read-only */
 259
 260                         __u32 eplc, epsc; /* E.PD */
 261                 } e;
 262                 __u8 pad[1020];
 263         } u;
 264 };
 265
 266 struct kvm_fpu {
 267         __u64 fpr[32];
 268 };
 269
 270 struct kvm_debug_exit_arch {
 271 };
 272
 273 /* for KVM_SET_GUEST_DEBUG */
 274 struct kvm_guest_debug_arch {
 275         struct {
 276                 /* H/W breakpoint/watchpoint address */
 277                 __u64 addr;
 278                 /*
 279                  * Type denotes h/w breakpoint, read watchpoint, write
 280                  * watchpoint or watchpoint (both read and write).
 281                  */
 282 #define KVMPPC_DEBUG_NONE               0x0
 283 #define KVMPPC_DEBUG_BREAKPOINT         (1UL << 1)
 284 #define KVMPPC_DEBUG_WATCH_WRITE        (1UL << 2)
 285 #define KVMPPC_DEBUG_WATCH_READ         (1UL << 3)
 286                 __u32 type;
 287                 __u32 reserved;
 288         } bp[16];
 289 };
 290
 291 /* Debug related defines */
 292 /*
 293  * kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic
 294  * and upper 16 bits are architecture specific. Architecture specific defines
 295  * that ioctl is for setting hardware breakpoint or software breakpoint.
 296  */
 297 #define KVM_GUESTDBG_USE_SW_BP          0x00010000
 298 #define KVM_GUESTDBG_USE_HW_BP          0x00020000
 299
 300 /* definition of registers in kvm_run */
 301 struct kvm_sync_regs {
 302 };
 303
 304 #define KVM_INTERRUPT_SET       -1U
 305 #define KVM_INTERRUPT_UNSET     -2U
 306 #define KVM_INTERRUPT_SET_LEVEL -3U
 307
 308 #define KVM_CPU_440             1
 309 #define KVM_CPU_E500V2          2
 310 #define KVM_CPU_3S_32           3
 311 #define KVM_CPU_3S_64           4
 312 #define KVM_CPU_E500MC          5
 313
 314 /* for KVM_CAP_SPAPR_TCE */
 315 struct kvm_create_spapr_tce {
 316         __u64 liobn;
 317         __u32 window_size;
 318 };
 319
 320 /* for KVM_ALLOCATE_RMA */
 321 struct kvm_allocate_rma {
 322         __u64 rma_size;
 323 };
 324
 325 struct kvm_book3e_206_tlb_entry {
 326         __u32 mas8;
 327         __u32 mas1;
 328         __u64 mas2;
 329         __u64 mas7_3;
 330 };
 331
 332 struct kvm_book3e_206_tlb_params {
 333         /*
 334          * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:
 335          *
 336          * - The number of ways of TLB0 must be a power of two between 2 and
 337          *   16.
 338          * - TLB1 must be fully associative.
 339          * - The size of TLB0 must be a multiple of the number of ways, and
 340          *   the number of sets must be a power of two.
 341          * - The size of TLB1 may not exceed 64 entries.
 342          * - TLB0 supports 4 KiB pages.
 343          * - The page sizes supported by TLB1 are as indicated by
 344          *   TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1)
 345          *   as returned by KVM_GET_SREGS.
 346          * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[]
 347          *   and tlb_ways[] must be zero.
 348          *
 349          * tlb_ways[n] = tlb_sizes[n] means the array is fully associative.
 350          *
 351          * KVM will adjust TLBnCFG based on the sizes configured here,
 352          * though arrays greater than 2048 entries will have TLBnCFG[NENTRY]
 353          * set to zero.
 354          */
 355         __u32 tlb_sizes[4];
 356         __u32 tlb_ways[4];
 357         __u32 reserved[8];
 358 };
 359
 360 /* For KVM_PPC_GET_HTAB_FD */
 361 struct kvm_get_htab_fd {
 362         __u64   flags;
 363         __u64   start_index;
 364         __u64   reserved[2];
 365 };
 366
 367 /* Values for kvm_get_htab_fd.flags */
 368 #define KVM_GET_HTAB_BOLTED_ONLY        ((__u64)0x1)
 369 #define KVM_GET_HTAB_WRITE              ((__u64)0x2)
 370
 371 /*
 372  * Data read on the file descriptor is formatted as a series of
 373  * records, each consisting of a header followed by a series of
 374  * `n_valid' HPTEs (16 bytes each), which are all valid.  Following
 375  * those valid HPTEs there are `n_invalid' invalid HPTEs, which
 376  * are not represented explicitly in the stream.  The same format
 377  * is used for writing.
 378  */
 379 struct kvm_get_htab_header {
 380         __u32   index;
 381         __u16   n_valid;
 382         __u16   n_invalid;
 383 };
 384
 385 #define KVM_REG_PPC_HIOR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
 386 #define KVM_REG_PPC_IAC1        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2)
 387 #define KVM_REG_PPC_IAC2        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3)
 388 #define KVM_REG_PPC_IAC3        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4)
 389 #define KVM_REG_PPC_IAC4        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5)
 390 #define KVM_REG_PPC_DAC1        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6)
 391 #define KVM_REG_PPC_DAC2        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7)
 392 #define KVM_REG_PPC_DABR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8)
 393 #define KVM_REG_PPC_DSCR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9)
 394 #define KVM_REG_PPC_PURR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa)
 395 #define KVM_REG_PPC_SPURR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb)
 396 #define KVM_REG_PPC_DAR         (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc)
 397 #define KVM_REG_PPC_DSISR       (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd)
 398 #define KVM_REG_PPC_AMR         (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe)
 399 #define KVM_REG_PPC_UAMOR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf)
 400
 401 #define KVM_REG_PPC_MMCR0       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10)
 402 #define KVM_REG_PPC_MMCR1       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11)
 403 #define KVM_REG_PPC_MMCRA       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12)
 404
 405 #define KVM_REG_PPC_PMC1        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18)
 406 #define KVM_REG_PPC_PMC2        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19)
 407 #define KVM_REG_PPC_PMC3        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a)
 408 #define KVM_REG_PPC_PMC4        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b)
 409 #define KVM_REG_PPC_PMC5        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c)
 410 #define KVM_REG_PPC_PMC6        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d)
 411 #define KVM_REG_PPC_PMC7        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e)
 412 #define KVM_REG_PPC_PMC8        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f)
 413
 414 /* 32 floating-point registers */
 415 #define KVM_REG_PPC_FPR0        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20)
 416 #define KVM_REG_PPC_FPR(n)      (KVM_REG_PPC_FPR0 + (n))
 417 #define KVM_REG_PPC_FPR31       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f)
 418
 419 /* 32 VMX/Altivec vector registers */
 420 #define KVM_REG_PPC_VR0         (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40)
 421 #define KVM_REG_PPC_VR(n)       (KVM_REG_PPC_VR0 + (n))
 422 #define KVM_REG_PPC_VR31        (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f)
 423
 424 /* 32 double-width FP registers for VSX */
 425 /* High-order halves overlap with FP regs */
 426 #define KVM_REG_PPC_VSR0        (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60)
 427 #define KVM_REG_PPC_VSR(n)      (KVM_REG_PPC_VSR0 + (n))
 428 #define KVM_REG_PPC_VSR31       (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f)
 429
 430 /* FP and vector status/control registers */
 431 #define KVM_REG_PPC_FPSCR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80)
 432 #define KVM_REG_PPC_VSCR        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81)
 433
 434 /* Virtual processor areas */
 435 /* For SLB & DTL, address in high (first) half, length in low half */
 436 #define KVM_REG_PPC_VPA_ADDR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82)
 437 #define KVM_REG_PPC_VPA_SLB     (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83)
 438 #define KVM_REG_PPC_VPA_DTL     (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84)
 439
 440 #define KVM_REG_PPC_EPCR        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85)
 441 #define KVM_REG_PPC_EPR         (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86)
 442
 443 /* Timer Status Register OR/CLEAR interface */
 444 #define KVM_REG_PPC_OR_TSR      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87)
 445 #define KVM_REG_PPC_CLEAR_TSR   (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88)
 446 #define KVM_REG_PPC_TCR         (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89)
 447 #define KVM_REG_PPC_TSR         (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a)
 448
 449 /* Debugging: Special instruction for software breakpoint */
 450 #define KVM_REG_PPC_DEBUG_INST  (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b)
 451
 452 /* MMU registers */
 453 #define KVM_REG_PPC_MAS0        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c)
 454 #define KVM_REG_PPC_MAS1        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d)
 455 #define KVM_REG_PPC_MAS2        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e)
 456 #define KVM_REG_PPC_MAS7_3      (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f)
 457 #define KVM_REG_PPC_MAS4        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90)
 458 #define KVM_REG_PPC_MAS6        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91)
 459 #define KVM_REG_PPC_MMUCFG      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92)
 460 /*
 461  * TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using
 462  * KVM_CAP_SW_TLB ioctl
 463  */
 464 #define KVM_REG_PPC_TLB0CFG     (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93)
 465 #define KVM_REG_PPC_TLB1CFG     (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94)
 466 #define KVM_REG_PPC_TLB2CFG     (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95)
 467 #define KVM_REG_PPC_TLB3CFG     (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96)
 468 #define KVM_REG_PPC_TLB0PS      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97)
 469 #define KVM_REG_PPC_TLB1PS      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98)
 470 #define KVM_REG_PPC_TLB2PS      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99)
 471 #define KVM_REG_PPC_TLB3PS      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)
 472 #define KVM_REG_PPC_EPTCFG      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b)
 473
 474 #endif /* __LINUX_KVM_POWERPC_H */