2 * This file contains low level CPU setup functions.
3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cache.h>
19 #include <asm/feature-fixups.h>
21 _GLOBAL(__setup_cpu_603)
25 mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
26 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
27 lis r10, (swapper_pg_dir - PAGE_OFFSET)@h
28 ori r10, r10, (swapper_pg_dir - PAGE_OFFSET)@l
29 mtspr SPRN_SPRG_PGDIR, r10
32 bl __init_fpu_registers
33 END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
34 bl setup_common_caches
37 _GLOBAL(__setup_cpu_604)
39 bl setup_common_caches
43 _GLOBAL(__setup_cpu_750)
45 bl __init_fpu_registers
46 bl setup_common_caches
47 bl setup_750_7400_hid0
50 _GLOBAL(__setup_cpu_750cx)
52 bl __init_fpu_registers
53 bl setup_common_caches
54 bl setup_750_7400_hid0
58 _GLOBAL(__setup_cpu_750fx)
60 bl __init_fpu_registers
61 bl setup_common_caches
62 bl setup_750_7400_hid0
66 _GLOBAL(__setup_cpu_7400)
68 bl __init_fpu_registers
69 bl setup_7400_workarounds
70 bl setup_common_caches
71 bl setup_750_7400_hid0
74 _GLOBAL(__setup_cpu_7410)
76 bl __init_fpu_registers
77 bl setup_7410_workarounds
78 bl setup_common_caches
79 bl setup_750_7400_hid0
84 _GLOBAL(__setup_cpu_745x)
86 bl setup_common_caches
87 bl setup_745x_specifics
91 /* Enable caches for 603's, 604, 750 & 7400 */
95 ori r11,r11,HID0_ICE|HID0_DCE
97 bne 1f /* don't invalidate the D-cache */
98 ori r8,r8,HID0_DCI /* unless it wasn't enabled */
100 mtspr SPRN_HID0,r8 /* enable and invalidate caches */
102 mtspr SPRN_HID0,r11 /* enable caches */
107 /* 604, 604e, 604ev, ...
108 * Enable superscalar execution & branch history table
112 ori r11,r11,HID0_SIED|HID0_BHTE
115 mtspr SPRN_HID0,r8 /* flush branch target address cache */
116 sync /* on 604e/604r */
122 /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
123 * erratas we work around here.
124 * Moto MPC710CE.pdf describes them, those are errata
126 * Note that we assume the firmware didn't choose to
127 * apply other workarounds (there are other ones documented
128 * in the .pdf). It appear that Apple firmware only works
129 * around #3 and with the same fix we use. We may want to
130 * check if the CPU is using 60x bus mode in which case
131 * the workaround for errata #4 is useless. Also, we may
132 * want to explicitly clear HID0_NOPDST as this is not
133 * needed once we have applied workaround #5 (though it's
134 * not set by Apple's firmware at least).
136 setup_7400_workarounds:
142 setup_7410_workarounds:
148 mfspr r11,SPRN_MSSSR0
149 /* Errata #3: Set L1OPQ_SIZE to 0x10 */
152 /* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */
154 /* Errata #5: Set DRLT_SIZE to 0x01 */
158 mtspr SPRN_MSSSR0,r11
164 * Enable Store Gathering (SGE), Address Broadcast (ABE),
165 * Branch History Table (BHTE), Branch Target ICache (BTIC)
166 * Dynamic Power Management (DPM), Speculative (SPD)
167 * Clear Instruction cache throttling (ICTC)
171 ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
172 oris r11,r11,HID0_DPM@h
174 xori r11,r11,HID0_BTIC
175 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
177 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
178 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
180 andc r11,r11,r3 /* clear SPD: enable speculative */
182 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
190 * Looks like we have to disable NAP feature for some PLL settings...
191 * (waiting for confirmation)
195 rlwinm r10,r10,4,28,31
199 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
200 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
202 lwz r6,CPU_SPEC_FEATURES(r4)
203 li r7,CPU_FTR_CAN_NAP
205 stw r6,CPU_SPEC_FEATURES(r4)
214 * Enable Store Gathering (SGE), Branch Folding (FOLD)
215 * Branch History Table (BHTE), Branch Target ICache (BTIC)
216 * Dynamic Power Management (DPM), Speculative (SPD)
217 * Ensure our data cache instructions really operate.
218 * Timebase has to be running or we wouldn't have made it here,
219 * just ensure we don't disable it.
220 * Clear Instruction cache throttling (ICTC)
221 * Enable L2 HW prefetch
223 setup_745x_specifics:
224 /* We check for the presence of an L3 cache setup by
225 * the firmware. If any, we disable NAP capability as
226 * it's known to be bogus on rev 2.1 and earlier
230 andis. r11,r11,L3CR_L3E@h
232 END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
233 lwz r6,CPU_SPEC_FEATURES(r4)
234 andis. r0,r6,CPU_FTR_L3_DISABLE_NAP@h
236 li r7,CPU_FTR_CAN_NAP
238 stw r6,CPU_SPEC_FEATURES(r4)
242 /* All of the bits we have to set.....
244 ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
245 ori r11,r11,HID0_LRSTK | HID0_BTIC
246 oris r11,r11,HID0_DPM@h
247 BEGIN_MMU_FTR_SECTION
248 oris r11,r11,HID0_HIGH_BAT@h
249 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
251 xori r11,r11,HID0_BTIC
252 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
254 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
255 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
257 /* All of the bits we have to clear....
259 li r3,HID0_SPD | HID0_NOPDST | HID0_NOPTI
260 andc r11,r11,r3 /* clear SPD: enable speculative */
263 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
269 /* Enable L2 HW prefetch, if L2 is enabled
272 andis. r3,r3,L2CR_L2E@h
283 * Initialize the FPU registers. This is needed to work around an errata
284 * in some 750 cpus where using a not yet initialized FPU register after
285 * power on reset may hang the CPU
287 _GLOBAL(__init_fpu_registers)
292 addis r9,r3,empty_zero_page@ha
293 addi r9,r9,empty_zero_page@l
301 /* Definitions for the table use to save CPU states */
313 .balign L1_CACHE_BYTES
316 .balign L1_CACHE_BYTES,0
319 /* Called in normal context to backup CPU 0 state. This
320 * does not include cache settings. This function is also
321 * called for machine sleep. This does not include the MMU
322 * setup, BATs, etc... but rather the "special" registers
323 * like HID0, HID1, MSSCR0, etc...
325 _GLOBAL(__save_cpu_setup)
326 /* Some CR fields are volatile, we back it up all */
329 /* Get storage ptr */
330 lis r5,cpu_state_storage@h
331 ori r5,r5,cpu_state_storage@l
333 /* Save HID0 (common to all CONFIG_PPC_BOOK3S_32 cpus) */
337 /* Now deal with CPU type dependent registers */
340 cmplwi cr0,r3,0x8000 /* 7450 */
341 cmplwi cr1,r3,0x000c /* 7400 */
342 cmplwi cr2,r3,0x800c /* 7410 */
343 cmplwi cr3,r3,0x8001 /* 7455 */
344 cmplwi cr4,r3,0x8002 /* 7457 */
345 cmplwi cr5,r3,0x8003 /* 7447A */
346 cmplwi cr6,r3,0x7000 /* 750FX */
347 cmplwi cr7,r3,0x8004 /* 7448 */
348 /* cr1 is 7400 || 7410 */
349 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
351 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
352 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
353 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
354 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
355 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
357 /* Backup 74xx specific regs */
363 /* Backup 745x specific registers */
374 /* Backup 750FX specific registers */
377 /* If rev 2.x, backup HID2 */
388 /* Called with no MMU context (typically MSR:IR/DR off) to
389 * restore CPU state as backed up by the previous
390 * function. This does not include cache setting
392 _GLOBAL(__restore_cpu_setup)
393 /* Some CR fields are volatile, we back it up all */
396 /* Get storage ptr */
397 lis r5,(cpu_state_storage-KERNELBASE)@h
398 ori r5,r5,cpu_state_storage@l
408 /* Now deal with CPU type dependent registers */
411 cmplwi cr0,r3,0x8000 /* 7450 */
412 cmplwi cr1,r3,0x000c /* 7400 */
413 cmplwi cr2,r3,0x800c /* 7410 */
414 cmplwi cr3,r3,0x8001 /* 7455 */
415 cmplwi cr4,r3,0x8002 /* 7457 */
416 cmplwi cr5,r3,0x8003 /* 7447A */
417 cmplwi cr6,r3,0x7000 /* 750FX */
418 cmplwi cr7,r3,0x8004 /* 7448 */
419 /* cr1 is 7400 || 7410 */
420 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
422 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
423 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
424 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
425 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
426 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
428 /* Restore 74xx specific regs */
440 /* Clear 7410 L2CR2 */
444 /* Restore 745x specific registers */
466 /* Restore 750FX specific registers
467 * that is restore HID2 on rev 2.x and PLL config & switch
470 /* If rev 2.x, restore HID2 with low voltage bit cleared */
483 /* Wait for PLL to stabilize */
489 /* Setup final PLL */