2 * This file contains low level CPU setup functions.
3 * Kumar Gala <galak@kernel.crashing.org>
4 * Copyright 2009 Freescale Semiconductor, Inc.
6 * Based on cpu_setup_6xx code by
7 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
17 #include <asm/processor.h>
18 #include <asm/cputable.h>
19 #include <asm/ppc_asm.h>
20 #include <asm/nohash/mmu-book3e.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/mpc85xx.h>
24 _GLOBAL(__e500_icache_setup)
26 andi. r3, r0, L1CSR1_ICE
27 bnelr /* Already enabled */
28 oris r0, r0, L1CSR1_CPE@h
29 ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
30 mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
34 _GLOBAL(__e500_dcache_setup)
36 andi. r3, r0, L1CSR0_DCE
37 bnelr /* Already enabled */
41 mtspr SPRN_L1CSR0, r0 /* Disable */
44 li r0, (L1CSR0_DCFI | L1CSR0_CLFC)
45 mtspr SPRN_L1CSR0, r0 /* Invalidate */
47 1: mfspr r0, SPRN_L1CSR0
48 andi. r3, r0, L1CSR0_CLFC
49 bne+ 1b /* Wait for lock bits reset */
50 oris r0, r0, L1CSR0_CPE@h
51 ori r0, r0, L1CSR0_DCE
54 mtspr SPRN_L1CSR0, r0 /* Enable */
59 * FIXME - we haven't yet done testing to determine a reasonable default
60 * value for PW20_WAIT_IDLE_BIT.
62 #define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
63 _GLOBAL(setup_pw20_idle)
64 mfspr r3, SPRN_PWRMGTCR0
66 /* Set PW20_WAIT bit, enable pw20 state*/
67 ori r3, r3, PWRMGTCR0_PW20_WAIT
68 li r11, PW20_WAIT_IDLE_BIT
70 /* Set Automatic PW20 Core Idle Count */
71 rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
73 mtspr SPRN_PWRMGTCR0, r3
78 * FIXME - we haven't yet done testing to determine a reasonable default
79 * value for AV_WAIT_IDLE_BIT.
81 #define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
82 _GLOBAL(setup_altivec_idle)
83 mfspr r3, SPRN_PWRMGTCR0
85 /* Enable Altivec Idle */
86 oris r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
87 li r11, AV_WAIT_IDLE_BIT
89 /* Set Automatic AltiVec Idle Count */
90 rlwimi r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
92 mtspr SPRN_PWRMGTCR0, r3
96 #ifdef CONFIG_PPC_E500MC
97 _GLOBAL(__setup_cpu_e6500)
100 bl setup_altivec_ivors
101 /* Touch IVOR42 only if the CPU supports E.HV category */
102 mfspr r10,SPRN_MMUCFG
103 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
109 bl setup_altivec_idle
113 #endif /* CONFIG_PPC_E500MC */
117 _GLOBAL(__setup_cpu_e200)
118 /* enable dedicated debug exception handling resources (Debug APU) */
120 ori r3,r3,HID0_DAPUEN@l
123 #endif /* CONFIG_E200 */
126 #ifndef CONFIG_PPC_E500MC
127 _GLOBAL(__setup_cpu_e500v1)
128 _GLOBAL(__setup_cpu_e500v2)
130 bl __e500_icache_setup
131 bl __e500_dcache_setup
132 bl __setup_e500_ivors
133 #if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
134 /* Ensure that RFXE is set */
136 oris r3,r3,HID1_RFXE@h
141 #else /* CONFIG_PPC_E500MC */
142 _GLOBAL(__setup_cpu_e500mc)
143 _GLOBAL(__setup_cpu_e5500)
145 bl __e500_icache_setup
146 bl __e500_dcache_setup
147 bl __setup_e500mc_ivors
149 * We only want to touch IVOR38-41 if we're running on hardware
150 * that supports category E.HV. The architectural way to determine
151 * this is MMUCFG[LPIDSIZE].
153 mfspr r3, SPRN_MMUCFG
154 rlwinm. r3, r3, 0, MMUCFG_LPIDSIZE
159 lwz r3, CPU_SPEC_FEATURES(r4)
160 /* We need this check as cpu_setup is also called for
161 * the secondary cores. So, if we have already cleared
162 * the feature on the primary core, avoid doing it on the
165 andi. r6, r3, CPU_FTR_EMB_HV
167 rlwinm r3, r3, 0, ~CPU_FTR_EMB_HV
168 stw r3, CPU_SPEC_FEATURES(r4)
172 #endif /* CONFIG_PPC_E500MC */
173 #endif /* CONFIG_E500 */
174 #endif /* CONFIG_PPC32 */
176 #ifdef CONFIG_PPC_BOOK3E_64
177 _GLOBAL(__restore_cpu_e6500)
179 bl setup_altivec_ivors
180 /* Touch IVOR42 only if the CPU supports E.HV category */
181 mfspr r10,SPRN_MMUCFG
182 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
187 bl setup_altivec_idle
188 bl __restore_cpu_e5500
192 _GLOBAL(__restore_cpu_e5500)
194 bl __e500_icache_setup
195 bl __e500_dcache_setup
196 bl __setup_base_ivors
197 bl setup_perfmon_ivor
198 bl setup_doorbell_ivors
200 * We only want to touch IVOR38-41 if we're running on hardware
201 * that supports category E.HV. The architectural way to determine
202 * this is MMUCFG[LPIDSIZE].
204 mfspr r10,SPRN_MMUCFG
205 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
212 _GLOBAL(__setup_cpu_e5500)
214 bl __e500_icache_setup
215 bl __e500_dcache_setup
216 bl __setup_base_ivors
217 bl setup_perfmon_ivor
218 bl setup_doorbell_ivors
220 * We only want to touch IVOR38-41 if we're running on hardware
221 * that supports category E.HV. The architectural way to determine
222 * this is MMUCFG[LPIDSIZE].
224 mfspr r10,SPRN_MMUCFG
225 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
230 ld r10,CPU_SPEC_FEATURES(r4)
231 LOAD_REG_IMMEDIATE(r9,CPU_FTR_EMB_HV)
233 std r10,CPU_SPEC_FEATURES(r4)
239 /* flush L1 date cache, it can apply to e500v2, e500mc and e5500 */
240 _GLOBAL(flush_dcache_L1)
245 rlwinm r5,r3,9,3 /* Extract cache block size */
246 twlgti r5,1 /* Only 32 and 64 byte cache blocks
247 * are currently defined.
250 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
251 * log2(number of ways)
253 slw r5,r4,r5 /* r5 = cache block size */
255 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
256 mulli r7,r7,13 /* An 8-way cache will require 13
261 /* save off HID0 and set DCFA */
263 ori r9,r8,HID0_DCFA@l
267 LOAD_REG_IMMEDIATE(r6, KERNELBASE)
271 1: lwz r3,0(r4) /* Load... */
279 1: dcbf 0,r4 /* ...and flush. */
292 /* skip L2 cache on P2040/P2040E as they have no L2 cache */
294 /* shift right by 8 bits and clear E bit of SVR */
295 rlwinm r4, r3, 24, ~0x800
298 ori r3, r3, SVR_P2040@l
308 /* flush backside L2 cache */
309 flush_backside_L2_cache:
316 /* Flush the L2 cache */
317 mfspr r3, SPRN_L2CSR0
318 ori r3, r3, L2CSR0_L2FL@l
324 /* check if it is complete */
325 1: mfspr r3,SPRN_L2CSR0
326 andi. r3, r3, L2CSR0_L2FL@l
331 _GLOBAL(cpu_down_flush_e500v2)
337 _GLOBAL(cpu_down_flush_e500mc)
338 _GLOBAL(cpu_down_flush_e5500)
341 bl flush_backside_L2_cache
345 /* L1 Data Cache of e6500 contains no modified data, no flush is required */
346 _GLOBAL(cpu_down_flush_e6500)