arch/powerpc/kernel/cpu_setup_fsl_booke.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  * Kumar Gala <galak@kernel.crashing.org>
   4  * Copyright 2009 Freescale Semiconductor, Inc.
   5  *
   6  * Based on cpu_setup_6xx code by
   7  * Benjamin Herrenschmidt <benh@kernel.crashing.org>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  */
  15
  16 #include <asm/processor.h>
  17 #include <asm/cputable.h>
  18 #include <asm/ppc_asm.h>
  19 #include <asm/mmu-book3e.h>
  20 #include <asm/asm-offsets.h>
  21
  22 _GLOBAL(__e500_icache_setup)
  23         mfspr   r0, SPRN_L1CSR1
  24         andi.   r3, r0, L1CSR1_ICE
  25         bnelr                           /* Already enabled */
  26         oris    r0, r0, L1CSR1_CPE@h
  27         ori     r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR |  L1CSR1_ICE)
  28         mtspr   SPRN_L1CSR1, r0         /* Enable I-Cache */
  29         isync
  30         blr
  31
  32 _GLOBAL(__e500_dcache_setup)
  33         mfspr   r0, SPRN_L1CSR0
  34         andi.   r3, r0, L1CSR0_DCE
  35         bnelr                           /* Already enabled */
  36         msync
  37         isync
  38         li      r0, 0
  39         mtspr   SPRN_L1CSR0, r0         /* Disable */
  40         msync
  41         isync
  42         li      r0, (L1CSR0_DCFI | L1CSR0_CLFC)
  43         mtspr   SPRN_L1CSR0, r0         /* Invalidate */
  44         isync
  45 1:      mfspr   r0, SPRN_L1CSR0
  46         andi.   r3, r0, L1CSR0_CLFC
  47         bne+    1b                      /* Wait for lock bits reset */
  48         oris    r0, r0, L1CSR0_CPE@h
  49         ori     r0, r0, L1CSR0_DCE
  50         msync
  51         isync
  52         mtspr   SPRN_L1CSR0, r0         /* Enable */
  53         isync
  54         blr
  55
  56 /*
  57  * FIXME - we haven't yet done testing to determine a reasonable default
  58  * value for PW20_WAIT_IDLE_BIT.
  59  */
  60 #define PW20_WAIT_IDLE_BIT              50 /* 1ms, TB frequency is 41.66MHZ */
  61 _GLOBAL(setup_pw20_idle)
  62         mfspr   r3, SPRN_PWRMGTCR0
  63
  64         /* Set PW20_WAIT bit, enable pw20 state*/
  65         ori     r3, r3, PWRMGTCR0_PW20_WAIT
  66         li      r11, PW20_WAIT_IDLE_BIT
  67
  68         /* Set Automatic PW20 Core Idle Count */
  69         rlwimi  r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
  70
  71         mtspr   SPRN_PWRMGTCR0, r3
  72
  73         blr
  74
  75 /*
  76  * FIXME - we haven't yet done testing to determine a reasonable default
  77  * value for AV_WAIT_IDLE_BIT.
  78  */
  79 #define AV_WAIT_IDLE_BIT                50 /* 1ms, TB frequency is 41.66MHZ */
  80 _GLOBAL(setup_altivec_idle)
  81         mfspr   r3, SPRN_PWRMGTCR0
  82
  83         /* Enable Altivec Idle */
  84         oris    r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
  85         li      r11, AV_WAIT_IDLE_BIT
  86
  87         /* Set Automatic AltiVec Idle Count */
  88         rlwimi  r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
  89
  90         mtspr   SPRN_PWRMGTCR0, r3
  91
  92         blr
  93
  94 _GLOBAL(__setup_cpu_e6500)
  95         mflr    r6
  96 #ifdef CONFIG_PPC64
  97         bl      .setup_altivec_ivors
  98         /* Touch IVOR42 only if the CPU supports E.HV category */
  99         mfspr   r10,SPRN_MMUCFG
 100         rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
 101         beq     1f
 102         bl      .setup_lrat_ivor
 103 1:
 104 #endif
 105         bl      setup_pw20_idle
 106         bl      setup_altivec_idle
 107         bl      __setup_cpu_e5500
 108         mtlr    r6
 109         blr
 110
 111 #ifdef CONFIG_PPC32
 112 _GLOBAL(__setup_cpu_e200)
 113         /* enable dedicated debug exception handling resources (Debug APU) */
 114         mfspr   r3,SPRN_HID0
 115         ori     r3,r3,HID0_DAPUEN@l
 116         mtspr   SPRN_HID0,r3
 117         b       __setup_e200_ivors
 118 _GLOBAL(__setup_cpu_e500v1)
 119 _GLOBAL(__setup_cpu_e500v2)
 120         mflr    r4
 121         bl      __e500_icache_setup
 122         bl      __e500_dcache_setup
 123         bl      __setup_e500_ivors
 124 #if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
 125         /* Ensure that RFXE is set */
 126         mfspr   r3,SPRN_HID1
 127         oris    r3,r3,HID1_RFXE@h
 128         mtspr   SPRN_HID1,r3
 129 #endif
 130         mtlr    r4
 131         blr
 132 _GLOBAL(__setup_cpu_e500mc)
 133 _GLOBAL(__setup_cpu_e5500)
 134         mflr    r5
 135         bl      __e500_icache_setup
 136         bl      __e500_dcache_setup
 137         bl      __setup_e500mc_ivors
 138         /*
 139          * We only want to touch IVOR38-41 if we're running on hardware
 140          * that supports category E.HV.  The architectural way to determine
 141          * this is MMUCFG[LPIDSIZE].
 142          */
 143         mfspr   r3, SPRN_MMUCFG
 144         rlwinm. r3, r3, 0, MMUCFG_LPIDSIZE
 145         beq     1f
 146         bl      __setup_ehv_ivors
 147         b       2f
 148 1:
 149         lwz     r3, CPU_SPEC_FEATURES(r4)
 150         /* We need this check as cpu_setup is also called for
 151          * the secondary cores. So, if we have already cleared
 152          * the feature on the primary core, avoid doing it on the
 153          * secondary core.
 154          */
 155         andis.  r6, r3, CPU_FTR_EMB_HV@h
 156         beq     2f
 157         rlwinm  r3, r3, 0, ~CPU_FTR_EMB_HV
 158         stw     r3, CPU_SPEC_FEATURES(r4)
 159 2:
 160         mtlr    r5
 161         blr
 162 #endif
 163
 164 #ifdef CONFIG_PPC_BOOK3E_64
 165 _GLOBAL(__restore_cpu_e6500)
 166         mflr    r5
 167         bl      .setup_altivec_ivors
 168         /* Touch IVOR42 only if the CPU supports E.HV category */
 169         mfspr   r10,SPRN_MMUCFG
 170         rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
 171         beq     1f
 172         bl      .setup_lrat_ivor
 173 1:
 174         bl      .setup_pw20_idle
 175         bl      .setup_altivec_idle
 176         bl      __restore_cpu_e5500
 177         mtlr    r5
 178         blr
 179
 180 _GLOBAL(__restore_cpu_e5500)
 181         mflr    r4
 182         bl      __e500_icache_setup
 183         bl      __e500_dcache_setup
 184         bl      .__setup_base_ivors
 185         bl      .setup_perfmon_ivor
 186         bl      .setup_doorbell_ivors
 187         /*
 188          * We only want to touch IVOR38-41 if we're running on hardware
 189          * that supports category E.HV.  The architectural way to determine
 190          * this is MMUCFG[LPIDSIZE].
 191          */
 192         mfspr   r10,SPRN_MMUCFG
 193         rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
 194         beq     1f
 195         bl      .setup_ehv_ivors
 196 1:
 197         mtlr    r4
 198         blr
 199
 200 _GLOBAL(__setup_cpu_e5500)
 201         mflr    r5
 202         bl      __e500_icache_setup
 203         bl      __e500_dcache_setup
 204         bl      .__setup_base_ivors
 205         bl      .setup_perfmon_ivor
 206         bl      .setup_doorbell_ivors
 207         /*
 208          * We only want to touch IVOR38-41 if we're running on hardware
 209          * that supports category E.HV.  The architectural way to determine
 210          * this is MMUCFG[LPIDSIZE].
 211          */
 212         mfspr   r10,SPRN_MMUCFG
 213         rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
 214         beq     1f
 215         bl      .setup_ehv_ivors
 216         b       2f
 217 1:
 218         ld      r10,CPU_SPEC_FEATURES(r4)
 219         LOAD_REG_IMMEDIATE(r9,CPU_FTR_EMB_HV)
 220         andc    r10,r10,r9
 221         std     r10,CPU_SPEC_FEATURES(r4)
 222 2:
 223         mtlr    r5
 224         blr
 225 #endif