arch/powerpc/kernel/cpu_setup_power.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  *
  10  */
  11
  12 #include <asm/processor.h>
  13 #include <asm/page.h>
  14 #include <asm/cputable.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/cache.h>
  18 #include <asm/book3s/64/mmu-hash.h>
  19
  20 /* Entry: r3 = crap, r4 = ptr to cputable entry
  21  *
  22  * Note that we can be called twice for pseudo-PVRs
  23  */
  24 _GLOBAL(__setup_cpu_power7)
  25         mflr    r11
  26         bl      __init_hvmode_206
  27         mtlr    r11
  28         beqlr
  29         li      r0,0
  30         mtspr   SPRN_LPID,r0
  31         mfspr   r3,SPRN_LPCR
  32         bl      __init_LPCR
  33         bl      __init_tlb_power7
  34         mtlr    r11
  35         blr
  36
  37 _GLOBAL(__restore_cpu_power7)
  38         mflr    r11
  39         mfmsr   r3
  40         rldicl. r0,r3,4,63
  41         beqlr
  42         li      r0,0
  43         mtspr   SPRN_LPID,r0
  44         mfspr   r3,SPRN_LPCR
  45         bl      __init_LPCR
  46         bl      __init_tlb_power7
  47         mtlr    r11
  48         blr
  49
  50 _GLOBAL(__setup_cpu_power8)
  51         mflr    r11
  52         bl      __init_FSCR
  53         bl      __init_PMU
  54         bl      __init_PMU_ISA207
  55         bl      __init_hvmode_206
  56         mtlr    r11
  57         beqlr
  58         li      r0,0
  59         mtspr   SPRN_LPID,r0
  60         mfspr   r3,SPRN_LPCR
  61         ori     r3, r3, LPCR_PECEDH
  62         bl      __init_LPCR
  63         bl      __init_HFSCR
  64         bl      __init_tlb_power8
  65         bl      __init_PMU_HV
  66         bl      __init_PMU_HV_ISA207
  67         mtlr    r11
  68         blr
  69
  70 _GLOBAL(__restore_cpu_power8)
  71         mflr    r11
  72         bl      __init_FSCR
  73         bl      __init_PMU
  74         bl      __init_PMU_ISA207
  75         mfmsr   r3
  76         rldicl. r0,r3,4,63
  77         mtlr    r11
  78         beqlr
  79         li      r0,0
  80         mtspr   SPRN_LPID,r0
  81         mfspr   r3,SPRN_LPCR
  82         ori     r3, r3, LPCR_PECEDH
  83         bl      __init_LPCR
  84         bl      __init_HFSCR
  85         bl      __init_tlb_power8
  86         bl      __init_PMU_HV
  87         bl      __init_PMU_HV_ISA207
  88         mtlr    r11
  89         blr
  90
  91 _GLOBAL(__setup_cpu_power9)
  92         mflr    r11
  93         bl      __init_FSCR
  94         bl      __init_PMU
  95         bl      __init_hvmode_206
  96         mtlr    r11
  97         beqlr
  98         li      r0,0
  99         mtspr   SPRN_LPID,r0
 100         mfspr   r3,SPRN_LPCR
 101         ori     r3, r3, LPCR_PECEDH
 102         ori     r3, r3, LPCR_HVICE
 103         bl      __init_LPCR
 104         bl      __init_HFSCR
 105         bl      __init_tlb_power9
 106         bl      __init_PMU_HV
 107         mtlr    r11
 108         blr
 109
 110 _GLOBAL(__restore_cpu_power9)
 111         mflr    r11
 112         bl      __init_FSCR
 113         bl      __init_PMU
 114         mfmsr   r3
 115         rldicl. r0,r3,4,63
 116         mtlr    r11
 117         beqlr
 118         li      r0,0
 119         mtspr   SPRN_LPID,r0
 120         mfspr   r3,SPRN_LPCR
 121         ori     r3, r3, LPCR_PECEDH
 122         ori     r3, r3, LPCR_HVICE
 123         bl      __init_LPCR
 124         bl      __init_HFSCR
 125         bl      __init_tlb_power9
 126         bl      __init_PMU_HV
 127         mtlr    r11
 128         blr
 129
 130 __init_hvmode_206:
 131         /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
 132         mfmsr   r3
 133         rldicl. r0,r3,4,63
 134         bnelr
 135         ld      r5,CPU_SPEC_FEATURES(r4)
 136         LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
 137         xor     r5,r5,r6
 138         std     r5,CPU_SPEC_FEATURES(r4)
 139         blr
 140
 141 __init_LPCR:
 142         /* Setup a sane LPCR:
 143          *   Called with initial LPCR in R3
 144          *
 145          *   LPES = 0b01 (HSRR0/1 used for 0x500)
 146          *   PECE = 0b111
 147          *   DPFD = 4
 148          *   HDICE = 0
 149          *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
 150          *   VRMASD = 0b10000 (L=1, LP=00)
 151          *
 152          * Other bits untouched for now
 153          */
 154         li      r5,1
 155         rldimi  r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
 156         ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
 157         li      r5,4
 158         rldimi  r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
 159         clrrdi  r3,r3,1         /* clear HDICE */
 160         li      r5,4
 161         rldimi  r3,r5, LPCR_VC_SH, 0
 162         li      r5,0x10
 163         rldimi  r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
 164         mtspr   SPRN_LPCR,r3
 165         isync
 166         blr
 167
 168 __init_FSCR:
 169         mfspr   r3,SPRN_FSCR
 170         ori     r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
 171         mtspr   SPRN_FSCR,r3
 172         blr
 173
 174 __init_HFSCR:
 175         mfspr   r3,SPRN_HFSCR
 176         ori     r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
 177                       HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
 178         mtspr   SPRN_HFSCR,r3
 179         blr
 180
 181 /*
 182  * Clear the TLB using the specified IS form of tlbiel instruction
 183  * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
 184  */
 185 __init_tlb_power7:
 186         li      r6,POWER7_TLB_SETS
 187         mtctr   r6
 188         li      r7,0xc00        /* IS field = 0b11 */
 189         ptesync
 190 2:      tlbiel  r7
 191         addi    r7,r7,0x1000
 192         bdnz    2b
 193         ptesync
 194 1:      blr
 195
 196 __init_tlb_power8:
 197         li      r6,POWER8_TLB_SETS
 198         mtctr   r6
 199         li      r7,0xc00        /* IS field = 0b11 */
 200         ptesync
 201 2:      tlbiel  r7
 202         addi    r7,r7,0x1000
 203         bdnz    2b
 204         ptesync
 205 1:      blr
 206
 207 __init_tlb_power9:
 208         li      r6,POWER9_TLB_SETS_HASH
 209         mtctr   r6
 210         li      r7,0xc00        /* IS field = 0b11 */
 211         ptesync
 212 2:      tlbiel  r7
 213         addi    r7,r7,0x1000
 214         bdnz    2b
 215         ptesync
 216 1:      blr
 217
 218 __init_PMU_HV:
 219         li      r5,0
 220         mtspr   SPRN_MMCRC,r5
 221         blr
 222
 223 __init_PMU_HV_ISA207:
 224         li      r5,0
 225         mtspr   SPRN_MMCRH,r5
 226         blr
 227
 228 __init_PMU:
 229         li      r5,0
 230         mtspr   SPRN_MMCRA,r5
 231         mtspr   SPRN_MMCR0,r5
 232         mtspr   SPRN_MMCR1,r5
 233         mtspr   SPRN_MMCR2,r5
 234         blr
 235
 236 __init_PMU_ISA207:
 237         li      r5,0
 238         mtspr   SPRN_MMCRS,r5
 239         blr