arch/powerpc/kernel/cpu_setup_power4.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  *
  10  */
  11
  12 #include <asm/processor.h>
  13 #include <asm/page.h>
  14 #include <asm/cputable.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/cache.h>
  18
  19 _GLOBAL(__970_cpu_preinit)
  20         /*
  21          * Do nothing if not running in HV mode
  22          */
  23         mfmsr   r0
  24         rldicl. r0,r0,4,63
  25         beqlr
  26
  27         /*
  28          * Deal only with PPC970 and PPC970FX.
  29          */
  30         mfspr   r0,SPRN_PVR
  31         srwi    r0,r0,16
  32         cmpwi   r0,0x39
  33         beq     1f
  34         cmpwi   r0,0x3c
  35         beq     1f
  36         cmpwi   r0,0x44
  37         bnelr
  38 1:
  39
  40         /* Make sure HID4:rm_ci is off before MMU is turned off, that large
  41          * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
  42          * HID5:DCBZ32_ill
  43          */
  44         li      r0,0
  45         mfspr   r3,SPRN_HID4
  46         rldimi  r3,r0,40,23     /* clear bit 23 (rm_ci) */
  47         rldimi  r3,r0,2,61      /* clear bit 61 (lg_pg_en) */
  48         sync
  49         mtspr   SPRN_HID4,r3
  50         isync
  51         sync
  52         mfspr   r3,SPRN_HID5
  53         rldimi  r3,r0,6,56      /* clear bits 56 & 57 (DCBZ*) */
  54         sync
  55         mtspr   SPRN_HID5,r3
  56         isync
  57         sync
  58
  59         /* Setup some basic HID1 features */
  60         mfspr   r0,SPRN_HID1
  61         li      r3,0x1200               /* enable i-fetch cacheability */
  62         sldi    r3,r3,44                /* and prefetch */
  63         or      r0,r0,r3
  64         mtspr   SPRN_HID1,r0
  65         mtspr   SPRN_HID1,r0
  66         isync
  67
  68         /* Clear HIOR */
  69         li      r0,0
  70         sync
  71         mtspr   SPRN_HIOR,0             /* Clear interrupt prefix */
  72         isync
  73         blr
  74
  75 _GLOBAL(__setup_cpu_ppc970)
  76         mfspr   r0,SPRN_HID0
  77         li      r11,5                   /* clear DOZE and SLEEP */
  78         rldimi  r0,r11,52,8             /* set NAP and DPM */
  79         mtspr   SPRN_HID0,r0
  80         mfspr   r0,SPRN_HID0
  81         mfspr   r0,SPRN_HID0
  82         mfspr   r0,SPRN_HID0
  83         mfspr   r0,SPRN_HID0
  84         mfspr   r0,SPRN_HID0
  85         mfspr   r0,SPRN_HID0
  86         sync
  87         isync
  88         blr
  89
  90 /* Definitions for the table use to save CPU states */
  91 #define CS_HID0         0
  92 #define CS_HID1         8
  93 #define CS_HID4         16
  94 #define CS_HID5         24
  95 #define CS_SIZE         32
  96
  97         .data
  98         .balign L1_CACHE_BYTES,0
  99 cpu_state_storage:
 100         .space  CS_SIZE
 101         .balign L1_CACHE_BYTES,0
 102         .text
 103
 104 /* Called in normal context to backup CPU 0 state. This
 105  * does not include cache settings. This function is also
 106  * called for machine sleep. This does not include the MMU
 107  * setup, BATs, etc... but rather the "special" registers
 108  * like HID0, HID1, HID4, etc...
 109  */
 110 _GLOBAL(__save_cpu_setup)
 111         /* Some CR fields are volatile, we back it up all */
 112         mfcr    r7
 113
 114         /* Get storage ptr */
 115         LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
 116
 117         /* We only deal with 970 for now */
 118         mfspr   r0,SPRN_PVR
 119         srwi    r0,r0,16
 120         cmpwi   r0,0x39
 121         beq     1f
 122         cmpwi   r0,0x3c
 123         beq     1f
 124         cmpwi   r0,0x44
 125         bne     2f
 126
 127 1:      /* skip if not running in HV mode */
 128         mfmsr   r0
 129         rldicl. r0,r0,4,63
 130         beq     2f
 131
 132         /* Save HID0,1,4 and 5 */
 133         mfspr   r3,SPRN_HID0
 134         std     r3,CS_HID0(r5)
 135         mfspr   r3,SPRN_HID1
 136         std     r3,CS_HID1(r5)
 137         mfspr   r3,SPRN_HID4
 138         std     r3,CS_HID4(r5)
 139         mfspr   r3,SPRN_HID5
 140         std     r3,CS_HID5(r5)
 141
 142 2:
 143         mtcr    r7
 144         blr
 145
 146 /* Called with no MMU context (typically MSR:IR/DR off) to
 147  * restore CPU state as backed up by the previous
 148  * function. This does not include cache setting
 149  */
 150 _GLOBAL(__restore_cpu_setup)
 151         /* Get storage ptr (FIXME when using anton reloc as we
 152          * are running with translation disabled here
 153          */
 154         LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
 155
 156         /* We only deal with 970 for now */
 157         mfspr   r0,SPRN_PVR
 158         srwi    r0,r0,16
 159         cmpwi   r0,0x39
 160         beq     1f
 161         cmpwi   r0,0x3c
 162         beq     1f
 163         cmpwi   r0,0x44
 164         bnelr
 165
 166 1:      /* skip if not running in HV mode */
 167         mfmsr   r0
 168         rldicl. r0,r0,4,63
 169         beqlr
 170
 171         /* Before accessing memory, we make sure rm_ci is clear */
 172         li      r0,0
 173         mfspr   r3,SPRN_HID4
 174         rldimi  r3,r0,40,23     /* clear bit 23 (rm_ci) */
 175         sync
 176         mtspr   SPRN_HID4,r3
 177         isync
 178         sync
 179
 180         /* Clear interrupt prefix */
 181         li      r0,0
 182         sync
 183         mtspr   SPRN_HIOR,0
 184         isync
 185
 186         /* Restore HID0 */
 187         ld      r3,CS_HID0(r5)
 188         sync
 189         isync
 190         mtspr   SPRN_HID0,r3
 191         mfspr   r3,SPRN_HID0
 192         mfspr   r3,SPRN_HID0
 193         mfspr   r3,SPRN_HID0
 194         mfspr   r3,SPRN_HID0
 195         mfspr   r3,SPRN_HID0
 196         mfspr   r3,SPRN_HID0
 197         sync
 198         isync
 199
 200         /* Restore HID1 */
 201         ld      r3,CS_HID1(r5)
 202         sync
 203         isync
 204         mtspr   SPRN_HID1,r3
 205         mtspr   SPRN_HID1,r3
 206         sync
 207         isync
 208
 209         /* Restore HID4 */
 210         ld      r3,CS_HID4(r5)
 211         sync
 212         isync
 213         mtspr   SPRN_HID4,r3
 214         sync
 215         isync
 216
 217         /* Restore HID5 */
 218         ld      r3,CS_HID5(r5)
 219         sync
 220         isync
 221         mtspr   SPRN_HID5,r3
 222         sync
 223         isync
 224         blr
 225