arch/powerpc/kernel/cpu_setup_power7.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  *
  10  */
  11
  12 #include <asm/processor.h>
  13 #include <asm/page.h>
  14 #include <asm/cputable.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/cache.h>
  18
  19 /* Entry: r3 = crap, r4 = ptr to cputable entry
  20  *
  21  * Note that we can be called twice for pseudo-PVRs
  22  */
  23 _GLOBAL(__setup_cpu_power7)
  24         mflr    r11
  25         bl      __init_hvmode_206
  26         mtlr    r11
  27         beqlr
  28         li      r0,0
  29         mtspr   SPRN_LPID,r0
  30         bl      __init_LPCR
  31         bl      __init_TLB
  32         mtlr    r11
  33         blr
  34
  35 _GLOBAL(__restore_cpu_power7)
  36         mflr    r11
  37         mfmsr   r3
  38         rldicl. r0,r3,4,63
  39         beqlr
  40         li      r0,0
  41         mtspr   SPRN_LPID,r0
  42         bl      __init_LPCR
  43         bl      __init_TLB
  44         mtlr    r11
  45         blr
  46
  47 __init_hvmode_206:
  48         /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
  49         mfmsr   r3
  50         rldicl. r0,r3,4,63
  51         bnelr
  52         ld      r5,CPU_SPEC_FEATURES(r4)
  53         LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
  54         xor     r5,r5,r6
  55         std     r5,CPU_SPEC_FEATURES(r4)
  56         blr
  57
  58 __init_LPCR:
  59         /* Setup a sane LPCR:
  60          *
  61          *   LPES = 0b01 (HSRR0/1 used for 0x500)
  62          *   PECE = 0b111
  63          *   DPFD = 4
  64          *   HDICE = 0
  65          *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
  66          *   VRMASD = 0b10000 (L=1, LP=00)
  67          *
  68          * Other bits untouched for now
  69          */
  70         mfspr   r3,SPRN_LPCR
  71         li      r5,1
  72         rldimi  r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
  73         ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
  74         li      r5,4
  75         rldimi  r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
  76         clrrdi  r3,r3,1         /* clear HDICE */
  77         li      r5,4
  78         rldimi  r3,r5, LPCR_VC_SH, 0
  79         li      r5,0x10
  80         rldimi  r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
  81         mtspr   SPRN_LPCR,r3
  82         isync
  83         blr
  84
  85 __init_TLB:
  86         /* Clear the TLB */
  87         li      r6,128
  88         mtctr   r6
  89         li      r7,0xc00        /* IS field = 0b11 */
  90         ptesync
  91 2:      tlbiel  r7
  92         addi    r7,r7,0x1000
  93         bdnz    2b
  94         ptesync
  95 1:      blr