arch/powerpc/kernel/cpu_setup_power7.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  *
  10  */
  11
  12 #include <asm/processor.h>
  13 #include <asm/page.h>
  14 #include <asm/cputable.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/cache.h>
  18
  19 /* Entry: r3 = crap, r4 = ptr to cputable entry
  20  *
  21  * Note that we can be called twice for pseudo-PVRs
  22  */
  23 _GLOBAL(__setup_cpu_power7)
  24         mflr    r11
  25         bl      __init_hvmode_206
  26         mtlr    r11
  27         beqlr
  28         bl      __init_LPCR
  29         mtlr    r11
  30         blr
  31
  32 _GLOBAL(__restore_cpu_power7)
  33         mflr    r11
  34         mfmsr   r3
  35         rldicl. r0,r3,4,63
  36         beqlr
  37         bl      __init_LPCR
  38         mtlr    r11
  39         blr
  40
  41 __init_hvmode_206:
  42         /* Disable CPU_FTR_HVMODE_206 and exit if MSR:HV is not set */
  43         mfmsr   r3
  44         rldicl. r0,r3,4,63
  45         bnelr
  46         ld      r5,CPU_SPEC_FEATURES(r4)
  47         LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE_206)
  48         xor     r5,r5,r6
  49         std     r5,CPU_SPEC_FEATURES(r4)
  50         blr
  51
  52 __init_LPCR:
  53         /* Setup a sane LPCR:
  54          *
  55          *   LPES = 0b01 (HSRR0/1 used for 0x500)
  56          *   PECE = 0b111
  57          *
  58          * Other bits untouched for now
  59          */
  60         mfspr   r3,SPRN_LPCR
  61         ori     r3,r3,(LPCR_LPES0|LPCR_LPES1)
  62         xori    r3,r3, LPCR_LPES0
  63         ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
  64         mtspr   SPRN_LPCR,r3
  65         isync
  66         blr