arch/powerpc/kernel/dma-iommu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corporation
   4  *
   5  * Provide default implementations of the DMA mapping callbacks for
   6  * busses using the iommu infrastructure
   7  */
   8
   9 #include <linux/dma-direct.h>
  10 #include <linux/pci.h>
  11 #include <asm/iommu.h>
  12
  13 /*
  14  * Generic iommu implementation
  15  */
  16
  17 /*
  18  * The coherent mask may be smaller than the real mask, check if we can
  19  * really use a direct window.
  20  */
  21 static inline bool dma_iommu_alloc_bypass(struct device *dev)
  22 {
  23         return dev->archdata.iommu_bypass && !iommu_fixed_is_weak &&
  24                 dma_direct_supported(dev, dev->coherent_dma_mask);
  25 }
  26
  27 static inline bool dma_iommu_map_bypass(struct device *dev,
  28                 unsigned long attrs)
  29 {
  30         return dev->archdata.iommu_bypass &&
  31                 (!iommu_fixed_is_weak || (attrs & DMA_ATTR_WEAK_ORDERING));
  32 }
  33
  34 /* Allocates a contiguous real buffer and creates mappings over it.
  35  * Returns the virtual address of the buffer and sets dma_handle
  36  * to the dma address (mapping) of the first page.
  37  */
  38 static void *dma_iommu_alloc_coherent(struct device *dev, size_t size,
  39                                       dma_addr_t *dma_handle, gfp_t flag,
  40                                       unsigned long attrs)
  41 {
  42         if (dma_iommu_alloc_bypass(dev))
  43                 return dma_direct_alloc(dev, size, dma_handle, flag, attrs);
  44         return iommu_alloc_coherent(dev, get_iommu_table_base(dev), size,
  45                                     dma_handle, dev->coherent_dma_mask, flag,
  46                                     dev_to_node(dev));
  47 }
  48
  49 static void dma_iommu_free_coherent(struct device *dev, size_t size,
  50                                     void *vaddr, dma_addr_t dma_handle,
  51                                     unsigned long attrs)
  52 {
  53         if (dma_iommu_alloc_bypass(dev))
  54                 dma_direct_free(dev, size, vaddr, dma_handle, attrs);
  55         else
  56                 iommu_free_coherent(get_iommu_table_base(dev), size, vaddr,
  57                                 dma_handle);
  58 }
  59
  60 /* Creates TCEs for a user provided buffer.  The user buffer must be
  61  * contiguous real kernel storage (not vmalloc).  The address passed here
  62  * comprises a page address and offset into that page. The dma_addr_t
  63  * returned will point to the same byte within the page as was passed in.
  64  */
  65 static dma_addr_t dma_iommu_map_page(struct device *dev, struct page *page,
  66                                      unsigned long offset, size_t size,
  67                                      enum dma_data_direction direction,
  68                                      unsigned long attrs)
  69 {
  70         if (dma_iommu_map_bypass(dev, attrs))
  71                 return dma_direct_map_page(dev, page, offset, size, direction,
  72                                 attrs);
  73         return iommu_map_page(dev, get_iommu_table_base(dev), page, offset,
  74                               size, device_to_mask(dev), direction, attrs);
  75 }
  76
  77
  78 static void dma_iommu_unmap_page(struct device *dev, dma_addr_t dma_handle,
  79                                  size_t size, enum dma_data_direction direction,
  80                                  unsigned long attrs)
  81 {
  82         if (!dma_iommu_map_bypass(dev, attrs))
  83                 iommu_unmap_page(get_iommu_table_base(dev), dma_handle, size,
  84                                 direction,  attrs);
  85 }
  86
  87
  88 static int dma_iommu_map_sg(struct device *dev, struct scatterlist *sglist,
  89                             int nelems, enum dma_data_direction direction,
  90                             unsigned long attrs)
  91 {
  92         if (dma_iommu_map_bypass(dev, attrs))
  93                 return dma_direct_map_sg(dev, sglist, nelems, direction, attrs);
  94         return ppc_iommu_map_sg(dev, get_iommu_table_base(dev), sglist, nelems,
  95                                 device_to_mask(dev), direction, attrs);
  96 }
  97
  98 static void dma_iommu_unmap_sg(struct device *dev, struct scatterlist *sglist,
  99                 int nelems, enum dma_data_direction direction,
 100                 unsigned long attrs)
 101 {
 102         if (!dma_iommu_map_bypass(dev, attrs))
 103                 ppc_iommu_unmap_sg(get_iommu_table_base(dev), sglist, nelems,
 104                            direction, attrs);
 105 }
 106
 107 static bool dma_iommu_bypass_supported(struct device *dev, u64 mask)
 108 {
 109         struct pci_dev *pdev = to_pci_dev(dev);
 110         struct pci_controller *phb = pci_bus_to_host(pdev->bus);
 111
 112         return phb->controller_ops.iommu_bypass_supported &&
 113                 phb->controller_ops.iommu_bypass_supported(pdev, mask);
 114 }
 115
 116 /* We support DMA to/from any memory page via the iommu */
 117 int dma_iommu_dma_supported(struct device *dev, u64 mask)
 118 {
 119         struct iommu_table *tbl = get_iommu_table_base(dev);
 120
 121         if (!tbl) {
 122                 dev_info(dev, "Warning: IOMMU dma not supported: mask 0x%08llx"
 123                         ", table unavailable\n", mask);
 124                 return 0;
 125         }
 126
 127         if (dev_is_pci(dev) && dma_iommu_bypass_supported(dev, mask)) {
 128                 dev->archdata.iommu_bypass = true;
 129                 dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n");
 130                 return 1;
 131         }
 132
 133         if (tbl->it_offset > (mask >> tbl->it_page_shift)) {
 134                 dev_info(dev, "Warning: IOMMU offset too big for device mask\n");
 135                 dev_info(dev, "mask: 0x%08llx, table offset: 0x%08lx\n",
 136                                 mask, tbl->it_offset << tbl->it_page_shift);
 137                 return 0;
 138         }
 139
 140         dev_dbg(dev, "iommu: not 64-bit, using default ops\n");
 141         dev->archdata.iommu_bypass = false;
 142         return 1;
 143 }
 144
 145 u64 dma_iommu_get_required_mask(struct device *dev)
 146 {
 147         struct iommu_table *tbl = get_iommu_table_base(dev);
 148         u64 mask;
 149
 150         if (!tbl)
 151                 return 0;
 152
 153         if (dev_is_pci(dev)) {
 154                 u64 bypass_mask = dma_direct_get_required_mask(dev);
 155
 156                 if (dma_iommu_bypass_supported(dev, bypass_mask))
 157                         return bypass_mask;
 158         }
 159
 160         mask = 1ULL < (fls_long(tbl->it_offset + tbl->it_size) - 1);
 161         mask += mask - 1;
 162
 163         return mask;
 164 }
 165
 166 const struct dma_map_ops dma_iommu_ops = {
 167         .alloc                  = dma_iommu_alloc_coherent,
 168         .free                   = dma_iommu_free_coherent,
 169         .map_sg                 = dma_iommu_map_sg,
 170         .unmap_sg               = dma_iommu_unmap_sg,
 171         .dma_supported          = dma_iommu_dma_supported,
 172         .map_page               = dma_iommu_map_page,
 173         .unmap_page             = dma_iommu_unmap_page,
 174         .get_required_mask      = dma_iommu_get_required_mask,
 175 };