2 * The file intends to implement PE based on the information from
3 * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device.
4 * All the PEs should be organized as hierarchy tree. The first level
5 * of the tree will be associated to existing PHBs since the particular
6 * PE is only meaningful in one PHB domain.
8 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/delay.h>
26 #include <linux/export.h>
27 #include <linux/gfp.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/string.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/ppc-pci.h>
35 static int eeh_pe_aux_size
= 0;
36 static LIST_HEAD(eeh_phb_pe
);
39 * eeh_set_pe_aux_size - Set PE auxillary data size
40 * @size: PE auxillary data size
42 * Set PE auxillary data size
44 void eeh_set_pe_aux_size(int size
)
49 eeh_pe_aux_size
= size
;
53 * eeh_pe_alloc - Allocate PE
54 * @phb: PCI controller
57 * Allocate PE instance dynamically.
59 static struct eeh_pe
*eeh_pe_alloc(struct pci_controller
*phb
, int type
)
64 alloc_size
= sizeof(struct eeh_pe
);
65 if (eeh_pe_aux_size
) {
66 alloc_size
= ALIGN(alloc_size
, cache_line_size());
67 alloc_size
+= eeh_pe_aux_size
;
71 pe
= kzalloc(alloc_size
, GFP_KERNEL
);
74 /* Initialize PHB PE */
77 INIT_LIST_HEAD(&pe
->child_list
);
78 INIT_LIST_HEAD(&pe
->edevs
);
80 pe
->data
= (void *)pe
+ ALIGN(sizeof(struct eeh_pe
),
86 * eeh_phb_pe_create - Create PHB PE
87 * @phb: PCI controller
89 * The function should be called while the PHB is detected during
90 * system boot or PCI hotplug in order to create PHB PE.
92 int eeh_phb_pe_create(struct pci_controller
*phb
)
97 pe
= eeh_pe_alloc(phb
, EEH_PE_PHB
);
99 pr_err("%s: out of memory!\n", __func__
);
103 /* Put it into the list */
104 list_add_tail(&pe
->child
, &eeh_phb_pe
);
106 pr_debug("EEH: Add PE for PHB#%x\n", phb
->global_number
);
112 * eeh_wait_state - Wait for PE state
114 * @max_wait: maximal period in millisecond
116 * Wait for the state of associated PE. It might take some time
117 * to retrieve the PE's state.
119 int eeh_wait_state(struct eeh_pe
*pe
, int max_wait
)
125 * According to PAPR, the state of PE might be temporarily
126 * unavailable. Under the circumstance, we have to wait
127 * for indicated time determined by firmware. The maximal
128 * wait time is 5 minutes, which is acquired from the original
129 * EEH implementation. Also, the original implementation
130 * also defined the minimal wait time as 1 second.
132 #define EEH_STATE_MIN_WAIT_TIME (1000)
133 #define EEH_STATE_MAX_WAIT_TIME (300 * 1000)
136 ret
= eeh_ops
->get_state(pe
, &mwait
);
138 if (ret
!= EEH_STATE_UNAVAILABLE
)
142 pr_warn("%s: Timeout when getting PE's state (%d)\n",
144 return EEH_STATE_NOT_SUPPORT
;
147 if (mwait
< EEH_STATE_MIN_WAIT_TIME
) {
148 pr_warn("%s: Firmware returned bad wait value %d\n",
150 mwait
= EEH_STATE_MIN_WAIT_TIME
;
151 } else if (mwait
> EEH_STATE_MAX_WAIT_TIME
) {
152 pr_warn("%s: Firmware returned too long wait value %d\n",
154 mwait
= EEH_STATE_MAX_WAIT_TIME
;
157 msleep(min(mwait
, max_wait
));
163 * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB
164 * @phb: PCI controller
166 * The overall PEs form hierarchy tree. The first layer of the
167 * hierarchy tree is composed of PHB PEs. The function is used
168 * to retrieve the corresponding PHB PE according to the given PHB.
170 struct eeh_pe
*eeh_phb_pe_get(struct pci_controller
*phb
)
174 list_for_each_entry(pe
, &eeh_phb_pe
, child
) {
176 * Actually, we needn't check the type since
177 * the PE for PHB has been determined when that
180 if ((pe
->type
& EEH_PE_PHB
) && pe
->phb
== phb
)
188 * eeh_pe_next - Retrieve the next PE in the tree
192 * The function is used to retrieve the next PE in the
195 struct eeh_pe
*eeh_pe_next(struct eeh_pe
*pe
, struct eeh_pe
*root
)
197 struct list_head
*next
= pe
->child_list
.next
;
199 if (next
== &pe
->child_list
) {
203 next
= pe
->child
.next
;
204 if (next
!= &pe
->parent
->child_list
)
210 return list_entry(next
, struct eeh_pe
, child
);
214 * eeh_pe_traverse - Traverse PEs in the specified PHB
217 * @flag: extra parameter to callback
219 * The function is used to traverse the specified PE and its
220 * child PEs. The traversing is to be terminated once the
221 * callback returns something other than NULL, or no more PEs
224 void *eeh_pe_traverse(struct eeh_pe
*root
,
225 eeh_pe_traverse_func fn
, void *flag
)
230 eeh_for_each_pe(root
, pe
) {
239 * eeh_pe_dev_traverse - Traverse the devices from the PE
241 * @fn: function callback
242 * @flag: extra parameter to callback
244 * The function is used to traverse the devices of the specified
245 * PE and its child PEs.
247 void *eeh_pe_dev_traverse(struct eeh_pe
*root
,
248 eeh_edev_traverse_func fn
, void *flag
)
251 struct eeh_dev
*edev
, *tmp
;
255 pr_warn("%s: Invalid PE %p\n",
260 /* Traverse root PE */
261 eeh_for_each_pe(root
, pe
) {
262 eeh_pe_for_each_dev(pe
, edev
, tmp
) {
263 ret
= fn(edev
, flag
);
273 * __eeh_pe_get - Check the PE address
277 * For one particular PE, it can be identified by PE address
278 * or tranditional BDF address. BDF address is composed of
279 * Bus/Device/Function number. The extra data referred by flag
280 * indicates which type of address should be used.
282 struct eeh_pe_get_flag
{
287 static void *__eeh_pe_get(struct eeh_pe
*pe
, void *flag
)
289 struct eeh_pe_get_flag
*tmp
= (struct eeh_pe_get_flag
*) flag
;
291 /* Unexpected PHB PE */
292 if (pe
->type
& EEH_PE_PHB
)
296 * We prefer PE address. For most cases, we should
297 * have non-zero PE address
299 if (eeh_has_flag(EEH_VALID_PE_ZERO
)) {
300 if (tmp
->pe_no
== pe
->addr
)
304 (tmp
->pe_no
== pe
->addr
))
308 /* Try BDF address */
309 if (tmp
->config_addr
&&
310 (tmp
->config_addr
== pe
->config_addr
))
317 * eeh_pe_get - Search PE based on the given address
318 * @phb: PCI controller
320 * @config_addr: Config address
322 * Search the corresponding PE based on the specified address which
323 * is included in the eeh device. The function is used to check if
324 * the associated PE has been created against the PE address. It's
325 * notable that the PE address has 2 format: traditional PE address
326 * which is composed of PCI bus/device/function number, or unified
329 struct eeh_pe
*eeh_pe_get(struct pci_controller
*phb
,
330 int pe_no
, int config_addr
)
332 struct eeh_pe
*root
= eeh_phb_pe_get(phb
);
333 struct eeh_pe_get_flag tmp
= { pe_no
, config_addr
};
336 pe
= eeh_pe_traverse(root
, __eeh_pe_get
, &tmp
);
342 * eeh_pe_get_parent - Retrieve the parent PE
345 * The whole PEs existing in the system are organized as hierarchy
346 * tree. The function is used to retrieve the parent PE according
347 * to the parent EEH device.
349 static struct eeh_pe
*eeh_pe_get_parent(struct eeh_dev
*edev
)
351 struct eeh_dev
*parent
;
352 struct pci_dn
*pdn
= eeh_dev_to_pdn(edev
);
355 * It might have the case for the indirect parent
356 * EEH device already having associated PE, but
357 * the direct parent EEH device doesn't have yet.
360 pdn
= pci_get_pdn(edev
->physfn
);
362 pdn
= pdn
? pdn
->parent
: NULL
;
364 /* We're poking out of PCI territory */
365 parent
= pdn_to_eeh_dev(pdn
);
379 * eeh_add_to_parent_pe - Add EEH device to parent PE
382 * Add EEH device to the parent PE. If the parent PE already
383 * exists, the PE type will be changed to EEH_PE_BUS. Otherwise,
384 * we have to create new PE to hold the EEH device and the new
385 * PE will be linked to its parent PE as well.
387 int eeh_add_to_parent_pe(struct eeh_dev
*edev
)
389 struct eeh_pe
*pe
, *parent
;
390 struct pci_dn
*pdn
= eeh_dev_to_pdn(edev
);
391 int config_addr
= (pdn
->busno
<< 8) | (pdn
->devfn
);
393 /* Check if the PE number is valid */
394 if (!eeh_has_flag(EEH_VALID_PE_ZERO
) && !edev
->pe_config_addr
) {
395 pr_err("%s: Invalid PE#0 for edev 0x%x on PHB#%x\n",
396 __func__
, config_addr
, pdn
->phb
->global_number
);
401 * Search the PE has been existing or not according
402 * to the PE address. If that has been existing, the
403 * PE should be composed of PCI bus and its subordinate
406 pe
= eeh_pe_get(pdn
->phb
, edev
->pe_config_addr
, config_addr
);
407 if (pe
&& !(pe
->type
& EEH_PE_INVALID
)) {
408 /* Mark the PE as type of PCI bus */
409 pe
->type
= EEH_PE_BUS
;
412 /* Put the edev to PE */
413 list_add_tail(&edev
->entry
, &pe
->edevs
);
414 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Bus PE#%x\n",
415 pdn
->phb
->global_number
,
417 PCI_SLOT(pdn
->devfn
),
418 PCI_FUNC(pdn
->devfn
),
421 } else if (pe
&& (pe
->type
& EEH_PE_INVALID
)) {
422 list_add_tail(&edev
->entry
, &pe
->edevs
);
425 * We're running to here because of PCI hotplug caused by
426 * EEH recovery. We need clear EEH_PE_INVALID until the top.
430 if (!(parent
->type
& EEH_PE_INVALID
))
432 parent
->type
&= ~EEH_PE_INVALID
;
433 parent
= parent
->parent
;
436 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Device "
437 "PE#%x, Parent PE#%x\n",
438 pdn
->phb
->global_number
,
440 PCI_SLOT(pdn
->devfn
),
441 PCI_FUNC(pdn
->devfn
),
442 pe
->addr
, pe
->parent
->addr
);
446 /* Create a new EEH PE */
448 pe
= eeh_pe_alloc(pdn
->phb
, EEH_PE_VF
);
450 pe
= eeh_pe_alloc(pdn
->phb
, EEH_PE_DEVICE
);
452 pr_err("%s: out of memory!\n", __func__
);
455 pe
->addr
= edev
->pe_config_addr
;
456 pe
->config_addr
= config_addr
;
459 * Put the new EEH PE into hierarchy tree. If the parent
460 * can't be found, the newly created PE will be attached
461 * to PHB directly. Otherwise, we have to associate the
462 * PE with its parent.
464 parent
= eeh_pe_get_parent(edev
);
466 parent
= eeh_phb_pe_get(pdn
->phb
);
468 pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
469 __func__
, pdn
->phb
->global_number
);
478 * Put the newly created PE into the child list and
479 * link the EEH device accordingly.
481 list_add_tail(&pe
->child
, &parent
->child_list
);
482 list_add_tail(&edev
->entry
, &pe
->edevs
);
484 pr_debug("EEH: Add %04x:%02x:%02x.%01x to "
485 "Device PE#%x, Parent PE#%x\n",
486 pdn
->phb
->global_number
,
488 PCI_SLOT(pdn
->devfn
),
489 PCI_FUNC(pdn
->devfn
),
490 pe
->addr
, pe
->parent
->addr
);
496 * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE
499 * The PE hierarchy tree might be changed when doing PCI hotplug.
500 * Also, the PCI devices or buses could be removed from the system
501 * during EEH recovery. So we have to call the function remove the
502 * corresponding PE accordingly if necessary.
504 int eeh_rmv_from_parent_pe(struct eeh_dev
*edev
)
506 struct eeh_pe
*pe
, *parent
, *child
;
508 struct pci_dn
*pdn
= eeh_dev_to_pdn(edev
);
510 pe
= eeh_dev_to_pe(edev
);
512 pr_debug("%s: No PE found for device %04x:%02x:%02x.%01x\n",
513 __func__
, pdn
->phb
->global_number
,
515 PCI_SLOT(pdn
->devfn
),
516 PCI_FUNC(pdn
->devfn
));
520 /* Remove the EEH device */
522 list_del(&edev
->entry
);
525 * Check if the parent PE includes any EEH devices.
526 * If not, we should delete that. Also, we should
527 * delete the parent PE if it doesn't have associated
528 * child PEs and EEH devices.
532 if (pe
->type
& EEH_PE_PHB
)
535 if (!(pe
->state
& EEH_PE_KEEP
)) {
536 if (list_empty(&pe
->edevs
) &&
537 list_empty(&pe
->child_list
)) {
538 list_del(&pe
->child
);
544 if (list_empty(&pe
->edevs
)) {
546 list_for_each_entry(child
, &pe
->child_list
, child
) {
547 if (!(child
->type
& EEH_PE_INVALID
)) {
554 pe
->type
|= EEH_PE_INVALID
;
567 * eeh_pe_update_time_stamp - Update PE's frozen time stamp
570 * We have time stamp for each PE to trace its time of getting
571 * frozen in last hour. The function should be called to update
572 * the time stamp on first error of the specific PE. On the other
573 * handle, we needn't account for errors happened in last hour.
575 void eeh_pe_update_time_stamp(struct eeh_pe
*pe
)
581 if (pe
->freeze_count
<= 0) {
582 pe
->freeze_count
= 0;
583 pe
->tstamp
= ktime_get_seconds();
585 tstamp
= ktime_get_seconds();
586 if (tstamp
- pe
->tstamp
> 3600) {
588 pe
->freeze_count
= 0;
594 * eeh_pe_state_mark - Mark specified state for PE and its associated device
597 * EEH error affects the current PE and its child PEs. The function
598 * is used to mark appropriate state for the affected PEs and the
599 * associated devices.
601 void eeh_pe_state_mark(struct eeh_pe
*root
, int state
)
605 eeh_for_each_pe(root
, pe
)
606 if (!(pe
->state
& EEH_PE_REMOVED
))
609 EXPORT_SYMBOL_GPL(eeh_pe_state_mark
);
612 * eeh_pe_mark_isolated
615 * Record that a PE has been isolated by marking the PE and it's children as
616 * EEH_PE_ISOLATED (and EEH_PE_CFG_BLOCKED, if required) and their PCI devices
617 * as pci_channel_io_frozen.
619 void eeh_pe_mark_isolated(struct eeh_pe
*root
)
622 struct eeh_dev
*edev
;
623 struct pci_dev
*pdev
;
625 eeh_pe_state_mark(root
, EEH_PE_ISOLATED
);
626 eeh_for_each_pe(root
, pe
) {
627 list_for_each_entry(edev
, &pe
->edevs
, entry
) {
628 pdev
= eeh_dev_to_pci_dev(edev
);
630 pdev
->error_state
= pci_channel_io_frozen
;
632 /* Block PCI config access if required */
633 if (pe
->state
& EEH_PE_CFG_RESTRICTED
)
634 pe
->state
|= EEH_PE_CFG_BLOCKED
;
637 EXPORT_SYMBOL_GPL(eeh_pe_mark_isolated
);
639 static void *__eeh_pe_dev_mode_mark(struct eeh_dev
*edev
, void *flag
)
641 int mode
= *((int *)flag
);
649 * eeh_pe_dev_state_mark - Mark state for all device under the PE
652 * Mark specific state for all child devices of the PE.
654 void eeh_pe_dev_mode_mark(struct eeh_pe
*pe
, int mode
)
656 eeh_pe_dev_traverse(pe
, __eeh_pe_dev_mode_mark
, &mode
);
660 * eeh_pe_state_clear - Clear state for the PE
663 * @include_passed: include passed-through devices?
665 * The function is used to clear the indicated state from the
666 * given PE. Besides, we also clear the check count of the PE
669 void eeh_pe_state_clear(struct eeh_pe
*root
, int state
, bool include_passed
)
672 struct eeh_dev
*edev
, *tmp
;
673 struct pci_dev
*pdev
;
675 eeh_for_each_pe(root
, pe
) {
676 /* Keep the state of permanently removed PE intact */
677 if (pe
->state
& EEH_PE_REMOVED
)
680 if (!include_passed
&& eeh_pe_passed(pe
))
686 * Special treatment on clearing isolated state. Clear
687 * check count since last isolation and put all affected
688 * devices to normal state.
690 if (!(state
& EEH_PE_ISOLATED
))
694 eeh_pe_for_each_dev(pe
, edev
, tmp
) {
695 pdev
= eeh_dev_to_pci_dev(edev
);
699 pdev
->error_state
= pci_channel_io_normal
;
702 /* Unblock PCI config access if required */
703 if (pe
->state
& EEH_PE_CFG_RESTRICTED
)
704 pe
->state
&= ~EEH_PE_CFG_BLOCKED
;
709 * Some PCI bridges (e.g. PLX bridges) have primary/secondary
710 * buses assigned explicitly by firmware, and we probably have
711 * lost that after reset. So we have to delay the check until
712 * the PCI-CFG registers have been restored for the parent
715 * Don't use normal PCI-CFG accessors, which probably has been
716 * blocked on normal path during the stage. So we need utilize
717 * eeh operations, which is always permitted.
719 static void eeh_bridge_check_link(struct eeh_dev
*edev
)
721 struct pci_dn
*pdn
= eeh_dev_to_pdn(edev
);
727 * We only check root port and downstream ports of
730 if (!(edev
->mode
& (EEH_DEV_ROOT_PORT
| EEH_DEV_DS_PORT
)))
733 pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
734 __func__
, pdn
->phb
->global_number
,
736 PCI_SLOT(pdn
->devfn
),
737 PCI_FUNC(pdn
->devfn
));
739 /* Check slot status */
740 cap
= edev
->pcie_cap
;
741 eeh_ops
->read_config(pdn
, cap
+ PCI_EXP_SLTSTA
, 2, &val
);
742 if (!(val
& PCI_EXP_SLTSTA_PDS
)) {
743 pr_debug(" No card in the slot (0x%04x) !\n", val
);
747 /* Check power status if we have the capability */
748 eeh_ops
->read_config(pdn
, cap
+ PCI_EXP_SLTCAP
, 2, &val
);
749 if (val
& PCI_EXP_SLTCAP_PCP
) {
750 eeh_ops
->read_config(pdn
, cap
+ PCI_EXP_SLTCTL
, 2, &val
);
751 if (val
& PCI_EXP_SLTCTL_PCC
) {
752 pr_debug(" In power-off state, power it on ...\n");
753 val
&= ~(PCI_EXP_SLTCTL_PCC
| PCI_EXP_SLTCTL_PIC
);
754 val
|= (0x0100 & PCI_EXP_SLTCTL_PIC
);
755 eeh_ops
->write_config(pdn
, cap
+ PCI_EXP_SLTCTL
, 2, val
);
761 eeh_ops
->read_config(pdn
, cap
+ PCI_EXP_LNKCTL
, 2, &val
);
762 val
&= ~PCI_EXP_LNKCTL_LD
;
763 eeh_ops
->write_config(pdn
, cap
+ PCI_EXP_LNKCTL
, 2, val
);
766 eeh_ops
->read_config(pdn
, cap
+ PCI_EXP_LNKCAP
, 4, &val
);
767 if (!(val
& PCI_EXP_LNKCAP_DLLLARC
)) {
768 pr_debug(" No link reporting capability (0x%08x) \n", val
);
773 /* Wait the link is up until timeout (5s) */
775 while (timeout
< 5000) {
779 eeh_ops
->read_config(pdn
, cap
+ PCI_EXP_LNKSTA
, 2, &val
);
780 if (val
& PCI_EXP_LNKSTA_DLLLA
)
784 if (val
& PCI_EXP_LNKSTA_DLLLA
)
785 pr_debug(" Link up (%s)\n",
786 (val
& PCI_EXP_LNKSTA_CLS_2_5GB
) ? "2.5GB" : "5GB");
788 pr_debug(" Link not ready (0x%04x)\n", val
);
791 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
792 #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
794 static void eeh_restore_bridge_bars(struct eeh_dev
*edev
)
796 struct pci_dn
*pdn
= eeh_dev_to_pdn(edev
);
800 * Device BARs: 0x10 - 0x18
801 * Bus numbers and windows: 0x18 - 0x30
803 for (i
= 4; i
< 13; i
++)
804 eeh_ops
->write_config(pdn
, i
*4, 4, edev
->config_space
[i
]);
806 eeh_ops
->write_config(pdn
, 14*4, 4, edev
->config_space
[14]);
808 /* Cache line & Latency timer: 0xC 0xD */
809 eeh_ops
->write_config(pdn
, PCI_CACHE_LINE_SIZE
, 1,
810 SAVED_BYTE(PCI_CACHE_LINE_SIZE
));
811 eeh_ops
->write_config(pdn
, PCI_LATENCY_TIMER
, 1,
812 SAVED_BYTE(PCI_LATENCY_TIMER
));
813 /* Max latency, min grant, interrupt ping and line: 0x3C */
814 eeh_ops
->write_config(pdn
, 15*4, 4, edev
->config_space
[15]);
816 /* PCI Command: 0x4 */
817 eeh_ops
->write_config(pdn
, PCI_COMMAND
, 4, edev
->config_space
[1] |
818 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
820 /* Check the PCIe link is ready */
821 eeh_bridge_check_link(edev
);
824 static void eeh_restore_device_bars(struct eeh_dev
*edev
)
826 struct pci_dn
*pdn
= eeh_dev_to_pdn(edev
);
830 for (i
= 4; i
< 10; i
++)
831 eeh_ops
->write_config(pdn
, i
*4, 4, edev
->config_space
[i
]);
832 /* 12 == Expansion ROM Address */
833 eeh_ops
->write_config(pdn
, 12*4, 4, edev
->config_space
[12]);
835 eeh_ops
->write_config(pdn
, PCI_CACHE_LINE_SIZE
, 1,
836 SAVED_BYTE(PCI_CACHE_LINE_SIZE
));
837 eeh_ops
->write_config(pdn
, PCI_LATENCY_TIMER
, 1,
838 SAVED_BYTE(PCI_LATENCY_TIMER
));
840 /* max latency, min grant, interrupt pin and line */
841 eeh_ops
->write_config(pdn
, 15*4, 4, edev
->config_space
[15]);
844 * Restore PERR & SERR bits, some devices require it,
845 * don't touch the other command bits
847 eeh_ops
->read_config(pdn
, PCI_COMMAND
, 4, &cmd
);
848 if (edev
->config_space
[1] & PCI_COMMAND_PARITY
)
849 cmd
|= PCI_COMMAND_PARITY
;
851 cmd
&= ~PCI_COMMAND_PARITY
;
852 if (edev
->config_space
[1] & PCI_COMMAND_SERR
)
853 cmd
|= PCI_COMMAND_SERR
;
855 cmd
&= ~PCI_COMMAND_SERR
;
856 eeh_ops
->write_config(pdn
, PCI_COMMAND
, 4, cmd
);
860 * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
864 * Loads the PCI configuration space base address registers,
865 * the expansion ROM base address, the latency timer, and etc.
866 * from the saved values in the device node.
868 static void *eeh_restore_one_device_bars(struct eeh_dev
*edev
, void *flag
)
870 struct pci_dn
*pdn
= eeh_dev_to_pdn(edev
);
872 /* Do special restore for bridges */
873 if (edev
->mode
& EEH_DEV_BRIDGE
)
874 eeh_restore_bridge_bars(edev
);
876 eeh_restore_device_bars(edev
);
878 if (eeh_ops
->restore_config
&& pdn
)
879 eeh_ops
->restore_config(pdn
);
885 * eeh_pe_restore_bars - Restore the PCI config space info
888 * This routine performs a recursive walk to the children
889 * of this device as well.
891 void eeh_pe_restore_bars(struct eeh_pe
*pe
)
894 * We needn't take the EEH lock since eeh_pe_dev_traverse()
897 eeh_pe_dev_traverse(pe
, eeh_restore_one_device_bars
, NULL
);
901 * eeh_pe_loc_get - Retrieve location code binding to the given PE
904 * Retrieve the location code of the given PE. If the primary PE bus
905 * is root bus, we will grab location code from PHB device tree node
906 * or root port. Otherwise, the upstream bridge's device tree node
907 * of the primary PE bus will be checked for the location code.
909 const char *eeh_pe_loc_get(struct eeh_pe
*pe
)
911 struct pci_bus
*bus
= eeh_pe_bus_get(pe
);
912 struct device_node
*dn
;
913 const char *loc
= NULL
;
916 dn
= pci_bus_to_OF_node(bus
);
922 if (pci_is_root_bus(bus
))
923 loc
= of_get_property(dn
, "ibm,io-base-loc-code", NULL
);
925 loc
= of_get_property(dn
, "ibm,slot-location-code",
938 * eeh_pe_bus_get - Retrieve PCI bus according to the given PE
941 * Retrieve the PCI bus according to the given PE. Basically,
942 * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the
943 * primary PCI bus will be retrieved. The parent bus will be
944 * returned for BUS PE. However, we don't have associated PCI
947 struct pci_bus
*eeh_pe_bus_get(struct eeh_pe
*pe
)
949 struct eeh_dev
*edev
;
950 struct pci_dev
*pdev
;
952 if (pe
->type
& EEH_PE_PHB
)
955 /* The primary bus might be cached during probe time */
956 if (pe
->state
& EEH_PE_PRI_BUS
)
959 /* Retrieve the parent PCI bus of first (top) PCI device */
960 edev
= list_first_entry_or_null(&pe
->edevs
, struct eeh_dev
, entry
);
961 pdev
= eeh_dev_to_pci_dev(edev
);