1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains the system call entry code, context switch
14 * code, and exception/interrupt return code for PowerPC.
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <asm/unistd.h>
20 #include <asm/processor.h>
23 #include <asm/thread_info.h>
24 #include <asm/code-patching-asm.h>
25 #include <asm/ppc_asm.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cputable.h>
28 #include <asm/firmware.h>
30 #include <asm/ptrace.h>
31 #include <asm/irqflags.h>
32 #include <asm/hw_irq.h>
33 #include <asm/context_tracking.h>
35 #include <asm/ppc-opcode.h>
36 #include <asm/barrier.h>
37 #include <asm/export.h>
38 #include <asm/asm-compat.h>
39 #ifdef CONFIG_PPC_BOOK3S
40 #include <asm/exception-64s.h>
42 #include <asm/exception-64e.h>
44 #include <asm/feature-fixups.h>
52 .tc sys_call_table[TC],sys_call_table
54 COMPAT_SYS_CALL_TABLE:
55 .tc compat_sys_call_table[TC],compat_sys_call_table
57 /* This value is used to mark exception frames on the stack. */
59 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
64 .globl system_call_common
66 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
68 extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
70 END_FTR_SECTION_IFSET(CPU_FTR_TM)
74 addi r1,r1,-INT_FRAME_SIZE
82 beq 2f /* if from kernel mode */
83 #ifdef CONFIG_PPC_FSL_BOOK3E
84 START_BTB_FLUSH_SECTION
88 ACCOUNT_CPU_USER_ENTRY(r13, r10, r11)
107 * This clears CR0.SO (bit 28), which is the error indication on
108 * return from this system call.
110 rldimi r2,r11,28,(63-28)
117 addi r9,r1,STACK_FRAME_OVERHEAD
118 ld r11,exception_marker@toc(r2)
119 std r11,-16(r9) /* "regshere" marker */
121 kuap_check_amr r10, r11
123 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
126 /* if from user, see if there are any DTL entries to process */
127 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
128 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
129 addi r10,r10,LPPACA_DTLIDX
130 LDX_BE r10,0,r10 /* get log write index */
133 bl accumulate_stolen_time
137 addi r9,r1,STACK_FRAME_OVERHEAD
139 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
140 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
143 * A syscall should always be called with interrupts enabled
144 * so we just unconditionally hard-enable here. When some kind
145 * of irq tracing is used, we additionally check that condition
148 #if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
149 lbz r10,PACAIRQSOFTMASK(r13)
150 1: tdnei r10,IRQS_ENABLED
151 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
154 #ifdef CONFIG_PPC_BOOK3E
160 #endif /* CONFIG_PPC_BOOK3E */
162 system_call: /* label this so stack traces look sane */
163 /* We do need to set SOFTE in the stack frame or the return
164 * from interrupt will be painful
169 ld r11, PACA_THREAD_INFO(r13)
171 andi. r11,r10,_TIF_SYSCALL_DOTRACE
172 bne .Lsyscall_dotrace /* does not return */
173 cmpldi 0,r0,NR_syscalls
174 bge- .Lsyscall_enosys
178 * Need to vector to 32 Bit or default sys_call_table here,
179 * based on caller's run-mode / personality.
181 ld r11,SYS_CALL_TABLE@toc(2)
182 andis. r10,r10,_TIF_32BIT@h
184 ld r11,COMPAT_SYS_CALL_TABLE@toc(2)
196 * Prevent the load of the handler below (based on the user-passed
197 * system call number) being speculatively executed until the test
198 * against NR_syscalls and branch to .Lsyscall_enosys above has
202 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
204 bctrl /* Call handler */
209 #ifdef CONFIG_DEBUG_RSEQ
210 /* Check whether the syscall is issued inside a restartable sequence */
211 addi r3,r1,STACK_FRAME_OVERHEAD
216 ld r12, PACA_THREAD_INFO(r13)
219 #ifdef CONFIG_PPC_BOOK3S
220 /* No MSR:RI on BookE */
222 beq- .Lunrecov_restore
226 * This is a few instructions into the actual syscall exit path (which actually
227 * starts at .Lsyscall_exit) to cater to kprobe blacklisting and to reduce the
228 * number of visible symbols for profiling purposes.
230 * We can probe from system_call until this point as MSR_RI is set. But once it
231 * is cleared below, we won't be able to take a trap.
233 * This is blacklisted from kprobes further below with _ASM_NOKPROBE_SYMBOL().
237 * Disable interrupts so current_thread_info()->flags can't change,
238 * and so that we don't get interrupted after loading SRR0/1.
240 * Leave MSR_RI enabled for now, because with THREAD_INFO_IN_TASK we
241 * could fault on the load of the TI_FLAGS below.
243 #ifdef CONFIG_PPC_BOOK3E
248 #endif /* CONFIG_PPC_BOOK3E */
252 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
253 bne- .Lsyscall_exit_work
257 #ifdef CONFIG_ALTIVEC
258 andis. r0,r8,MSR_VEC@h
261 2: addi r3,r1,STACK_FRAME_OVERHEAD
270 .Lsyscall_error_cont:
273 stdcx. r0,0,r1 /* to clear the reservation */
274 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
278 kuap_check_amr r10, r11
280 #ifdef CONFIG_PPC_BOOK3S
282 * Clear MSR_RI, MSR_EE is already and remains disabled. We could do
283 * this later, but testing shows that doing it here causes less slow
284 * down than doing it closer to the rfid.
291 ACCOUNT_CPU_USER_EXIT(r13, r11, r12)
295 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
297 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
298 std r8, PACATMSCRATCH(r13)
302 * We don't need to restore AMR on the way back to userspace for KUAP.
303 * The value of AMR only matters while we're in the kernel.
305 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
313 b . /* prevent speculative execution */
315 1: /* exit to kernel */
325 b . /* prevent speculative execution */
328 oris r5,r5,0x1000 /* Set SO bit in CR */
331 b .Lsyscall_error_cont
333 /* Traced system call support */
336 addi r3,r1,STACK_FRAME_OVERHEAD
337 bl do_syscall_trace_enter
340 * We use the return value of do_syscall_trace_enter() as the syscall
341 * number. If the syscall was rejected for any reason do_syscall_trace_enter()
342 * returns an invalid syscall number and the test below against
343 * NR_syscalls will fail.
347 /* Restore argument registers just clobbered and/or possibly changed. */
355 /* Repopulate r9 and r10 for the syscall path */
356 addi r9,r1,STACK_FRAME_OVERHEAD
357 ld r10, PACA_THREAD_INFO(r13)
360 cmpldi r0,NR_syscalls
363 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
372 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
373 If TIF_NOERROR is set, just save r3 as it is. */
375 andi. r0,r9,_TIF_RESTOREALL
379 0: cmpld r3,r11 /* r11 is -MAX_ERRNO */
381 andi. r0,r9,_TIF_NOERROR
385 oris r5,r5,0x1000 /* Set SO bit in CR */
388 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
391 /* Clear per-syscall TIF flags if any are set. */
393 li r11,_TIF_PERSYSCALL_MASK
394 addi r12,r12,TI_FLAGS
399 subi r12,r12,TI_FLAGS
401 4: /* Anything else left to do? */
403 lis r3,DEFAULT_PPR@highest /* Set default PPR */
404 sldi r3,r3,32 /* bits 11-13 are used for ppr */
406 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
408 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
409 beq ret_from_except_lite
411 /* Re-enable interrupts */
412 #ifdef CONFIG_PPC_BOOK3E
418 #endif /* CONFIG_PPC_BOOK3E */
421 addi r3,r1,STACK_FRAME_OVERHEAD
422 bl do_syscall_trace_leave
425 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
427 /* Firstly we need to enable TM in the kernel */
430 rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG
433 /* tabort, this dooms the transaction, nothing else */
434 li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
438 * Return directly to userspace. We have corrupted user register state,
439 * but userspace will never see that register state. Execution will
440 * resume after the tbegin of the aborted transaction with the
441 * checkpointed register state.
449 b . /* prevent speculative execution */
451 _ASM_NOKPROBE_SYMBOL(system_call_common);
452 _ASM_NOKPROBE_SYMBOL(system_call_exit);
454 /* Save non-volatile GPRs, if not already saved. */
463 _ASM_NOKPROBE_SYMBOL(save_nvgprs);
467 * The sigsuspend and rt_sigsuspend system calls can call do_signal
468 * and thus put the process into the stopped state where we might
469 * want to examine its user state with ptrace. Therefore we need
470 * to save all the nonvolatile registers (r14 - r31) before calling
471 * the C code. Similarly, fork, vfork and clone need the full
472 * register state on the stack so that it can be copied to the child.
490 _GLOBAL(ppc32_swapcontext)
492 bl compat_sys_swapcontext
495 _GLOBAL(ppc64_swapcontext)
500 _GLOBAL(ppc_switch_endian)
505 _GLOBAL(ret_from_fork)
511 _GLOBAL(ret_from_kernel_thread)
516 #ifdef PPC64_ELF_ABI_v2
523 #ifdef CONFIG_PPC_BOOK3S_64
525 #define FLUSH_COUNT_CACHE \
527 patch_site 1b, patch__call_flush_count_cache
530 #define BCCTR_FLUSH .long 0x4c400420
539 .global flush_count_cache
541 /* Save LR into r9 */
559 patch_site 2b patch__flush_count_cache_return
571 #define FLUSH_COUNT_CACHE
572 #endif /* CONFIG_PPC_BOOK3S_64 */
575 * This routine switches between two different tasks. The process
576 * state of one is saved on its kernel stack. Then the state
577 * of the other is restored from its kernel stack. The memory
578 * management hardware is updated to the second process's state.
579 * Finally, we can return to the second process, via ret_from_except.
580 * On entry, r3 points to the THREAD for the current task, r4
581 * points to the THREAD for the new task.
583 * Note: there are two ways to get to the "going out" portion
584 * of this code; either by coming in via the entry (_switch)
585 * or via "fork" which must set up an environment equivalent
586 * to the "_switch" path. If you change this you'll have to change
587 * the fork code also.
589 * The code which creates the new task context is in 'copy_thread'
590 * in arch/powerpc/kernel/process.c
596 stdu r1,-SWITCH_FRAME_SIZE(r1)
597 /* r3-r13 are caller saved -- Cort */
600 std r0,_NIP(r1) /* Return to switch caller */
603 std r1,KSP(r3) /* Set old stack pointer */
605 kuap_check_amr r9, r10
610 * On SMP kernels, care must be taken because a task may be
611 * scheduled off CPUx and on to CPUy. Memory ordering must be
614 * Cacheable stores on CPUx will be visible when the task is
615 * scheduled on CPUy by virtue of the core scheduler barriers
616 * (see "Notes on Program-Order guarantees on SMP systems." in
617 * kernel/sched/core.c).
619 * Uncacheable stores in the case of involuntary preemption must
620 * be taken care of. The smp_mb__before_spin_lock() in __schedule()
621 * is implemented as hwsync on powerpc, which orders MMIO too. So
622 * long as there is an hwsync in the context switch path, it will
623 * be executed on the source CPU after the task has performed
624 * all MMIO ops on that CPU, and on the destination CPU before the
625 * task performs any MMIO ops there.
629 * The kernel context switch path must contain a spin_lock,
630 * which contains larx/stcx, which will clear any reservation
631 * of the task being switched.
633 #ifdef CONFIG_PPC_BOOK3S
634 /* Cancel all explict user streams as they will have no use after context
635 * switch and will stop the HW from creating streams itself
637 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r6)
640 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
641 std r6,PACACURRENT(r13) /* Set new 'current' */
642 #if defined(CONFIG_STACKPROTECTOR)
643 ld r6, TASK_CANARY(r6)
644 std r6, PACA_CANARY(r13)
647 ld r8,KSP(r4) /* new stack pointer */
648 #ifdef CONFIG_PPC_BOOK3S_64
649 BEGIN_MMU_FTR_SECTION
651 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
653 clrrdi r6,r8,28 /* get its ESID */
654 clrrdi r9,r1,28 /* get current sp ESID */
656 clrrdi r6,r8,40 /* get its 1T ESID */
657 clrrdi r9,r1,40 /* get current sp 1T ESID */
658 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
659 clrldi. r0,r6,2 /* is new ESID c00000000? */
660 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
662 beq 2f /* if yes, don't slbie it */
664 /* Bolt in the new stack SLB entry */
665 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
666 oris r0,r6,(SLB_ESID_V)@h
667 ori r0,r0,(SLB_NUM_BOLTED-1)@l
669 li r9,MMU_SEGSIZE_1T /* insert B field */
670 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
671 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
672 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
674 /* Update the last bolted SLB. No write barriers are needed
675 * here, provided we only update the current CPU's SLB shadow
678 ld r9,PACA_SLBSHADOWPTR(r13)
680 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
681 li r12,SLBSHADOW_STACKVSID
682 STDX_BE r7,r12,r9 /* Save VSID */
683 li r12,SLBSHADOW_STACKESID
684 STDX_BE r0,r12,r9 /* Save ESID */
686 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
687 * we have 1TB segments, the only CPUs known to have the errata
688 * only support less than 1TB of system memory and we'll never
689 * actually hit this code path.
695 slbie r6 /* Workaround POWER5 < DD2.1 issue */
696 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
700 #endif /* CONFIG_PPC_BOOK3S_64 */
702 clrrdi r7, r8, THREAD_SHIFT /* base of new stack */
703 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
704 because we don't need to leave the 288-byte ABI gap at the
705 top of the kernel stack. */
706 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
709 * PMU interrupts in radix may come in here. They will use r1, not
710 * PACAKSAVE, so this stack switch will not cause a problem. They
711 * will store to the process stack, which may then be migrated to
712 * another CPU. However the rq lock release on this CPU paired with
713 * the rq lock acquire on the new CPU before the stack becomes
714 * active on the new CPU, will order those stores.
716 mr r1,r8 /* start using new stack pointer */
717 std r7,PACAKSAVE(r13)
722 /* r3-r13 are destroyed -- Cort */
726 /* convert old thread to its task_struct for return value */
728 ld r7,_NIP(r1) /* Return to _switch caller in new task */
730 addi r1,r1,SWITCH_FRAME_SIZE
734 _GLOBAL(ret_from_except)
737 bne ret_from_except_lite
740 _GLOBAL(ret_from_except_lite)
742 * Disable interrupts so that current_thread_info()->flags
743 * can't change between when we test it and when we return
744 * from the interrupt.
746 #ifdef CONFIG_PPC_BOOK3E
750 mtmsrd r10,1 /* Update machine state */
751 #endif /* CONFIG_PPC_BOOK3E */
753 ld r9, PACA_THREAD_INFO(r13)
755 #ifdef CONFIG_PPC_BOOK3E
756 ld r10,PACACURRENT(r13)
757 #endif /* CONFIG_PPC_BOOK3E */
761 #ifdef CONFIG_PPC_BOOK3E
762 lwz r3,(THREAD+THREAD_DBCR0)(r10)
763 #endif /* CONFIG_PPC_BOOK3E */
765 /* Check current_thread_info()->flags */
766 andi. r0,r4,_TIF_USER_WORK_MASK
768 #ifdef CONFIG_PPC_BOOK3E
770 * Check to see if the dbcr0 register is set up to debug.
771 * Use the internal debug mode bit to do this.
773 andis. r0,r3,DBCR0_IDM@h
776 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
783 addi r3,r1,STACK_FRAME_OVERHEAD
787 1: andi. r0,r4,_TIF_NEED_RESCHED
789 bl restore_interrupts
791 b ret_from_except_lite
793 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
794 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
795 bne 3f /* only restore TM if nothing else to do */
796 addi r3,r1,STACK_FRAME_OVERHEAD
803 * Use a non volatile GPR to save and restore our thread_info flags
804 * across the call to restore_interrupts.
807 bl restore_interrupts
809 addi r3,r1,STACK_FRAME_OVERHEAD
814 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
815 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
818 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
821 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
822 mr r4,r1 /* src: current exception frame */
823 mr r1,r3 /* Reroute the trampoline frame to r1 */
825 /* Copy from the original to the trampoline. */
826 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
827 li r6,0 /* start offset: 0 */
834 /* Do real store operation to complete stdu */
838 /* Clear _TIF_EMULATE_STACK_STORE flag */
839 lis r11,_TIF_EMULATE_STACK_STORE@h
847 #ifdef CONFIG_PREEMPT
848 /* Check if we need to preempt */
849 andi. r0,r4,_TIF_NEED_RESCHED
851 /* Check that preempt_count() == 0 and interrupts are enabled */
852 lwz r8,TI_PREEMPT(r9)
856 andi. r0,r0,IRQS_DISABLED
860 * Here we are preempting the current task. We want to make
861 * sure we are soft-disabled first and reconcile irq state.
863 RECONCILE_IRQ_STATE(r3,r4)
864 bl preempt_schedule_irq
867 * arch_local_irq_restore() from preempt_schedule_irq above may
868 * enable hard interrupt but we really should disable interrupts
869 * when we return from the interrupt, and so that we don't get
870 * interrupted after loading SRR0/1.
872 #ifdef CONFIG_PPC_BOOK3E
876 mtmsrd r10,1 /* Update machine state */
877 #endif /* CONFIG_PPC_BOOK3E */
878 #endif /* CONFIG_PREEMPT */
880 .globl fast_exc_return_irq
884 * This is the main kernel exit path. First we check if we
885 * are about to re-enable interrupts
888 lbz r6,PACAIRQSOFTMASK(r13)
889 andi. r5,r5,IRQS_DISABLED
890 bne .Lrestore_irq_off
892 /* We are enabling, were we already enabled ? Yes, just return */
893 andi. r6,r6,IRQS_DISABLED
897 * We are about to soft-enable interrupts (we are hard disabled
898 * at this point). We check if there's anything that needs to
901 lbz r0,PACAIRQHAPPENED(r13)
903 bne- .Lrestore_check_irq_replay
906 * Get here when nothing happened while soft-disabled, just
907 * soft-enable and move-on. We will hard-enable as a side
913 stb r0,PACAIRQSOFTMASK(r13);
916 * Final return path. BookE is handled in a different file
919 #ifdef CONFIG_PPC_BOOK3E
920 b exception_return_book3e
923 * Clear the reservation. If we know the CPU tracks the address of
924 * the reservation then we can potentially save some cycles and use
925 * a larx. On POWER6 and POWER7 this is significantly faster.
928 stdcx. r0,0,r1 /* to clear the reservation */
931 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
934 * Some code path such as load_up_fpu or altivec return directly
935 * here. They run entirely hard disabled and do not alter the
936 * interrupt state. They also don't use lwarx/stwcx. and thus
937 * are known not to leave dangling reservations.
939 .globl fast_exception_return
940 fast_exception_return:
949 kuap_check_amr r5, r6
954 beq- .Lunrecov_restore
957 * Clear RI before restoring r13. If we are returning to
958 * userspace and we take an exception after restoring r13,
959 * we end up corrupting the userspace r13 value.
964 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
966 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
969 * r13 is our per cpu area, only restore it if we are returning to
970 * userspace the value stored in the stack frame may belong to
979 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
980 ACCOUNT_CPU_USER_EXIT(r13, r2, r4)
984 * We don't need to restore AMR on the way back to userspace for KUAP.
985 * The value of AMR only matters while we're in the kernel.
1000 b . /* prevent speculative execution */
1002 1: mtspr SPRN_SRR1,r3
1010 * Leaving a stale exception_marker on the stack can confuse
1011 * the reliable stack unwinder later on. Clear it.
1014 std r2,STACK_FRAME_OVERHEAD-16(r1)
1025 b . /* prevent speculative execution */
1027 #endif /* CONFIG_PPC_BOOK3E */
1030 * We are returning to a context with interrupts soft disabled.
1032 * However, we may also about to hard enable, so we need to
1033 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
1034 * or that bit can get out of sync and bad things will happen
1038 lbz r7,PACAIRQHAPPENED(r13)
1041 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
1042 stb r7,PACAIRQHAPPENED(r13)
1044 #if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
1045 /* The interrupt should not have soft enabled. */
1046 lbz r7,PACAIRQSOFTMASK(r13)
1047 1: tdeqi r7,IRQS_ENABLED
1048 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1053 * Something did happen, check if a re-emit is needed
1054 * (this also clears paca->irq_happened)
1056 .Lrestore_check_irq_replay:
1057 /* XXX: We could implement a fast path here where we check
1058 * for irq_happened being just 0x01, in which case we can
1059 * clear it and return. That means that we would potentially
1060 * miss a decrementer having wrapped all the way around.
1062 * Still, this might be useful for things like hash_page
1064 bl __check_irq_replay
1066 beq .Lrestore_no_replay
1069 * We need to re-emit an interrupt. We do so by re-using our
1070 * existing exception frame. We first change the trap value,
1071 * but we need to ensure we preserve the low nibble of it
1079 * PACA_IRQ_HARD_DIS won't always be set here, so set it now
1080 * to reconcile the IRQ state. Tracing is already accounted for.
1082 lbz r4,PACAIRQHAPPENED(r13)
1083 ori r4,r4,PACA_IRQ_HARD_DIS
1084 stb r4,PACAIRQHAPPENED(r13)
1087 * Then find the right handler and call it. Interrupts are
1088 * still soft-disabled and we keep them that way.
1092 addi r3,r1,STACK_FRAME_OVERHEAD;
1095 1: cmpwi cr0,r3,0xf00
1097 addi r3,r1,STACK_FRAME_OVERHEAD;
1098 bl performance_monitor_exception
1100 1: cmpwi cr0,r3,0xe60
1102 addi r3,r1,STACK_FRAME_OVERHEAD;
1103 bl handle_hmi_exception
1105 1: cmpwi cr0,r3,0x900
1107 addi r3,r1,STACK_FRAME_OVERHEAD;
1110 #ifdef CONFIG_PPC_DOORBELL
1112 #ifdef CONFIG_PPC_BOOK3E
1116 #endif /* CONFIG_PPC_BOOK3E */
1118 addi r3,r1,STACK_FRAME_OVERHEAD;
1119 bl doorbell_exception
1120 #endif /* CONFIG_PPC_DOORBELL */
1121 1: b ret_from_except /* What else to do here ? */
1124 addi r3,r1,STACK_FRAME_OVERHEAD
1125 bl unrecoverable_exception
1128 _ASM_NOKPROBE_SYMBOL(ret_from_except);
1129 _ASM_NOKPROBE_SYMBOL(ret_from_except_lite);
1130 _ASM_NOKPROBE_SYMBOL(resume_kernel);
1131 _ASM_NOKPROBE_SYMBOL(fast_exc_return_irq);
1132 _ASM_NOKPROBE_SYMBOL(restore);
1133 _ASM_NOKPROBE_SYMBOL(fast_exception_return);
1136 #ifdef CONFIG_PPC_RTAS
1138 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1139 * called with the MMU off.
1141 * In addition, we need to be in 32b mode, at least for now.
1143 * Note: r3 is an input parameter to rtas, so don't trash it...
1148 stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space. */
1150 /* Because RTAS is running in 32b mode, it clobbers the high order half
1151 * of all registers that it saves. We therefore save those registers
1152 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
1154 SAVE_GPR(2, r1) /* Save the TOC */
1155 SAVE_GPR(13, r1) /* Save paca */
1156 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
1157 SAVE_10GPRS(22, r1) /* ditto */
1170 /* Temporary workaround to clear CR until RTAS can be modified to
1177 /* There is no way it is acceptable to get here with interrupts enabled,
1178 * check it with the asm equivalent of WARN_ON
1180 lbz r0,PACAIRQSOFTMASK(r13)
1181 1: tdeqi r0,IRQS_ENABLED
1182 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1185 /* Hard-disable interrupts */
1191 /* Unfortunately, the stack pointer and the MSR are also clobbered,
1192 * so they are saved in the PACA which allows us to restore
1193 * our original state after RTAS returns.
1196 std r6,PACASAVEDMSR(r13)
1198 /* Setup our real return addr */
1199 LOAD_REG_ADDR(r4,rtas_return_loc)
1200 clrldi r4,r4,2 /* convert to realmode address */
1204 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1208 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1209 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1213 sync /* disable interrupts so SRR0/1 */
1214 mtmsrd r0 /* don't get trashed */
1216 LOAD_REG_ADDR(r4, rtas)
1217 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1218 ld r4,RTASBASE(r4) /* get the rtas->base value */
1223 b . /* prevent speculative execution */
1229 * Clear RI and set SF before anything.
1234 sldi r0,r0,(MSR_SF_LG - MSR_RI_LG)
1239 /* relocation is off at this point */
1241 clrldi r4,r4,2 /* convert to realmode address */
1245 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
1247 ld r1,PACAR1(r4) /* Restore our SP */
1248 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1253 b . /* prevent speculative execution */
1254 _ASM_NOKPROBE_SYMBOL(__enter_rtas)
1255 _ASM_NOKPROBE_SYMBOL(rtas_return_loc)
1258 1: .8byte rtas_restore_regs
1261 /* relocation is on at this point */
1262 REST_GPR(2, r1) /* Restore the TOC */
1263 REST_GPR(13, r1) /* Restore paca */
1264 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1265 REST_10GPRS(22, r1) /* ditto */
1280 addi r1,r1,SWITCH_FRAME_SIZE /* Unstack our frame */
1281 ld r0,16(r1) /* get return address */
1284 blr /* return to caller */
1286 #endif /* CONFIG_PPC_RTAS */
1291 stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space */
1293 /* Because PROM is running in 32b mode, it clobbers the high order half
1294 * of all registers that it saves. We therefore save those registers
1295 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1306 /* Put PROM address in SRR0 */
1309 /* Setup our trampoline return addr in LR */
1312 addi r4,r4,(1f - 0b)
1315 /* Prepare a 32-bit mode big endian MSR
1317 #ifdef CONFIG_PPC_BOOK3E
1318 rlwinm r11,r11,0,1,31
1321 #else /* CONFIG_PPC_BOOK3E */
1322 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1326 #endif /* CONFIG_PPC_BOOK3E */
1328 1: /* Return from OF */
1331 /* Just make sure that r1 top 32 bits didn't get
1336 /* Restore the MSR (back to 64 bits) */
1341 /* Restore other registers */
1349 addi r1,r1,SWITCH_FRAME_SIZE