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powerpc/64s: Consolidate External 0x500 interrupt
[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / kernel / exceptions-64s.S
1 /*
2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
6 *
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
9 *
10 * Most of this originates from head_64.S and thus has the same
11 * copyright history.
12 *
13 */
14
15 #include <asm/hw_irq.h>
16 #include <asm/exception-64s.h>
17 #include <asm/ptrace.h>
18 #include <asm/cpuidle.h>
19 #include <asm/head-64.h>
20
21 /*
22 * There are a few constraints to be concerned with.
23 * - Real mode exceptions code/data must be located at their physical location.
24 * - Virtual mode exceptions must be mapped at their 0xc000... location.
25 * - Fixed location code must not call directly beyond the __end_interrupts
26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
27 * must be used.
28 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
29 * virtual 0xc00...
30 * - Conditional branch targets must be within +/-32K of caller.
31 *
32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
33 * therefore don't have to run in physically located code or rfid to
34 * virtual mode kernel code. However on relocatable kernels they do have
35 * to branch to KERNELBASE offset because the rest of the kernel (outside
36 * the exception vectors) may be located elsewhere.
37 *
38 * Virtual exceptions correspond with physical, except their entry points
39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
40 * offset applied. Virtual exceptions are enabled with the Alternate
41 * Interrupt Location (AIL) bit set in the LPCR. However this does not
42 * guarantee they will be delivered virtually. Some conditions (see the ISA)
43 * cause exceptions to be delivered in real mode.
44 *
45 * It's impossible to receive interrupts below 0x300 via AIL.
46 *
47 * KVM: None of the virtual exceptions are from the guest. Anything that
48 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
49 *
50 *
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
54 * 0x1900 - 0x3fff : Real mode trampolines
55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
56 * 0x5900 - 0x6fff : Relon mode trampolines
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - .... : Common interrupt handlers, remaining early
59 * setup code, rest of kernel.
60 */
61 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
62 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
63 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
64 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
65 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
66 /*
67 * Data area reserved for FWNMI option.
68 * This address (0x7000) is fixed by the RPA.
69 * pseries and powernv need to keep the whole page from
70 * 0x7000 to 0x8000 free for use by the firmware
71 */
72 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
73 OPEN_TEXT_SECTION(0x8000)
74 #else
75 OPEN_TEXT_SECTION(0x7000)
76 #endif
77
78 USE_FIXED_SECTION(real_vectors)
79
80 #define LOAD_SYSCALL_HANDLER(reg) \
81 ld reg,PACAKBASE(r13); \
82 ori reg,reg,(ABS_ADDR(system_call_common))@l;
83
84 /* Syscall routine is used twice, in reloc-off and reloc-on paths */
85 #define SYSCALL_PSERIES_1 \
86 BEGIN_FTR_SECTION \
87 cmpdi r0,0x1ebe ; \
88 beq- 1f ; \
89 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
90 mr r9,r13 ; \
91 GET_PACA(r13) ; \
92 mfspr r11,SPRN_SRR0 ; \
93 0:
94
95 #define SYSCALL_PSERIES_2_RFID \
96 mfspr r12,SPRN_SRR1 ; \
97 LOAD_SYSCALL_HANDLER(r10) ; \
98 mtspr SPRN_SRR0,r10 ; \
99 ld r10,PACAKMSR(r13) ; \
100 mtspr SPRN_SRR1,r10 ; \
101 rfid ; \
102 b . ; /* prevent speculative execution */
103
104 #define SYSCALL_PSERIES_3 \
105 /* Fast LE/BE switch system call */ \
106 1: mfspr r12,SPRN_SRR1 ; \
107 xori r12,r12,MSR_LE ; \
108 mtspr SPRN_SRR1,r12 ; \
109 rfid ; /* return to userspace */ \
110 b . ; /* prevent speculative execution */
111
112 #if defined(CONFIG_RELOCATABLE)
113 /*
114 * We can't branch directly so we do it via the CTR which
115 * is volatile across system calls.
116 */
117 #define SYSCALL_PSERIES_2_DIRECT \
118 LOAD_SYSCALL_HANDLER(r12) ; \
119 mtctr r12 ; \
120 mfspr r12,SPRN_SRR1 ; \
121 li r10,MSR_RI ; \
122 mtmsrd r10,1 ; \
123 bctr ;
124 #else
125 /* We can branch directly */
126 #define SYSCALL_PSERIES_2_DIRECT \
127 mfspr r12,SPRN_SRR1 ; \
128 li r10,MSR_RI ; \
129 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
130 b system_call_common ;
131 #endif
132
133 /*
134 * This is the start of the interrupt handlers for pSeries
135 * This code runs with relocation off.
136 * Code from here to __end_interrupts gets copied down to real
137 * address 0x100 when we are running a relocatable kernel.
138 * Therefore any relative branches in this section must only
139 * branch to labels in this section.
140 */
141 .globl __start_interrupts
142 __start_interrupts:
143
144 EXC_REAL_BEGIN(system_reset, 0x100, 0x200)
145 SET_SCRATCH0(r13)
146 #ifdef CONFIG_PPC_P7_NAP
147 BEGIN_FTR_SECTION
148 /* Running native on arch 2.06 or later, check if we are
149 * waking up from nap/sleep/winkle.
150 */
151 mfspr r13,SPRN_SRR1
152 rlwinm. r13,r13,47-31,30,31
153 beq 9f
154
155 cmpwi cr3,r13,2
156 GET_PACA(r13)
157 bl pnv_restore_hyp_resource
158
159 li r0,PNV_THREAD_RUNNING
160 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
161
162 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
163 li r0,KVM_HWTHREAD_IN_KERNEL
164 stb r0,HSTATE_HWTHREAD_STATE(r13)
165 /* Order setting hwthread_state vs. testing hwthread_req */
166 sync
167 lbz r0,HSTATE_HWTHREAD_REQ(r13)
168 cmpwi r0,0
169 beq 1f
170 b kvm_start_guest
171 1:
172 #endif
173
174 /* Return SRR1 from power7_nap() */
175 mfspr r3,SPRN_SRR1
176 blt cr3,2f
177 b pnv_wakeup_loss
178 2: b pnv_wakeup_noloss
179
180 9:
181 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
182 #endif /* CONFIG_PPC_P7_NAP */
183 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
184 NOTEST, 0x100)
185 EXC_REAL_END(system_reset, 0x100, 0x200)
186 EXC_VIRT_NONE(0x4100, 0x4200)
187 EXC_COMMON(system_reset_common, 0x100, system_reset_exception)
188
189 #ifdef CONFIG_PPC_PSERIES
190 /*
191 * Vectors for the FWNMI option. Share common code.
192 */
193 TRAMP_REAL_BEGIN(system_reset_fwnmi)
194 SET_SCRATCH0(r13) /* save r13 */
195 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
196 NOTEST, 0x100)
197 #endif /* CONFIG_PPC_PSERIES */
198
199
200 EXC_REAL_BEGIN(machine_check, 0x200, 0x300)
201 /* This is moved out of line as it can be patched by FW, but
202 * some code path might still want to branch into the original
203 * vector
204 */
205 SET_SCRATCH0(r13) /* save r13 */
206 /*
207 * Running native on arch 2.06 or later, we may wakeup from winkle
208 * inside machine check. If yes, then last bit of HSPGR0 would be set
209 * to 1. Hence clear it unconditionally.
210 */
211 GET_PACA(r13)
212 clrrdi r13,r13,1
213 SET_PACA(r13)
214 EXCEPTION_PROLOG_0(PACA_EXMC)
215 BEGIN_FTR_SECTION
216 b machine_check_powernv_early
217 FTR_SECTION_ELSE
218 b machine_check_pSeries_0
219 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
220 EXC_REAL_END(machine_check, 0x200, 0x300)
221 EXC_VIRT_NONE(0x4200, 0x4300)
222 TRAMP_REAL_BEGIN(machine_check_powernv_early)
223 BEGIN_FTR_SECTION
224 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
225 /*
226 * Register contents:
227 * R13 = PACA
228 * R9 = CR
229 * Original R9 to R13 is saved on PACA_EXMC
230 *
231 * Switch to mc_emergency stack and handle re-entrancy (we limit
232 * the nested MCE upto level 4 to avoid stack overflow).
233 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
234 *
235 * We use paca->in_mce to check whether this is the first entry or
236 * nested machine check. We increment paca->in_mce to track nested
237 * machine checks.
238 *
239 * If this is the first entry then set stack pointer to
240 * paca->mc_emergency_sp, otherwise r1 is already pointing to
241 * stack frame on mc_emergency stack.
242 *
243 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
244 * checkstop if we get another machine check exception before we do
245 * rfid with MSR_ME=1.
246 */
247 mr r11,r1 /* Save r1 */
248 lhz r10,PACA_IN_MCE(r13)
249 cmpwi r10,0 /* Are we in nested machine check */
250 bne 0f /* Yes, we are. */
251 /* First machine check entry */
252 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
253 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
254 addi r10,r10,1 /* increment paca->in_mce */
255 sth r10,PACA_IN_MCE(r13)
256 /* Limit nested MCE to level 4 to avoid stack overflow */
257 cmpwi r10,4
258 bgt 2f /* Check if we hit limit of 4 */
259 std r11,GPR1(r1) /* Save r1 on the stack. */
260 std r11,0(r1) /* make stack chain pointer */
261 mfspr r11,SPRN_SRR0 /* Save SRR0 */
262 std r11,_NIP(r1)
263 mfspr r11,SPRN_SRR1 /* Save SRR1 */
264 std r11,_MSR(r1)
265 mfspr r11,SPRN_DAR /* Save DAR */
266 std r11,_DAR(r1)
267 mfspr r11,SPRN_DSISR /* Save DSISR */
268 std r11,_DSISR(r1)
269 std r9,_CCR(r1) /* Save CR in stackframe */
270 /* Save r9 through r13 from EXMC save area to stack frame. */
271 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
272 mfmsr r11 /* get MSR value */
273 ori r11,r11,MSR_ME /* turn on ME bit */
274 ori r11,r11,MSR_RI /* turn on RI bit */
275 LOAD_HANDLER(r12, machine_check_handle_early)
276 1: mtspr SPRN_SRR0,r12
277 mtspr SPRN_SRR1,r11
278 rfid
279 b . /* prevent speculative execution */
280 2:
281 /* Stack overflow. Stay on emergency stack and panic.
282 * Keep the ME bit off while panic-ing, so that if we hit
283 * another machine check we checkstop.
284 */
285 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
286 ld r11,PACAKMSR(r13)
287 LOAD_HANDLER(r12, unrecover_mce)
288 li r10,MSR_ME
289 andc r11,r11,r10 /* Turn off MSR_ME */
290 b 1b
291 b . /* prevent speculative execution */
292 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
293
294 TRAMP_REAL_BEGIN(machine_check_pSeries)
295 .globl machine_check_fwnmi
296 machine_check_fwnmi:
297 SET_SCRATCH0(r13) /* save r13 */
298 EXCEPTION_PROLOG_0(PACA_EXMC)
299 machine_check_pSeries_0:
300 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
301 /*
302 * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the
303 * difference that MSR_RI is not enabled, because PACA_EXMC is being
304 * used, so nested machine check corrupts it. machine_check_common
305 * enables MSR_RI.
306 */
307 ld r10,PACAKMSR(r13)
308 xori r10,r10,MSR_RI
309 mfspr r11,SPRN_SRR0
310 LOAD_HANDLER(r12, machine_check_common)
311 mtspr SPRN_SRR0,r12
312 mfspr r12,SPRN_SRR1
313 mtspr SPRN_SRR1,r10
314 rfid
315 b . /* prevent speculative execution */
316
317 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
318
319 EXC_COMMON_BEGIN(machine_check_common)
320 /*
321 * Machine check is different because we use a different
322 * save area: PACA_EXMC instead of PACA_EXGEN.
323 */
324 mfspr r10,SPRN_DAR
325 std r10,PACA_EXMC+EX_DAR(r13)
326 mfspr r10,SPRN_DSISR
327 stw r10,PACA_EXMC+EX_DSISR(r13)
328 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
329 FINISH_NAP
330 RECONCILE_IRQ_STATE(r10, r11)
331 ld r3,PACA_EXMC+EX_DAR(r13)
332 lwz r4,PACA_EXMC+EX_DSISR(r13)
333 /* Enable MSR_RI when finished with PACA_EXMC */
334 li r10,MSR_RI
335 mtmsrd r10,1
336 std r3,_DAR(r1)
337 std r4,_DSISR(r1)
338 bl save_nvgprs
339 addi r3,r1,STACK_FRAME_OVERHEAD
340 bl machine_check_exception
341 b ret_from_except
342
343 #define MACHINE_CHECK_HANDLER_WINDUP \
344 /* Clear MSR_RI before setting SRR0 and SRR1. */\
345 li r0,MSR_RI; \
346 mfmsr r9; /* get MSR value */ \
347 andc r9,r9,r0; \
348 mtmsrd r9,1; /* Clear MSR_RI */ \
349 /* Move original SRR0 and SRR1 into the respective regs */ \
350 ld r9,_MSR(r1); \
351 mtspr SPRN_SRR1,r9; \
352 ld r3,_NIP(r1); \
353 mtspr SPRN_SRR0,r3; \
354 ld r9,_CTR(r1); \
355 mtctr r9; \
356 ld r9,_XER(r1); \
357 mtxer r9; \
358 ld r9,_LINK(r1); \
359 mtlr r9; \
360 REST_GPR(0, r1); \
361 REST_8GPRS(2, r1); \
362 REST_GPR(10, r1); \
363 ld r11,_CCR(r1); \
364 mtcr r11; \
365 /* Decrement paca->in_mce. */ \
366 lhz r12,PACA_IN_MCE(r13); \
367 subi r12,r12,1; \
368 sth r12,PACA_IN_MCE(r13); \
369 REST_GPR(11, r1); \
370 REST_2GPRS(12, r1); \
371 /* restore original r1. */ \
372 ld r1,GPR1(r1)
373
374 /*
375 * Handle machine check early in real mode. We come here with
376 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
377 */
378 EXC_COMMON_BEGIN(machine_check_handle_early)
379 std r0,GPR0(r1) /* Save r0 */
380 EXCEPTION_PROLOG_COMMON_3(0x200)
381 bl save_nvgprs
382 addi r3,r1,STACK_FRAME_OVERHEAD
383 bl machine_check_early
384 std r3,RESULT(r1) /* Save result */
385 ld r12,_MSR(r1)
386 #ifdef CONFIG_PPC_P7_NAP
387 /*
388 * Check if thread was in power saving mode. We come here when any
389 * of the following is true:
390 * a. thread wasn't in power saving mode
391 * b. thread was in power saving mode with no state loss,
392 * supervisor state loss or hypervisor state loss.
393 *
394 * Go back to nap/sleep/winkle mode again if (b) is true.
395 */
396 rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */
397 beq 4f /* No, it wasn;t */
398 /* Thread was in power saving mode. Go back to nap again. */
399 cmpwi r11,2
400 blt 3f
401 /* Supervisor/Hypervisor state loss */
402 li r0,1
403 stb r0,PACA_NAPSTATELOST(r13)
404 3: bl machine_check_queue_event
405 MACHINE_CHECK_HANDLER_WINDUP
406 GET_PACA(r13)
407 ld r1,PACAR1(r13)
408 /*
409 * Check what idle state this CPU was in and go back to same mode
410 * again.
411 */
412 lbz r3,PACA_THREAD_IDLE_STATE(r13)
413 cmpwi r3,PNV_THREAD_NAP
414 bgt 10f
415 IDLE_STATE_ENTER_SEQ(PPC_NAP)
416 /* No return */
417 10:
418 cmpwi r3,PNV_THREAD_SLEEP
419 bgt 2f
420 IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
421 /* No return */
422
423 2:
424 /*
425 * Go back to winkle. Please note that this thread was woken up in
426 * machine check from winkle and have not restored the per-subcore
427 * state. Hence before going back to winkle, set last bit of HSPGR0
428 * to 1. This will make sure that if this thread gets woken up
429 * again at reset vector 0x100 then it will get chance to restore
430 * the subcore state.
431 */
432 ori r13,r13,1
433 SET_PACA(r13)
434 IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
435 /* No return */
436 4:
437 #endif
438 /*
439 * Check if we are coming from hypervisor userspace. If yes then we
440 * continue in host kernel in V mode to deliver the MC event.
441 */
442 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
443 beq 5f
444 andi. r11,r12,MSR_PR /* See if coming from user. */
445 bne 9f /* continue in V mode if we are. */
446
447 5:
448 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
449 /*
450 * We are coming from kernel context. Check if we are coming from
451 * guest. if yes, then we can continue. We will fall through
452 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
453 */
454 lbz r11,HSTATE_IN_GUEST(r13)
455 cmpwi r11,0 /* Check if coming from guest */
456 bne 9f /* continue if we are. */
457 #endif
458 /*
459 * At this point we are not sure about what context we come from.
460 * Queue up the MCE event and return from the interrupt.
461 * But before that, check if this is an un-recoverable exception.
462 * If yes, then stay on emergency stack and panic.
463 */
464 andi. r11,r12,MSR_RI
465 bne 2f
466 1: mfspr r11,SPRN_SRR0
467 LOAD_HANDLER(r10,unrecover_mce)
468 mtspr SPRN_SRR0,r10
469 ld r10,PACAKMSR(r13)
470 /*
471 * We are going down. But there are chances that we might get hit by
472 * another MCE during panic path and we may run into unstable state
473 * with no way out. Hence, turn ME bit off while going down, so that
474 * when another MCE is hit during panic path, system will checkstop
475 * and hypervisor will get restarted cleanly by SP.
476 */
477 li r3,MSR_ME
478 andc r10,r10,r3 /* Turn off MSR_ME */
479 mtspr SPRN_SRR1,r10
480 rfid
481 b .
482 2:
483 /*
484 * Check if we have successfully handled/recovered from error, if not
485 * then stay on emergency stack and panic.
486 */
487 ld r3,RESULT(r1) /* Load result */
488 cmpdi r3,0 /* see if we handled MCE successfully */
489
490 beq 1b /* if !handled then panic */
491 /*
492 * Return from MC interrupt.
493 * Queue up the MCE event so that we can log it later, while
494 * returning from kernel or opal call.
495 */
496 bl machine_check_queue_event
497 MACHINE_CHECK_HANDLER_WINDUP
498 rfid
499 9:
500 /* Deliver the machine check to host kernel in V mode. */
501 MACHINE_CHECK_HANDLER_WINDUP
502 b machine_check_pSeries
503
504 EXC_COMMON_BEGIN(unrecover_mce)
505 /* Invoke machine_check_exception to print MCE event and panic. */
506 addi r3,r1,STACK_FRAME_OVERHEAD
507 bl machine_check_exception
508 /*
509 * We will not reach here. Even if we did, there is no way out. Call
510 * unrecoverable_exception and die.
511 */
512 1: addi r3,r1,STACK_FRAME_OVERHEAD
513 bl unrecoverable_exception
514 b 1b
515
516
517 EXC_REAL(data_access, 0x300, 0x380)
518 EXC_VIRT(data_access, 0x4300, 0x4380, 0x300)
519 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
520
521 EXC_COMMON_BEGIN(data_access_common)
522 /*
523 * Here r13 points to the paca, r9 contains the saved CR,
524 * SRR0 and SRR1 are saved in r11 and r12,
525 * r9 - r13 are saved in paca->exgen.
526 */
527 mfspr r10,SPRN_DAR
528 std r10,PACA_EXGEN+EX_DAR(r13)
529 mfspr r10,SPRN_DSISR
530 stw r10,PACA_EXGEN+EX_DSISR(r13)
531 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
532 RECONCILE_IRQ_STATE(r10, r11)
533 ld r12,_MSR(r1)
534 ld r3,PACA_EXGEN+EX_DAR(r13)
535 lwz r4,PACA_EXGEN+EX_DSISR(r13)
536 li r5,0x300
537 std r3,_DAR(r1)
538 std r4,_DSISR(r1)
539 BEGIN_MMU_FTR_SECTION
540 b do_hash_page /* Try to handle as hpte fault */
541 MMU_FTR_SECTION_ELSE
542 b handle_page_fault
543 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
544
545
546 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400)
547 SET_SCRATCH0(r13)
548 EXCEPTION_PROLOG_0(PACA_EXSLB)
549 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
550 std r3,PACA_EXSLB+EX_R3(r13)
551 mfspr r3,SPRN_DAR
552 mfspr r12,SPRN_SRR1
553 crset 4*cr6+eq
554 #ifndef CONFIG_RELOCATABLE
555 b slb_miss_realmode
556 #else
557 /*
558 * We can't just use a direct branch to slb_miss_realmode
559 * because the distance from here to there depends on where
560 * the kernel ends up being put.
561 */
562 mfctr r11
563 LOAD_HANDLER(r10, slb_miss_realmode)
564 mtctr r10
565 bctr
566 #endif
567 EXC_REAL_END(data_access_slb, 0x380, 0x400)
568
569 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400)
570 SET_SCRATCH0(r13)
571 EXCEPTION_PROLOG_0(PACA_EXSLB)
572 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
573 std r3,PACA_EXSLB+EX_R3(r13)
574 mfspr r3,SPRN_DAR
575 mfspr r12,SPRN_SRR1
576 crset 4*cr6+eq
577 #ifndef CONFIG_RELOCATABLE
578 b slb_miss_realmode
579 #else
580 /*
581 * We can't just use a direct branch to slb_miss_realmode
582 * because the distance from here to there depends on where
583 * the kernel ends up being put.
584 */
585 mfctr r11
586 LOAD_HANDLER(r10, slb_miss_realmode)
587 mtctr r10
588 bctr
589 #endif
590 EXC_VIRT_END(data_access_slb, 0x4380, 0x4400)
591 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
592
593
594 EXC_REAL(instruction_access, 0x400, 0x480)
595 EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400)
596 TRAMP_KVM(PACA_EXGEN, 0x400)
597
598 EXC_COMMON_BEGIN(instruction_access_common)
599 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
600 RECONCILE_IRQ_STATE(r10, r11)
601 ld r12,_MSR(r1)
602 ld r3,_NIP(r1)
603 andis. r4,r12,0x5820
604 li r5,0x400
605 std r3,_DAR(r1)
606 std r4,_DSISR(r1)
607 BEGIN_MMU_FTR_SECTION
608 b do_hash_page /* Try to handle as hpte fault */
609 MMU_FTR_SECTION_ELSE
610 b handle_page_fault
611 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
612
613
614 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500)
615 SET_SCRATCH0(r13)
616 EXCEPTION_PROLOG_0(PACA_EXSLB)
617 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
618 std r3,PACA_EXSLB+EX_R3(r13)
619 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
620 mfspr r12,SPRN_SRR1
621 crclr 4*cr6+eq
622 #ifndef CONFIG_RELOCATABLE
623 b slb_miss_realmode
624 #else
625 mfctr r11
626 LOAD_HANDLER(r10, slb_miss_realmode)
627 mtctr r10
628 bctr
629 #endif
630 EXC_REAL_END(instruction_access_slb, 0x480, 0x500)
631
632 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500)
633 SET_SCRATCH0(r13)
634 EXCEPTION_PROLOG_0(PACA_EXSLB)
635 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
636 std r3,PACA_EXSLB+EX_R3(r13)
637 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
638 mfspr r12,SPRN_SRR1
639 crclr 4*cr6+eq
640 #ifndef CONFIG_RELOCATABLE
641 b slb_miss_realmode
642 #else
643 mfctr r11
644 LOAD_HANDLER(r10, slb_miss_realmode)
645 mtctr r10
646 bctr
647 #endif
648 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500)
649 TRAMP_KVM(PACA_EXSLB, 0x480)
650
651
652 /* This handler is used by both 0x380 and 0x480 slb miss interrupts */
653 EXC_COMMON_BEGIN(slb_miss_realmode)
654 /*
655 * r13 points to the PACA, r9 contains the saved CR,
656 * r12 contain the saved SRR1, SRR0 is still ready for return
657 * r3 has the faulting address
658 * r9 - r13 are saved in paca->exslb.
659 * r3 is saved in paca->slb_r3
660 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
661 * We assume we aren't going to take any exceptions during this
662 * procedure.
663 */
664 mflr r10
665 #ifdef CONFIG_RELOCATABLE
666 mtctr r11
667 #endif
668
669 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
670 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
671 std r3,PACA_EXSLB+EX_DAR(r13)
672
673 crset 4*cr0+eq
674 #ifdef CONFIG_PPC_STD_MMU_64
675 BEGIN_MMU_FTR_SECTION
676 bl slb_allocate_realmode
677 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
678 #endif
679
680 ld r10,PACA_EXSLB+EX_LR(r13)
681 ld r3,PACA_EXSLB+EX_R3(r13)
682 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
683 mtlr r10
684
685 beq 8f /* if bad address, make full stack frame */
686
687 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
688 beq- 2f
689
690 /* All done -- return from exception. */
691
692 .machine push
693 .machine "power4"
694 mtcrf 0x80,r9
695 mtcrf 0x02,r9 /* I/D indication is in cr6 */
696 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
697 .machine pop
698
699 RESTORE_PPR_PACA(PACA_EXSLB, r9)
700 ld r9,PACA_EXSLB+EX_R9(r13)
701 ld r10,PACA_EXSLB+EX_R10(r13)
702 ld r11,PACA_EXSLB+EX_R11(r13)
703 ld r12,PACA_EXSLB+EX_R12(r13)
704 ld r13,PACA_EXSLB+EX_R13(r13)
705 rfid
706 b . /* prevent speculative execution */
707
708 2: mfspr r11,SPRN_SRR0
709 LOAD_HANDLER(r10,unrecov_slb)
710 mtspr SPRN_SRR0,r10
711 ld r10,PACAKMSR(r13)
712 mtspr SPRN_SRR1,r10
713 rfid
714 b .
715
716 8: mfspr r11,SPRN_SRR0
717 LOAD_HANDLER(r10,bad_addr_slb)
718 mtspr SPRN_SRR0,r10
719 ld r10,PACAKMSR(r13)
720 mtspr SPRN_SRR1,r10
721 rfid
722 b .
723
724 EXC_COMMON_BEGIN(unrecov_slb)
725 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
726 RECONCILE_IRQ_STATE(r10, r11)
727 bl save_nvgprs
728 1: addi r3,r1,STACK_FRAME_OVERHEAD
729 bl unrecoverable_exception
730 b 1b
731
732 EXC_COMMON_BEGIN(bad_addr_slb)
733 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
734 RECONCILE_IRQ_STATE(r10, r11)
735 ld r3, PACA_EXSLB+EX_DAR(r13)
736 std r3, _DAR(r1)
737 beq cr6, 2f
738 li r10, 0x480 /* fix trap number for I-SLB miss */
739 std r10, _TRAP(r1)
740 2: bl save_nvgprs
741 addi r3, r1, STACK_FRAME_OVERHEAD
742 bl slb_miss_bad_addr
743 b ret_from_except
744
745 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600)
746 .globl hardware_interrupt_hv;
747 hardware_interrupt_hv:
748 BEGIN_FTR_SECTION
749 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
750 EXC_HV, SOFTEN_TEST_HV)
751 do_kvm_H0x500:
752 KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502)
753 FTR_SECTION_ELSE
754 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
755 EXC_STD, SOFTEN_TEST_PR)
756 do_kvm_0x500:
757 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500)
758 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
759 EXC_REAL_END(hardware_interrupt, 0x500, 0x600)
760
761 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600)
762 .globl hardware_interrupt_relon_hv;
763 hardware_interrupt_relon_hv:
764 BEGIN_FTR_SECTION
765 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
766 FTR_SECTION_ELSE
767 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
768 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
769 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600)
770
771 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
772
773
774 EXC_REAL(alignment, 0x600, 0x700)
775
776 TRAMP_KVM(PACA_EXGEN, 0x600)
777
778 EXC_REAL(program_check, 0x700, 0x800)
779
780 TRAMP_KVM(PACA_EXGEN, 0x700)
781
782 EXC_REAL(fp_unavailable, 0x800, 0x900)
783
784 TRAMP_KVM(PACA_EXGEN, 0x800)
785
786 EXC_REAL_MASKABLE(decrementer, 0x900, 0x980)
787
788 EXC_REAL_HV(hdecrementer, 0x980, 0xa00)
789
790 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00)
791
792 TRAMP_KVM(PACA_EXGEN, 0xa00)
793
794 EXC_REAL(trap_0b, 0xb00, 0xc00)
795
796 TRAMP_KVM(PACA_EXGEN, 0xb00)
797
798 EXC_REAL_BEGIN(system_call, 0xc00, 0xd00)
799 /*
800 * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems
801 * that support it) before changing to HMT_MEDIUM. That allows the KVM
802 * code to save that value into the guest state (it is the guest's PPR
803 * value). Otherwise just change to HMT_MEDIUM as userspace has
804 * already saved the PPR.
805 */
806 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
807 SET_SCRATCH0(r13)
808 GET_PACA(r13)
809 std r9,PACA_EXGEN+EX_R9(r13)
810 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR);
811 HMT_MEDIUM;
812 std r10,PACA_EXGEN+EX_R10(r13)
813 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR);
814 mfcr r9
815 KVMTEST_PR(0xc00)
816 GET_SCRATCH0(r13)
817 #else
818 HMT_MEDIUM;
819 #endif
820 SYSCALL_PSERIES_1
821 SYSCALL_PSERIES_2_RFID
822 SYSCALL_PSERIES_3
823 EXC_REAL_END(system_call, 0xc00, 0xd00)
824
825 TRAMP_KVM(PACA_EXGEN, 0xc00)
826
827 EXC_REAL(single_step, 0xd00, 0xe00)
828
829 TRAMP_KVM(PACA_EXGEN, 0xd00)
830
831
832 /* At 0xe??? we have a bunch of hypervisor exceptions, we branch
833 * out of line to handle them
834 */
835 __EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20)
836
837 __EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40)
838
839 __EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60)
840
841 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early)
842
843 __EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0)
844
845 __EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0)
846
847 EXC_REAL_NONE(0xec0, 0xf00)
848
849 __EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20)
850
851 __EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40)
852
853 __EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60)
854
855 __EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80)
856
857 __EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0)
858
859 EXC_REAL_NONE(0xfa0, 0x1200)
860
861 #ifdef CONFIG_CBE_RAS
862 EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300)
863
864 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
865
866 #else /* CONFIG_CBE_RAS */
867 EXC_REAL_NONE(0x1200, 0x1300)
868 #endif
869
870 EXC_REAL(instruction_breakpoint, 0x1300, 0x1400)
871
872 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
873
874 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600)
875 mtspr SPRN_SPRG_HSCRATCH0,r13
876 EXCEPTION_PROLOG_0(PACA_EXGEN)
877 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
878
879 #ifdef CONFIG_PPC_DENORMALISATION
880 mfspr r10,SPRN_HSRR1
881 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
882 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
883 addi r11,r11,-4 /* HSRR0 is next instruction */
884 bne+ denorm_assist
885 #endif
886
887 KVMTEST_PR(0x1500)
888 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
889 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600)
890
891 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
892
893 #ifdef CONFIG_CBE_RAS
894 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700)
895
896 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
897
898 #else /* CONFIG_CBE_RAS */
899 EXC_REAL_NONE(0x1600, 0x1700)
900 #endif
901
902 EXC_REAL(altivec_assist, 0x1700, 0x1800)
903
904 TRAMP_KVM(PACA_EXGEN, 0x1700)
905
906 #ifdef CONFIG_CBE_RAS
907 EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900)
908
909 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
910
911 #else /* CONFIG_CBE_RAS */
912 EXC_REAL_NONE(0x1800, 0x1900)
913 #endif
914
915
916 /*** Out of line interrupts support ***/
917
918 /* moved from 0x200 */
919 TRAMP_KVM(PACA_EXGEN, 0x900)
920 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
921
922 #ifdef CONFIG_PPC_DENORMALISATION
923 TRAMP_REAL_BEGIN(denorm_assist)
924 BEGIN_FTR_SECTION
925 /*
926 * To denormalise we need to move a copy of the register to itself.
927 * For POWER6 do that here for all FP regs.
928 */
929 mfmsr r10
930 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
931 xori r10,r10,(MSR_FE0|MSR_FE1)
932 mtmsrd r10
933 sync
934
935 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
936 #define FMR4(n) FMR2(n) ; FMR2(n+2)
937 #define FMR8(n) FMR4(n) ; FMR4(n+4)
938 #define FMR16(n) FMR8(n) ; FMR8(n+8)
939 #define FMR32(n) FMR16(n) ; FMR16(n+16)
940 FMR32(0)
941
942 FTR_SECTION_ELSE
943 /*
944 * To denormalise we need to move a copy of the register to itself.
945 * For POWER7 do that here for the first 32 VSX registers only.
946 */
947 mfmsr r10
948 oris r10,r10,MSR_VSX@h
949 mtmsrd r10
950 sync
951
952 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
953 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
954 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
955 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
956 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
957 XVCPSGNDP32(0)
958
959 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
960
961 BEGIN_FTR_SECTION
962 b denorm_done
963 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
964 /*
965 * To denormalise we need to move a copy of the register to itself.
966 * For POWER8 we need to do that for all 64 VSX registers
967 */
968 XVCPSGNDP32(32)
969 denorm_done:
970 mtspr SPRN_HSRR0,r11
971 mtcrf 0x80,r9
972 ld r9,PACA_EXGEN+EX_R9(r13)
973 RESTORE_PPR_PACA(PACA_EXGEN, r10)
974 BEGIN_FTR_SECTION
975 ld r10,PACA_EXGEN+EX_CFAR(r13)
976 mtspr SPRN_CFAR,r10
977 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
978 ld r10,PACA_EXGEN+EX_R10(r13)
979 ld r11,PACA_EXGEN+EX_R11(r13)
980 ld r12,PACA_EXGEN+EX_R12(r13)
981 ld r13,PACA_EXGEN+EX_R13(r13)
982 HRFID
983 b .
984 #endif
985
986 /* moved from 0xe00 */
987 __TRAMP_REAL_REAL_OOL_HV(h_data_storage, 0xe00)
988 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
989
990 __TRAMP_REAL_REAL_OOL_HV(h_instr_storage, 0xe20)
991 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
992
993 __TRAMP_REAL_REAL_OOL_HV(emulation_assist, 0xe40)
994 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
995
996 __TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
997 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
998
999 __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80)
1000 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1001
1002 __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0)
1003 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1004
1005 /* moved from 0xf00 */
1006 __TRAMP_REAL_REAL_OOL(performance_monitor, 0xf00)
1007 TRAMP_KVM(PACA_EXGEN, 0xf00)
1008
1009 __TRAMP_REAL_REAL_OOL(altivec_unavailable, 0xf20)
1010 TRAMP_KVM(PACA_EXGEN, 0xf20)
1011
1012 __TRAMP_REAL_REAL_OOL(vsx_unavailable, 0xf40)
1013 TRAMP_KVM(PACA_EXGEN, 0xf40)
1014
1015 __TRAMP_REAL_REAL_OOL(facility_unavailable, 0xf60)
1016 TRAMP_KVM(PACA_EXGEN, 0xf60)
1017
1018 __TRAMP_REAL_REAL_OOL_HV(h_facility_unavailable, 0xf80)
1019 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1020
1021 /*
1022 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1023 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1024 * - If it was a doorbell we return immediately since doorbells are edge
1025 * triggered and won't automatically refire.
1026 * - If it was a HMI we return immediately since we handled it in realmode
1027 * and it won't refire.
1028 * - else we hard disable and return.
1029 * This is called with r10 containing the value to OR to the paca field.
1030 */
1031 #define MASKED_INTERRUPT(_H) \
1032 masked_##_H##interrupt: \
1033 std r11,PACA_EXGEN+EX_R11(r13); \
1034 lbz r11,PACAIRQHAPPENED(r13); \
1035 or r11,r11,r10; \
1036 stb r11,PACAIRQHAPPENED(r13); \
1037 cmpwi r10,PACA_IRQ_DEC; \
1038 bne 1f; \
1039 lis r10,0x7fff; \
1040 ori r10,r10,0xffff; \
1041 mtspr SPRN_DEC,r10; \
1042 b 2f; \
1043 1: cmpwi r10,PACA_IRQ_DBELL; \
1044 beq 2f; \
1045 cmpwi r10,PACA_IRQ_HMI; \
1046 beq 2f; \
1047 mfspr r10,SPRN_##_H##SRR1; \
1048 rldicl r10,r10,48,1; /* clear MSR_EE */ \
1049 rotldi r10,r10,16; \
1050 mtspr SPRN_##_H##SRR1,r10; \
1051 2: mtcrf 0x80,r9; \
1052 ld r9,PACA_EXGEN+EX_R9(r13); \
1053 ld r10,PACA_EXGEN+EX_R10(r13); \
1054 ld r11,PACA_EXGEN+EX_R11(r13); \
1055 GET_SCRATCH0(r13); \
1056 ##_H##rfid; \
1057 b .
1058
1059 /*
1060 * Real mode exceptions actually use this too, but alternate
1061 * instruction code patches (which end up in the common .text area)
1062 * cannot reach these if they are put there.
1063 */
1064 USE_FIXED_SECTION(virt_trampolines)
1065 MASKED_INTERRUPT()
1066 MASKED_INTERRUPT(H)
1067
1068 /*
1069 * Called from arch_local_irq_enable when an interrupt needs
1070 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1071 * which kind of interrupt. MSR:EE is already off. We generate a
1072 * stackframe like if a real interrupt had happened.
1073 *
1074 * Note: While MSR:EE is off, we need to make sure that _MSR
1075 * in the generated frame has EE set to 1 or the exception
1076 * handler will not properly re-enable them.
1077 */
1078 USE_TEXT_SECTION()
1079 _GLOBAL(__replay_interrupt)
1080 /* We are going to jump to the exception common code which
1081 * will retrieve various register values from the PACA which
1082 * we don't give a damn about, so we don't bother storing them.
1083 */
1084 mfmsr r12
1085 mflr r11
1086 mfcr r9
1087 ori r12,r12,MSR_EE
1088 cmpwi r3,0x900
1089 beq decrementer_common
1090 cmpwi r3,0x500
1091 beq hardware_interrupt_common
1092 BEGIN_FTR_SECTION
1093 cmpwi r3,0xe80
1094 beq h_doorbell_common
1095 cmpwi r3,0xea0
1096 beq h_virt_irq_common
1097 cmpwi r3,0xe60
1098 beq hmi_exception_common
1099 FTR_SECTION_ELSE
1100 cmpwi r3,0xa00
1101 beq doorbell_super_common
1102 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1103 blr
1104
1105 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1106 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1107 /*
1108 * Here all GPRs are unchanged from when the interrupt happened
1109 * except for r13, which is saved in SPRG_SCRATCH0.
1110 */
1111 mfspr r13, SPRN_SRR0
1112 addi r13, r13, 4
1113 mtspr SPRN_SRR0, r13
1114 GET_SCRATCH0(r13)
1115 rfid
1116 b .
1117
1118 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1119 /*
1120 * Here all GPRs are unchanged from when the interrupt happened
1121 * except for r13, which is saved in SPRG_SCRATCH0.
1122 */
1123 mfspr r13, SPRN_HSRR0
1124 addi r13, r13, 4
1125 mtspr SPRN_HSRR0, r13
1126 GET_SCRATCH0(r13)
1127 hrfid
1128 b .
1129 #endif
1130
1131 /*
1132 * Ensure that any handlers that get invoked from the exception prologs
1133 * above are below the first 64KB (0x10000) of the kernel image because
1134 * the prologs assemble the addresses of these handlers using the
1135 * LOAD_HANDLER macro, which uses an ori instruction.
1136 */
1137
1138 /*** Common interrupt handlers ***/
1139
1140 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
1141 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
1142
1143 #ifdef CONFIG_PPC_DOORBELL
1144 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
1145 #else
1146 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
1147 #endif
1148 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
1149 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
1150 EXC_COMMON(trap_0e_common, 0xe00, unknown_exception)
1151 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1152 EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
1153 #ifdef CONFIG_PPC_DOORBELL
1154 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1155 #else
1156 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1157 #endif
1158 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1159 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1160 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1161 EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1162 #ifdef CONFIG_ALTIVEC
1163 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1164 #else
1165 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1166 #endif
1167
1168 /*
1169 * Relocation-on interrupts: A subset of the interrupts can be delivered
1170 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1171 * it. Addresses are the same as the original interrupt addresses, but
1172 * offset by 0xc000000000004000.
1173 * It's impossible to receive interrupts below 0x300 via this mechanism.
1174 * KVM: None of these traps are from the guest ; anything that escalated
1175 * to HV=1 from HV=0 is delivered via real mode handlers.
1176 */
1177
1178 /*
1179 * This uses the standard macro, since the original 0x300 vector
1180 * only has extra guff for STAB-based processors -- which never
1181 * come here.
1182 */
1183
1184 EXC_VIRT(alignment, 0x4600, 0x4700, 0x600)
1185 EXC_VIRT(program_check, 0x4700, 0x4800, 0x700)
1186 EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800)
1187 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900)
1188 EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980)
1189 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00)
1190 EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00)
1191
1192 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00)
1193 HMT_MEDIUM
1194 SYSCALL_PSERIES_1
1195 SYSCALL_PSERIES_2_DIRECT
1196 SYSCALL_PSERIES_3
1197 EXC_VIRT_END(system_call, 0x4c00, 0x4d00)
1198
1199 EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00)
1200
1201 EXC_VIRT_BEGIN(unused, 0x4e00, 0x4e20)
1202 b . /* Can't happen, see v2.07 Book III-S section 6.5 */
1203 EXC_VIRT_END(unused, 0x4e00, 0x4e20)
1204
1205 EXC_VIRT_BEGIN(unused, 0x4e20, 0x4e40)
1206 b . /* Can't happen, see v2.07 Book III-S section 6.5 */
1207 EXC_VIRT_END(unused, 0x4e20, 0x4e40)
1208
1209 __EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60)
1210
1211 EXC_VIRT_BEGIN(unused, 0x4e60, 0x4e80)
1212 b . /* Can't happen, see v2.07 Book III-S section 6.5 */
1213 EXC_VIRT_END(unused, 0x4e60, 0x4e80)
1214
1215 __EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0)
1216
1217 __EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0)
1218
1219 EXC_VIRT_NONE(0x4ec0, 0x4f00)
1220
1221 __EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20)
1222
1223 __EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40)
1224
1225 __EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60)
1226
1227 __EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80)
1228
1229 __EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0)
1230
1231 EXC_VIRT_NONE(0x4fa0, 0x5200)
1232
1233 EXC_VIRT_NONE(0x5200, 0x5300)
1234
1235 EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300)
1236
1237 #ifdef CONFIG_PPC_DENORMALISATION
1238 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600)
1239 b exc_real_0x1500_denorm_exception_hv
1240 EXC_VIRT_END(denorm_exception, 0x5500, 0x5600)
1241 #else
1242 EXC_VIRT_NONE(0x5500, 0x5600)
1243 #endif
1244
1245 EXC_VIRT_NONE(0x5600, 0x5700)
1246
1247 EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700)
1248
1249 EXC_VIRT_NONE(0x5800, 0x5900)
1250
1251 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1252 b __ppc64_runlatch_on
1253
1254 EXC_COMMON_BEGIN(h_data_storage_common)
1255 mfspr r10,SPRN_HDAR
1256 std r10,PACA_EXGEN+EX_DAR(r13)
1257 mfspr r10,SPRN_HDSISR
1258 stw r10,PACA_EXGEN+EX_DSISR(r13)
1259 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
1260 bl save_nvgprs
1261 RECONCILE_IRQ_STATE(r10, r11)
1262 addi r3,r1,STACK_FRAME_OVERHEAD
1263 bl unknown_exception
1264 b ret_from_except
1265
1266
1267 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1268
1269 EXC_COMMON_BEGIN(alignment_common)
1270 mfspr r10,SPRN_DAR
1271 std r10,PACA_EXGEN+EX_DAR(r13)
1272 mfspr r10,SPRN_DSISR
1273 stw r10,PACA_EXGEN+EX_DSISR(r13)
1274 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1275 ld r3,PACA_EXGEN+EX_DAR(r13)
1276 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1277 std r3,_DAR(r1)
1278 std r4,_DSISR(r1)
1279 bl save_nvgprs
1280 RECONCILE_IRQ_STATE(r10, r11)
1281 addi r3,r1,STACK_FRAME_OVERHEAD
1282 bl alignment_exception
1283 b ret_from_except
1284
1285 EXC_COMMON_BEGIN(program_check_common)
1286 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1287 bl save_nvgprs
1288 RECONCILE_IRQ_STATE(r10, r11)
1289 addi r3,r1,STACK_FRAME_OVERHEAD
1290 bl program_check_exception
1291 b ret_from_except
1292
1293 EXC_COMMON_BEGIN(fp_unavailable_common)
1294 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1295 bne 1f /* if from user, just load it up */
1296 bl save_nvgprs
1297 RECONCILE_IRQ_STATE(r10, r11)
1298 addi r3,r1,STACK_FRAME_OVERHEAD
1299 bl kernel_fp_unavailable_exception
1300 BUG_OPCODE
1301 1:
1302 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1303 BEGIN_FTR_SECTION
1304 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1305 * transaction), go do TM stuff
1306 */
1307 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1308 bne- 2f
1309 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1310 #endif
1311 bl load_up_fpu
1312 b fast_exception_return
1313 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1314 2: /* User process was in a transaction */
1315 bl save_nvgprs
1316 RECONCILE_IRQ_STATE(r10, r11)
1317 addi r3,r1,STACK_FRAME_OVERHEAD
1318 bl fp_unavailable_tm
1319 b ret_from_except
1320 #endif
1321
1322 EXC_COMMON_BEGIN(altivec_unavailable_common)
1323 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1324 #ifdef CONFIG_ALTIVEC
1325 BEGIN_FTR_SECTION
1326 beq 1f
1327 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1328 BEGIN_FTR_SECTION_NESTED(69)
1329 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1330 * transaction), go do TM stuff
1331 */
1332 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1333 bne- 2f
1334 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1335 #endif
1336 bl load_up_altivec
1337 b fast_exception_return
1338 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1339 2: /* User process was in a transaction */
1340 bl save_nvgprs
1341 RECONCILE_IRQ_STATE(r10, r11)
1342 addi r3,r1,STACK_FRAME_OVERHEAD
1343 bl altivec_unavailable_tm
1344 b ret_from_except
1345 #endif
1346 1:
1347 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1348 #endif
1349 bl save_nvgprs
1350 RECONCILE_IRQ_STATE(r10, r11)
1351 addi r3,r1,STACK_FRAME_OVERHEAD
1352 bl altivec_unavailable_exception
1353 b ret_from_except
1354
1355 EXC_COMMON_BEGIN(vsx_unavailable_common)
1356 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1357 #ifdef CONFIG_VSX
1358 BEGIN_FTR_SECTION
1359 beq 1f
1360 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1361 BEGIN_FTR_SECTION_NESTED(69)
1362 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1363 * transaction), go do TM stuff
1364 */
1365 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1366 bne- 2f
1367 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1368 #endif
1369 b load_up_vsx
1370 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1371 2: /* User process was in a transaction */
1372 bl save_nvgprs
1373 RECONCILE_IRQ_STATE(r10, r11)
1374 addi r3,r1,STACK_FRAME_OVERHEAD
1375 bl vsx_unavailable_tm
1376 b ret_from_except
1377 #endif
1378 1:
1379 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1380 #endif
1381 bl save_nvgprs
1382 RECONCILE_IRQ_STATE(r10, r11)
1383 addi r3,r1,STACK_FRAME_OVERHEAD
1384 bl vsx_unavailable_exception
1385 b ret_from_except
1386
1387 /* Equivalents to the above handlers for relocation-on interrupt vectors */
1388 __TRAMP_REAL_VIRT_OOL_HV(emulation_assist, 0xe40)
1389 __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_doorbell, 0xe80)
1390 __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0xea0)
1391 __TRAMP_REAL_VIRT_OOL(performance_monitor, 0xf00)
1392 __TRAMP_REAL_VIRT_OOL(altivec_unavailable, 0xf20)
1393 __TRAMP_REAL_VIRT_OOL(vsx_unavailable, 0xf40)
1394 __TRAMP_REAL_VIRT_OOL(facility_unavailable, 0xf60)
1395 __TRAMP_REAL_VIRT_OOL_HV(h_facility_unavailable, 0xf80)
1396
1397 USE_FIXED_SECTION(virt_trampolines)
1398 /*
1399 * The __end_interrupts marker must be past the out-of-line (OOL)
1400 * handlers, so that they are copied to real address 0x100 when running
1401 * a relocatable kernel. This ensures they can be reached from the short
1402 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1403 * directly, without using LOAD_HANDLER().
1404 */
1405 .align 7
1406 .globl __end_interrupts
1407 __end_interrupts:
1408 DEFINE_FIXED_SYMBOL(__end_interrupts)
1409
1410 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1411 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1412
1413 #ifdef CONFIG_CBE_RAS
1414 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1415 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1416 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1417 #endif /* CONFIG_CBE_RAS */
1418
1419
1420 TRAMP_REAL_BEGIN(hmi_exception_early)
1421 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1422 mr r10,r1 /* Save r1 */
1423 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1424 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1425 std r9,_CCR(r1) /* save CR in stackframe */
1426 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1427 std r11,_NIP(r1) /* save HSRR0 in stackframe */
1428 mfspr r12,SPRN_HSRR1 /* Save SRR1 */
1429 std r12,_MSR(r1) /* save SRR1 in stackframe */
1430 std r10,0(r1) /* make stack chain pointer */
1431 std r0,GPR0(r1) /* save r0 in stackframe */
1432 std r10,GPR1(r1) /* save r1 in stackframe */
1433 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1434 EXCEPTION_PROLOG_COMMON_3(0xe60)
1435 addi r3,r1,STACK_FRAME_OVERHEAD
1436 bl hmi_exception_realmode
1437 /* Windup the stack. */
1438 /* Move original HSRR0 and HSRR1 into the respective regs */
1439 ld r9,_MSR(r1)
1440 mtspr SPRN_HSRR1,r9
1441 ld r3,_NIP(r1)
1442 mtspr SPRN_HSRR0,r3
1443 ld r9,_CTR(r1)
1444 mtctr r9
1445 ld r9,_XER(r1)
1446 mtxer r9
1447 ld r9,_LINK(r1)
1448 mtlr r9
1449 REST_GPR(0, r1)
1450 REST_8GPRS(2, r1)
1451 REST_GPR(10, r1)
1452 ld r11,_CCR(r1)
1453 mtcr r11
1454 REST_GPR(11, r1)
1455 REST_2GPRS(12, r1)
1456 /* restore original r1. */
1457 ld r1,GPR1(r1)
1458
1459 /*
1460 * Go to virtual mode and pull the HMI event information from
1461 * firmware.
1462 */
1463 .globl hmi_exception_after_realmode
1464 hmi_exception_after_realmode:
1465 SET_SCRATCH0(r13)
1466 EXCEPTION_PROLOG_0(PACA_EXGEN)
1467 b tramp_real_hmi_exception
1468
1469 #ifdef CONFIG_PPC_970_NAP
1470 TRAMP_REAL_BEGIN(power4_fixup_nap)
1471 andc r9,r9,r10
1472 std r9,TI_LOCAL_FLAGS(r11)
1473 ld r10,_LINK(r1) /* make idle task do the */
1474 std r10,_NIP(r1) /* equivalent of a blr */
1475 blr
1476 #endif
1477
1478 CLOSE_FIXED_SECTION(real_vectors);
1479 CLOSE_FIXED_SECTION(real_trampolines);
1480 CLOSE_FIXED_SECTION(virt_vectors);
1481 CLOSE_FIXED_SECTION(virt_trampolines);
1482
1483 USE_TEXT_SECTION()
1484
1485 /*
1486 * Hash table stuff
1487 */
1488 .align 7
1489 do_hash_page:
1490 #ifdef CONFIG_PPC_STD_MMU_64
1491 andis. r0,r4,0xa410 /* weird error? */
1492 bne- handle_page_fault /* if not, try to insert a HPTE */
1493 andis. r0,r4,DSISR_DABRMATCH@h
1494 bne- handle_dabr_fault
1495 CURRENT_THREAD_INFO(r11, r1)
1496 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1497 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1498 bne 77f /* then don't call hash_page now */
1499
1500 /*
1501 * r3 contains the faulting address
1502 * r4 msr
1503 * r5 contains the trap number
1504 * r6 contains dsisr
1505 *
1506 * at return r3 = 0 for success, 1 for page fault, negative for error
1507 */
1508 mr r4,r12
1509 ld r6,_DSISR(r1)
1510 bl __hash_page /* build HPTE if possible */
1511 cmpdi r3,0 /* see if __hash_page succeeded */
1512
1513 /* Success */
1514 beq fast_exc_return_irq /* Return from exception on success */
1515
1516 /* Error */
1517 blt- 13f
1518 #endif /* CONFIG_PPC_STD_MMU_64 */
1519
1520 /* Here we have a page fault that hash_page can't handle. */
1521 handle_page_fault:
1522 11: ld r4,_DAR(r1)
1523 ld r5,_DSISR(r1)
1524 addi r3,r1,STACK_FRAME_OVERHEAD
1525 bl do_page_fault
1526 cmpdi r3,0
1527 beq+ 12f
1528 bl save_nvgprs
1529 mr r5,r3
1530 addi r3,r1,STACK_FRAME_OVERHEAD
1531 lwz r4,_DAR(r1)
1532 bl bad_page_fault
1533 b ret_from_except
1534
1535 /* We have a data breakpoint exception - handle it */
1536 handle_dabr_fault:
1537 bl save_nvgprs
1538 ld r4,_DAR(r1)
1539 ld r5,_DSISR(r1)
1540 addi r3,r1,STACK_FRAME_OVERHEAD
1541 bl do_break
1542 12: b ret_from_except_lite
1543
1544
1545 #ifdef CONFIG_PPC_STD_MMU_64
1546 /* We have a page fault that hash_page could handle but HV refused
1547 * the PTE insertion
1548 */
1549 13: bl save_nvgprs
1550 mr r5,r3
1551 addi r3,r1,STACK_FRAME_OVERHEAD
1552 ld r4,_DAR(r1)
1553 bl low_hash_fault
1554 b ret_from_except
1555 #endif
1556
1557 /*
1558 * We come here as a result of a DSI at a point where we don't want
1559 * to call hash_page, such as when we are accessing memory (possibly
1560 * user memory) inside a PMU interrupt that occurred while interrupts
1561 * were soft-disabled. We want to invoke the exception handler for
1562 * the access, or panic if there isn't a handler.
1563 */
1564 77: bl save_nvgprs
1565 mr r4,r3
1566 addi r3,r1,STACK_FRAME_OVERHEAD
1567 li r5,SIGSEGV
1568 bl bad_page_fault
1569 b ret_from_except
1570
1571 /*
1572 * Here we have detected that the kernel stack pointer is bad.
1573 * R9 contains the saved CR, r13 points to the paca,
1574 * r10 contains the (bad) kernel stack pointer,
1575 * r11 and r12 contain the saved SRR0 and SRR1.
1576 * We switch to using an emergency stack, save the registers there,
1577 * and call kernel_bad_stack(), which panics.
1578 */
1579 bad_stack:
1580 ld r1,PACAEMERGSP(r13)
1581 subi r1,r1,64+INT_FRAME_SIZE
1582 std r9,_CCR(r1)
1583 std r10,GPR1(r1)
1584 std r11,_NIP(r1)
1585 std r12,_MSR(r1)
1586 mfspr r11,SPRN_DAR
1587 mfspr r12,SPRN_DSISR
1588 std r11,_DAR(r1)
1589 std r12,_DSISR(r1)
1590 mflr r10
1591 mfctr r11
1592 mfxer r12
1593 std r10,_LINK(r1)
1594 std r11,_CTR(r1)
1595 std r12,_XER(r1)
1596 SAVE_GPR(0,r1)
1597 SAVE_GPR(2,r1)
1598 ld r10,EX_R3(r3)
1599 std r10,GPR3(r1)
1600 SAVE_GPR(4,r1)
1601 SAVE_4GPRS(5,r1)
1602 ld r9,EX_R9(r3)
1603 ld r10,EX_R10(r3)
1604 SAVE_2GPRS(9,r1)
1605 ld r9,EX_R11(r3)
1606 ld r10,EX_R12(r3)
1607 ld r11,EX_R13(r3)
1608 std r9,GPR11(r1)
1609 std r10,GPR12(r1)
1610 std r11,GPR13(r1)
1611 BEGIN_FTR_SECTION
1612 ld r10,EX_CFAR(r3)
1613 std r10,ORIG_GPR3(r1)
1614 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1615 SAVE_8GPRS(14,r1)
1616 SAVE_10GPRS(22,r1)
1617 lhz r12,PACA_TRAP_SAVE(r13)
1618 std r12,_TRAP(r1)
1619 addi r11,r1,INT_FRAME_SIZE
1620 std r11,0(r1)
1621 li r12,0
1622 std r12,0(r11)
1623 ld r2,PACATOC(r13)
1624 ld r11,exception_marker@toc(r2)
1625 std r12,RESULT(r1)
1626 std r11,STACK_FRAME_OVERHEAD-16(r1)
1627 1: addi r3,r1,STACK_FRAME_OVERHEAD
1628 bl kernel_bad_stack
1629 b 1b
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