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1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 *
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
23
24 #include <linux/init.h>
25 #include <asm/reg.h>
26 #include <asm/page.h>
27 #include <asm/mmu.h>
28 #include <asm/pgtable.h>
29 #include <asm/cputable.h>
30 #include <asm/cache.h>
31 #include <asm/thread_info.h>
32 #include <asm/ppc_asm.h>
33 #include <asm/asm-offsets.h>
34 #include <asm/ptrace.h>
35 #include <asm/bug.h>
36 #include <asm/kvm_book3s_asm.h>
37 #include <asm/export.h>
38 #include <asm/feature-fixups.h>
39
40 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
41 #define LOAD_BAT(n, reg, RA, RB) \
42 /* see the comment for clear_bats() -- Cort */ \
43 li RA,0; \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_DBAT##n##U,RA; \
46 lwz RA,(n*16)+0(reg); \
47 lwz RB,(n*16)+4(reg); \
48 mtspr SPRN_IBAT##n##U,RA; \
49 mtspr SPRN_IBAT##n##L,RB; \
50 beq 1f; \
51 lwz RA,(n*16)+8(reg); \
52 lwz RB,(n*16)+12(reg); \
53 mtspr SPRN_DBAT##n##U,RA; \
54 mtspr SPRN_DBAT##n##L,RB; \
55 1:
56
57 __HEAD
58 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
59 .stabs "head_32.S",N_SO,0,0,0f
60 0:
61 _ENTRY(_stext);
62
63 /*
64 * _start is defined this way because the XCOFF loader in the OpenFirmware
65 * on the powermac expects the entry point to be a procedure descriptor.
66 */
67 _ENTRY(_start);
68 /*
69 * These are here for legacy reasons, the kernel used to
70 * need to look like a coff function entry for the pmac
71 * but we're always started by some kind of bootloader now.
72 * -- Cort
73 */
74 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
75 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
76 nop
77
78 /* PMAC
79 * Enter here with the kernel text, data and bss loaded starting at
80 * 0, running with virtual == physical mapping.
81 * r5 points to the prom entry point (the client interface handler
82 * address). Address translation is turned on, with the prom
83 * managing the hash table. Interrupts are disabled. The stack
84 * pointer (r1) points to just below the end of the half-meg region
85 * from 0x380000 - 0x400000, which is mapped in already.
86 *
87 * If we are booted from MacOS via BootX, we enter with the kernel
88 * image loaded somewhere, and the following values in registers:
89 * r3: 'BooX' (0x426f6f58)
90 * r4: virtual address of boot_infos_t
91 * r5: 0
92 *
93 * PREP
94 * This is jumped to on prep systems right after the kernel is relocated
95 * to its proper place in memory by the boot loader. The expected layout
96 * of the regs is:
97 * r3: ptr to residual data
98 * r4: initrd_start or if no initrd then 0
99 * r5: initrd_end - unused if r4 is 0
100 * r6: Start of command line string
101 * r7: End of command line string
102 *
103 * This just gets a minimal mmu environment setup so we can call
104 * start_here() to do the real work.
105 * -- Cort
106 */
107
108 .globl __start
109 __start:
110 /*
111 * We have to do any OF calls before we map ourselves to KERNELBASE,
112 * because OF may have I/O devices mapped into that area
113 * (particularly on CHRP).
114 */
115 cmpwi 0,r5,0
116 beq 1f
117
118 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
119 /* find out where we are now */
120 bcl 20,31,$+4
121 0: mflr r8 /* r8 = runtime addr here */
122 addis r8,r8,(_stext - 0b)@ha
123 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
124 bl prom_init
125 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
126
127 /* We never return. We also hit that trap if trying to boot
128 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
129 trap
130
131 /*
132 * Check for BootX signature when supporting PowerMac and branch to
133 * appropriate trampoline if it's present
134 */
135 #ifdef CONFIG_PPC_PMAC
136 1: lis r31,0x426f
137 ori r31,r31,0x6f58
138 cmpw 0,r3,r31
139 bne 1f
140 bl bootx_init
141 trap
142 #endif /* CONFIG_PPC_PMAC */
143
144 1: mr r31,r3 /* save device tree ptr */
145 li r24,0 /* cpu # */
146
147 /*
148 * early_init() does the early machine identification and does
149 * the necessary low-level setup and clears the BSS
150 * -- Cort <cort@fsmlabs.com>
151 */
152 bl early_init
153
154 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
155 * the physical address we are running at, returned by early_init()
156 */
157 bl mmu_off
158 __after_mmu_off:
159 bl clear_bats
160 bl flush_tlbs
161
162 bl initial_bats
163 #if defined(CONFIG_BOOTX_TEXT)
164 bl setup_disp_bat
165 #endif
166 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
167 bl setup_cpm_bat
168 #endif
169 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
170 bl setup_usbgecko_bat
171 #endif
172
173 /*
174 * Call setup_cpu for CPU 0 and initialize 6xx Idle
175 */
176 bl reloc_offset
177 li r24,0 /* cpu# */
178 bl call_setup_cpu /* Call setup_cpu for this CPU */
179 #ifdef CONFIG_PPC_BOOK3S_32
180 bl reloc_offset
181 bl init_idle_6xx
182 #endif /* CONFIG_PPC_BOOK3S_32 */
183
184
185 /*
186 * We need to run with _start at physical address 0.
187 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
188 * the exception vectors at 0 (and therefore this copy
189 * overwrites OF's exception vectors with our own).
190 * The MMU is off at this point.
191 */
192 bl reloc_offset
193 mr r26,r3
194 addis r4,r3,KERNELBASE@h /* current address of _start */
195 lis r5,PHYSICAL_START@h
196 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
197 bne relocate_kernel
198 /*
199 * we now have the 1st 16M of ram mapped with the bats.
200 * prep needs the mmu to be turned on here, but pmac already has it on.
201 * this shouldn't bother the pmac since it just gets turned on again
202 * as we jump to our code at KERNELBASE. -- Cort
203 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
204 * off, and in other cases, we now turn it off before changing BATs above.
205 */
206 turn_on_mmu:
207 mfmsr r0
208 ori r0,r0,MSR_DR|MSR_IR
209 mtspr SPRN_SRR1,r0
210 lis r0,start_here@h
211 ori r0,r0,start_here@l
212 mtspr SPRN_SRR0,r0
213 SYNC
214 RFI /* enables MMU */
215
216 /*
217 * We need __secondary_hold as a place to hold the other cpus on
218 * an SMP machine, even when we are running a UP kernel.
219 */
220 . = 0xc0 /* for prep bootloader */
221 li r3,1 /* MTX only has 1 cpu */
222 .globl __secondary_hold
223 __secondary_hold:
224 /* tell the master we're here */
225 stw r3,__secondary_hold_acknowledge@l(0)
226 #ifdef CONFIG_SMP
227 100: lwz r4,0(0)
228 /* wait until we're told to start */
229 cmpw 0,r4,r3
230 bne 100b
231 /* our cpu # was at addr 0 - go */
232 mr r24,r3 /* cpu # */
233 b __secondary_start
234 #else
235 b .
236 #endif /* CONFIG_SMP */
237
238 .globl __secondary_hold_spinloop
239 __secondary_hold_spinloop:
240 .long 0
241 .globl __secondary_hold_acknowledge
242 __secondary_hold_acknowledge:
243 .long -1
244
245 /*
246 * Exception entry code. This code runs with address translation
247 * turned off, i.e. using physical addresses.
248 * We assume sprg3 has the physical address of the current
249 * task's thread_struct.
250 */
251 #define EXCEPTION_PROLOG \
252 mtspr SPRN_SPRG_SCRATCH0,r10; \
253 mtspr SPRN_SPRG_SCRATCH1,r11; \
254 mfcr r10; \
255 EXCEPTION_PROLOG_1; \
256 EXCEPTION_PROLOG_2
257
258 #define EXCEPTION_PROLOG_1 \
259 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
260 andi. r11,r11,MSR_PR; \
261 tophys(r11,r1); /* use tophys(r1) if kernel */ \
262 beq 1f; \
263 mfspr r11,SPRN_SPRG_THREAD; \
264 lwz r11,THREAD_INFO-THREAD(r11); \
265 addi r11,r11,THREAD_SIZE; \
266 tophys(r11,r11); \
267 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
268
269
270 #define EXCEPTION_PROLOG_2 \
271 stw r10,_CCR(r11); /* save registers */ \
272 stw r12,GPR12(r11); \
273 stw r9,GPR9(r11); \
274 mfspr r10,SPRN_SPRG_SCRATCH0; \
275 stw r10,GPR10(r11); \
276 mfspr r12,SPRN_SPRG_SCRATCH1; \
277 stw r12,GPR11(r11); \
278 mflr r10; \
279 stw r10,_LINK(r11); \
280 mfspr r12,SPRN_SRR0; \
281 mfspr r9,SPRN_SRR1; \
282 stw r1,GPR1(r11); \
283 stw r1,0(r11); \
284 tovirt(r1,r11); /* set new kernel sp */ \
285 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
286 MTMSRD(r10); /* (except for mach check in rtas) */ \
287 stw r0,GPR0(r11); \
288 lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
289 addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
290 stw r10,8(r11); \
291 SAVE_4GPRS(3, r11); \
292 SAVE_2GPRS(7, r11)
293
294 /*
295 * Note: code which follows this uses cr0.eq (set if from kernel),
296 * r11, r12 (SRR0), and r9 (SRR1).
297 *
298 * Note2: once we have set r1 we are in a position to take exceptions
299 * again, and we could thus set MSR:RI at that point.
300 */
301
302 /*
303 * Exception vectors.
304 */
305 #define EXCEPTION(n, label, hdlr, xfer) \
306 . = n; \
307 DO_KVM n; \
308 label: \
309 EXCEPTION_PROLOG; \
310 addi r3,r1,STACK_FRAME_OVERHEAD; \
311 xfer(n, hdlr)
312
313 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
314 li r10,trap; \
315 stw r10,_TRAP(r11); \
316 li r10,MSR_KERNEL; \
317 copyee(r10, r9); \
318 bl tfer; \
319 i##n: \
320 .long hdlr; \
321 .long ret
322
323 #define COPY_EE(d, s) rlwimi d,s,0,16,16
324 #define NOCOPY(d, s)
325
326 #define EXC_XFER_STD(n, hdlr) \
327 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
328 ret_from_except_full)
329
330 #define EXC_XFER_LITE(n, hdlr) \
331 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
332 ret_from_except)
333
334 #define EXC_XFER_EE(n, hdlr) \
335 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
336 ret_from_except_full)
337
338 #define EXC_XFER_EE_LITE(n, hdlr) \
339 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
340 ret_from_except)
341
342 /* System reset */
343 /* core99 pmac starts the seconary here by changing the vector, and
344 putting it back to what it was (unknown_exception) when done. */
345 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
346
347 /* Machine check */
348 /*
349 * On CHRP, this is complicated by the fact that we could get a
350 * machine check inside RTAS, and we have no guarantee that certain
351 * critical registers will have the values we expect. The set of
352 * registers that might have bad values includes all the GPRs
353 * and all the BATs. We indicate that we are in RTAS by putting
354 * a non-zero value, the address of the exception frame to use,
355 * in SPRG2. The machine check handler checks SPRG2 and uses its
356 * value if it is non-zero. If we ever needed to free up SPRG2,
357 * we could use a field in the thread_info or thread_struct instead.
358 * (Other exception handlers assume that r1 is a valid kernel stack
359 * pointer when we take an exception from supervisor mode.)
360 * -- paulus.
361 */
362 . = 0x200
363 DO_KVM 0x200
364 mtspr SPRN_SPRG_SCRATCH0,r10
365 mtspr SPRN_SPRG_SCRATCH1,r11
366 mfcr r10
367 #ifdef CONFIG_PPC_CHRP
368 mfspr r11,SPRN_SPRG_RTAS
369 cmpwi 0,r11,0
370 bne 7f
371 #endif /* CONFIG_PPC_CHRP */
372 EXCEPTION_PROLOG_1
373 7: EXCEPTION_PROLOG_2
374 addi r3,r1,STACK_FRAME_OVERHEAD
375 #ifdef CONFIG_PPC_CHRP
376 mfspr r4,SPRN_SPRG_RTAS
377 cmpwi cr1,r4,0
378 bne cr1,1f
379 #endif
380 EXC_XFER_STD(0x200, machine_check_exception)
381 #ifdef CONFIG_PPC_CHRP
382 1: b machine_check_in_rtas
383 #endif
384
385 /* Data access exception. */
386 . = 0x300
387 DO_KVM 0x300
388 DataAccess:
389 EXCEPTION_PROLOG
390 mfspr r10,SPRN_DSISR
391 stw r10,_DSISR(r11)
392 andis. r0,r10,(DSISR_BAD_FAULT_32S|DSISR_DABRMATCH)@h
393 bne 1f /* if not, try to put a PTE */
394 mfspr r4,SPRN_DAR /* into the hash table */
395 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
396 BEGIN_MMU_FTR_SECTION
397 bl hash_page
398 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
399 1: lwz r5,_DSISR(r11) /* get DSISR value */
400 mfspr r4,SPRN_DAR
401 EXC_XFER_LITE(0x300, handle_page_fault)
402
403
404 /* Instruction access exception. */
405 . = 0x400
406 DO_KVM 0x400
407 InstructionAccess:
408 EXCEPTION_PROLOG
409 andis. r0,r9,SRR1_ISI_NOPT@h /* no pte found? */
410 beq 1f /* if so, try to put a PTE */
411 li r3,0 /* into the hash table */
412 mr r4,r12 /* SRR0 is fault address */
413 BEGIN_MMU_FTR_SECTION
414 bl hash_page
415 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
416 1: mr r4,r12
417 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
418 EXC_XFER_LITE(0x400, handle_page_fault)
419
420 /* External interrupt */
421 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
422
423 /* Alignment exception */
424 . = 0x600
425 DO_KVM 0x600
426 Alignment:
427 EXCEPTION_PROLOG
428 mfspr r4,SPRN_DAR
429 stw r4,_DAR(r11)
430 mfspr r5,SPRN_DSISR
431 stw r5,_DSISR(r11)
432 addi r3,r1,STACK_FRAME_OVERHEAD
433 EXC_XFER_EE(0x600, alignment_exception)
434
435 /* Program check exception */
436 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
437
438 /* Floating-point unavailable */
439 . = 0x800
440 DO_KVM 0x800
441 FPUnavailable:
442 BEGIN_FTR_SECTION
443 /*
444 * Certain Freescale cores don't have a FPU and treat fp instructions
445 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
446 */
447 b ProgramCheck
448 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
449 EXCEPTION_PROLOG
450 beq 1f
451 bl load_up_fpu /* if from user, just load it up */
452 b fast_exception_return
453 1: addi r3,r1,STACK_FRAME_OVERHEAD
454 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
455
456 /* Decrementer */
457 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
458
459 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
460 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
461
462 /* System call */
463 . = 0xc00
464 DO_KVM 0xc00
465 SystemCall:
466 EXCEPTION_PROLOG
467 EXC_XFER_EE_LITE(0xc00, DoSyscall)
468
469 /* Single step - not used on 601 */
470 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
471 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
472
473 /*
474 * The Altivec unavailable trap is at 0x0f20. Foo.
475 * We effectively remap it to 0x3000.
476 * We include an altivec unavailable exception vector even if
477 * not configured for Altivec, so that you can't panic a
478 * non-altivec kernel running on a machine with altivec just
479 * by executing an altivec instruction.
480 */
481 . = 0xf00
482 DO_KVM 0xf00
483 b PerformanceMonitor
484
485 . = 0xf20
486 DO_KVM 0xf20
487 b AltiVecUnavailable
488
489 /*
490 * Handle TLB miss for instruction on 603/603e.
491 * Note: we get an alternate set of r0 - r3 to use automatically.
492 */
493 . = 0x1000
494 InstructionTLBMiss:
495 /*
496 * r0: scratch
497 * r1: linux style pte ( later becomes ppc hardware pte )
498 * r2: ptr to linux-style pte
499 * r3: scratch
500 */
501 /* Get PTE (linux-style) and check access */
502 mfspr r3,SPRN_IMISS
503 lis r1,PAGE_OFFSET@h /* check if kernel address */
504 cmplw 0,r1,r3
505 mfspr r2,SPRN_SPRG_THREAD
506 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
507 lwz r2,PGDIR(r2)
508 bge- 112f
509 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
510 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
511 lis r2,swapper_pg_dir@ha /* if kernel address, use */
512 addi r2,r2,swapper_pg_dir@l /* kernel page table */
513 112: tophys(r2,r2)
514 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
515 lwz r2,0(r2) /* get pmd entry */
516 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
517 beq- InstructionAddressInvalid /* return if no mapping */
518 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
519 lwz r0,0(r2) /* get linux-style pte */
520 andc. r1,r1,r0 /* check access & ~permission */
521 bne- InstructionAddressInvalid /* return if access not permitted */
522 ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
523 /*
524 * NOTE! We are assuming this is not an SMP system, otherwise
525 * we would need to update the pte atomically with lwarx/stwcx.
526 */
527 stw r0,0(r2) /* update PTE (accessed bit) */
528 /* Convert linux-style PTE to low word of PPC-style PTE */
529 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
530 rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
531 and r1,r1,r2 /* writable if _RW and _DIRTY */
532 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
533 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
534 ori r1,r1,0xe04 /* clear out reserved bits */
535 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
536 BEGIN_FTR_SECTION
537 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
538 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
539 mtspr SPRN_RPA,r1
540 tlbli r3
541 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
542 mtcrf 0x80,r3
543 rfi
544 InstructionAddressInvalid:
545 mfspr r3,SPRN_SRR1
546 rlwinm r1,r3,9,6,6 /* Get load/store bit */
547
548 addis r1,r1,0x2000
549 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
550 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
551 or r2,r2,r1
552 mtspr SPRN_SRR1,r2
553 mfspr r1,SPRN_IMISS /* Get failing address */
554 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
555 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
556 xor r1,r1,r2
557 mtspr SPRN_DAR,r1 /* Set fault address */
558 mfmsr r0 /* Restore "normal" registers */
559 xoris r0,r0,MSR_TGPR>>16
560 mtcrf 0x80,r3 /* Restore CR0 */
561 mtmsr r0
562 b InstructionAccess
563
564 /*
565 * Handle TLB miss for DATA Load operation on 603/603e
566 */
567 . = 0x1100
568 DataLoadTLBMiss:
569 /*
570 * r0: scratch
571 * r1: linux style pte ( later becomes ppc hardware pte )
572 * r2: ptr to linux-style pte
573 * r3: scratch
574 */
575 /* Get PTE (linux-style) and check access */
576 mfspr r3,SPRN_DMISS
577 lis r1,PAGE_OFFSET@h /* check if kernel address */
578 cmplw 0,r1,r3
579 mfspr r2,SPRN_SPRG_THREAD
580 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
581 lwz r2,PGDIR(r2)
582 bge- 112f
583 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
584 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
585 lis r2,swapper_pg_dir@ha /* if kernel address, use */
586 addi r2,r2,swapper_pg_dir@l /* kernel page table */
587 112: tophys(r2,r2)
588 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
589 lwz r2,0(r2) /* get pmd entry */
590 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
591 beq- DataAddressInvalid /* return if no mapping */
592 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
593 lwz r0,0(r2) /* get linux-style pte */
594 andc. r1,r1,r0 /* check access & ~permission */
595 bne- DataAddressInvalid /* return if access not permitted */
596 ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
597 /*
598 * NOTE! We are assuming this is not an SMP system, otherwise
599 * we would need to update the pte atomically with lwarx/stwcx.
600 */
601 stw r0,0(r2) /* update PTE (accessed bit) */
602 /* Convert linux-style PTE to low word of PPC-style PTE */
603 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
604 rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
605 and r1,r1,r2 /* writable if _RW and _DIRTY */
606 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
607 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
608 ori r1,r1,0xe04 /* clear out reserved bits */
609 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
610 BEGIN_FTR_SECTION
611 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
612 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
613 mtspr SPRN_RPA,r1
614 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
615 mtcrf 0x80,r2
616 BEGIN_MMU_FTR_SECTION
617 li r0,1
618 mfspr r1,SPRN_SPRG_603_LRU
619 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
620 slw r0,r0,r2
621 xor r1,r0,r1
622 srw r0,r1,r2
623 mtspr SPRN_SPRG_603_LRU,r1
624 mfspr r2,SPRN_SRR1
625 rlwimi r2,r0,31-14,14,14
626 mtspr SPRN_SRR1,r2
627 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
628 tlbld r3
629 rfi
630 DataAddressInvalid:
631 mfspr r3,SPRN_SRR1
632 rlwinm r1,r3,9,6,6 /* Get load/store bit */
633 addis r1,r1,0x2000
634 mtspr SPRN_DSISR,r1
635 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
636 mtspr SPRN_SRR1,r2
637 mfspr r1,SPRN_DMISS /* Get failing address */
638 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
639 beq 20f /* Jump if big endian */
640 xori r1,r1,3
641 20: mtspr SPRN_DAR,r1 /* Set fault address */
642 mfmsr r0 /* Restore "normal" registers */
643 xoris r0,r0,MSR_TGPR>>16
644 mtcrf 0x80,r3 /* Restore CR0 */
645 mtmsr r0
646 b DataAccess
647
648 /*
649 * Handle TLB miss for DATA Store on 603/603e
650 */
651 . = 0x1200
652 DataStoreTLBMiss:
653 /*
654 * r0: scratch
655 * r1: linux style pte ( later becomes ppc hardware pte )
656 * r2: ptr to linux-style pte
657 * r3: scratch
658 */
659 /* Get PTE (linux-style) and check access */
660 mfspr r3,SPRN_DMISS
661 lis r1,PAGE_OFFSET@h /* check if kernel address */
662 cmplw 0,r1,r3
663 mfspr r2,SPRN_SPRG_THREAD
664 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
665 lwz r2,PGDIR(r2)
666 bge- 112f
667 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
668 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
669 lis r2,swapper_pg_dir@ha /* if kernel address, use */
670 addi r2,r2,swapper_pg_dir@l /* kernel page table */
671 112: tophys(r2,r2)
672 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
673 lwz r2,0(r2) /* get pmd entry */
674 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
675 beq- DataAddressInvalid /* return if no mapping */
676 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
677 lwz r0,0(r2) /* get linux-style pte */
678 andc. r1,r1,r0 /* check access & ~permission */
679 bne- DataAddressInvalid /* return if access not permitted */
680 ori r0,r0,_PAGE_ACCESSED|_PAGE_DIRTY
681 /*
682 * NOTE! We are assuming this is not an SMP system, otherwise
683 * we would need to update the pte atomically with lwarx/stwcx.
684 */
685 stw r0,0(r2) /* update PTE (accessed/dirty bits) */
686 /* Convert linux-style PTE to low word of PPC-style PTE */
687 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
688 li r1,0xe05 /* clear out reserved bits & PP lsb */
689 andc r1,r0,r1 /* PP = user? 2: 0 */
690 BEGIN_FTR_SECTION
691 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
692 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
693 mtspr SPRN_RPA,r1
694 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
695 mtcrf 0x80,r2
696 BEGIN_MMU_FTR_SECTION
697 li r0,1
698 mfspr r1,SPRN_SPRG_603_LRU
699 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
700 slw r0,r0,r2
701 xor r1,r0,r1
702 srw r0,r1,r2
703 mtspr SPRN_SPRG_603_LRU,r1
704 mfspr r2,SPRN_SRR1
705 rlwimi r2,r0,31-14,14,14
706 mtspr SPRN_SRR1,r2
707 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
708 tlbld r3
709 rfi
710
711 #ifndef CONFIG_ALTIVEC
712 #define altivec_assist_exception unknown_exception
713 #endif
714
715 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
716 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
717 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
718 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
719 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
720 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
721 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
722 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
723 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
724 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
725 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
726 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
727 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
728 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
729 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
730 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
731 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
732 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
733 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
734 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
735 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
736 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
737 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
738 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
739 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
740 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
741 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
742 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
743 EXCEPTION(0x2f00, Trap_2f, unknown_exception, EXC_XFER_EE)
744
745 . = 0x3000
746
747 AltiVecUnavailable:
748 EXCEPTION_PROLOG
749 #ifdef CONFIG_ALTIVEC
750 beq 1f
751 bl load_up_altivec /* if from user, just load it up */
752 b fast_exception_return
753 #endif /* CONFIG_ALTIVEC */
754 1: addi r3,r1,STACK_FRAME_OVERHEAD
755 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
756
757 PerformanceMonitor:
758 EXCEPTION_PROLOG
759 addi r3,r1,STACK_FRAME_OVERHEAD
760 EXC_XFER_STD(0xf00, performance_monitor_exception)
761
762
763 /*
764 * This code is jumped to from the startup code to copy
765 * the kernel image to physical address PHYSICAL_START.
766 */
767 relocate_kernel:
768 addis r9,r26,klimit@ha /* fetch klimit */
769 lwz r25,klimit@l(r9)
770 addis r25,r25,-KERNELBASE@h
771 lis r3,PHYSICAL_START@h /* Destination base address */
772 li r6,0 /* Destination offset */
773 li r5,0x4000 /* # bytes of memory to copy */
774 bl copy_and_flush /* copy the first 0x4000 bytes */
775 addi r0,r3,4f@l /* jump to the address of 4f */
776 mtctr r0 /* in copy and do the rest. */
777 bctr /* jump to the copy */
778 4: mr r5,r25
779 bl copy_and_flush /* copy the rest */
780 b turn_on_mmu
781
782 /*
783 * Copy routine used to copy the kernel to start at physical address 0
784 * and flush and invalidate the caches as needed.
785 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
786 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
787 */
788 _ENTRY(copy_and_flush)
789 addi r5,r5,-4
790 addi r6,r6,-4
791 4: li r0,L1_CACHE_BYTES/4
792 mtctr r0
793 3: addi r6,r6,4 /* copy a cache line */
794 lwzx r0,r6,r4
795 stwx r0,r6,r3
796 bdnz 3b
797 dcbst r6,r3 /* write it to memory */
798 sync
799 icbi r6,r3 /* flush the icache line */
800 cmplw 0,r6,r5
801 blt 4b
802 sync /* additional sync needed on g4 */
803 isync
804 addi r5,r5,4
805 addi r6,r6,4
806 blr
807
808 #ifdef CONFIG_SMP
809 .globl __secondary_start_mpc86xx
810 __secondary_start_mpc86xx:
811 mfspr r3, SPRN_PIR
812 stw r3, __secondary_hold_acknowledge@l(0)
813 mr r24, r3 /* cpu # */
814 b __secondary_start
815
816 .globl __secondary_start_pmac_0
817 __secondary_start_pmac_0:
818 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
819 li r24,0
820 b 1f
821 li r24,1
822 b 1f
823 li r24,2
824 b 1f
825 li r24,3
826 1:
827 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
828 set to map the 0xf0000000 - 0xffffffff region */
829 mfmsr r0
830 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
831 SYNC
832 mtmsr r0
833 isync
834
835 .globl __secondary_start
836 __secondary_start:
837 /* Copy some CPU settings from CPU 0 */
838 bl __restore_cpu_setup
839
840 lis r3,-KERNELBASE@h
841 mr r4,r24
842 bl call_setup_cpu /* Call setup_cpu for this CPU */
843 #ifdef CONFIG_PPC_BOOK3S_32
844 lis r3,-KERNELBASE@h
845 bl init_idle_6xx
846 #endif /* CONFIG_PPC_BOOK3S_32 */
847
848 /* get current_thread_info and current */
849 lis r1,secondary_ti@ha
850 tophys(r1,r1)
851 lwz r1,secondary_ti@l(r1)
852 tophys(r2,r1)
853 lwz r2,TI_TASK(r2)
854
855 /* stack */
856 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
857 li r0,0
858 tophys(r3,r1)
859 stw r0,0(r3)
860
861 /* load up the MMU */
862 bl load_up_mmu
863
864 /* ptr to phys current thread */
865 tophys(r4,r2)
866 addi r4,r4,THREAD /* phys address of our thread_struct */
867 mtspr SPRN_SPRG_THREAD,r4
868 li r3,0
869 mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
870
871 /* enable MMU and jump to start_secondary */
872 li r4,MSR_KERNEL
873 lis r3,start_secondary@h
874 ori r3,r3,start_secondary@l
875 mtspr SPRN_SRR0,r3
876 mtspr SPRN_SRR1,r4
877 SYNC
878 RFI
879 #endif /* CONFIG_SMP */
880
881 #ifdef CONFIG_KVM_BOOK3S_HANDLER
882 #include "../kvm/book3s_rmhandlers.S"
883 #endif
884
885 /*
886 * Those generic dummy functions are kept for CPUs not
887 * included in CONFIG_PPC_BOOK3S_32
888 */
889 #if !defined(CONFIG_PPC_BOOK3S_32)
890 _ENTRY(__save_cpu_setup)
891 blr
892 _ENTRY(__restore_cpu_setup)
893 blr
894 #endif /* !defined(CONFIG_PPC_BOOK3S_32) */
895
896
897 /*
898 * Load stuff into the MMU. Intended to be called with
899 * IR=0 and DR=0.
900 */
901 load_up_mmu:
902 sync /* Force all PTE updates to finish */
903 isync
904 tlbia /* Clear all TLB entries */
905 sync /* wait for tlbia/tlbie to finish */
906 TLBSYNC /* ... on all CPUs */
907 /* Load the SDR1 register (hash table base & size) */
908 lis r6,_SDR1@ha
909 tophys(r6,r6)
910 lwz r6,_SDR1@l(r6)
911 mtspr SPRN_SDR1,r6
912 li r0,16 /* load up segment register values */
913 mtctr r0 /* for context 0 */
914 lis r3,0x2000 /* Ku = 1, VSID = 0 */
915 li r4,0
916 3: mtsrin r3,r4
917 addi r3,r3,0x111 /* increment VSID */
918 addis r4,r4,0x1000 /* address of next segment */
919 bdnz 3b
920
921 /* Load the BAT registers with the values set up by MMU_init.
922 MMU_init takes care of whether we're on a 601 or not. */
923 mfpvr r3
924 srwi r3,r3,16
925 cmpwi r3,1
926 lis r3,BATS@ha
927 addi r3,r3,BATS@l
928 tophys(r3,r3)
929 LOAD_BAT(0,r3,r4,r5)
930 LOAD_BAT(1,r3,r4,r5)
931 LOAD_BAT(2,r3,r4,r5)
932 LOAD_BAT(3,r3,r4,r5)
933 BEGIN_MMU_FTR_SECTION
934 LOAD_BAT(4,r3,r4,r5)
935 LOAD_BAT(5,r3,r4,r5)
936 LOAD_BAT(6,r3,r4,r5)
937 LOAD_BAT(7,r3,r4,r5)
938 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
939 blr
940
941 /*
942 * This is where the main kernel code starts.
943 */
944 start_here:
945 /* ptr to current */
946 lis r2,init_task@h
947 ori r2,r2,init_task@l
948 /* Set up for using our exception vectors */
949 /* ptr to phys current thread */
950 tophys(r4,r2)
951 addi r4,r4,THREAD /* init task's THREAD */
952 mtspr SPRN_SPRG_THREAD,r4
953 li r3,0
954 mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
955
956 /* stack */
957 lis r1,init_thread_union@ha
958 addi r1,r1,init_thread_union@l
959 li r0,0
960 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
961 /*
962 * Do early platform-specific initialization,
963 * and set up the MMU.
964 */
965 li r3,0
966 mr r4,r31
967 bl machine_init
968 bl __save_cpu_setup
969 bl MMU_init
970
971 /*
972 * Go back to running unmapped so we can load up new values
973 * for SDR1 (hash table pointer) and the segment registers
974 * and change to using our exception vectors.
975 */
976 lis r4,2f@h
977 ori r4,r4,2f@l
978 tophys(r4,r4)
979 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
980 mtspr SPRN_SRR0,r4
981 mtspr SPRN_SRR1,r3
982 SYNC
983 RFI
984 /* Load up the kernel context */
985 2: bl load_up_mmu
986
987 #ifdef CONFIG_BDI_SWITCH
988 /* Add helper information for the Abatron bdiGDB debugger.
989 * We do this here because we know the mmu is disabled, and
990 * will be enabled for real in just a few instructions.
991 */
992 lis r5, abatron_pteptrs@h
993 ori r5, r5, abatron_pteptrs@l
994 stw r5, 0xf0(r0) /* This much match your Abatron config */
995 lis r6, swapper_pg_dir@h
996 ori r6, r6, swapper_pg_dir@l
997 tophys(r5, r5)
998 stw r6, 0(r5)
999 #endif /* CONFIG_BDI_SWITCH */
1000
1001 /* Now turn on the MMU for real! */
1002 li r4,MSR_KERNEL
1003 lis r3,start_kernel@h
1004 ori r3,r3,start_kernel@l
1005 mtspr SPRN_SRR0,r3
1006 mtspr SPRN_SRR1,r4
1007 SYNC
1008 RFI
1009
1010 /*
1011 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1012 *
1013 * Set up the segment registers for a new context.
1014 */
1015 _ENTRY(switch_mmu_context)
1016 lwz r3,MMCONTEXTID(r4)
1017 cmpwi cr0,r3,0
1018 blt- 4f
1019 mulli r3,r3,897 /* multiply context by skew factor */
1020 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1021 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1022 li r0,NUM_USER_SEGMENTS
1023 mtctr r0
1024
1025 #ifdef CONFIG_BDI_SWITCH
1026 /* Context switch the PTE pointer for the Abatron BDI2000.
1027 * The PGDIR is passed as second argument.
1028 */
1029 lwz r4,MM_PGD(r4)
1030 lis r5, KERNELBASE@h
1031 lwz r5, 0xf0(r5)
1032 stw r4, 0x4(r5)
1033 #endif
1034 li r4,0
1035 isync
1036 3:
1037 mtsrin r3,r4
1038 addi r3,r3,0x111 /* next VSID */
1039 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1040 addis r4,r4,0x1000 /* address of next segment */
1041 bdnz 3b
1042 sync
1043 isync
1044 blr
1045 4: trap
1046 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1047 blr
1048 EXPORT_SYMBOL(switch_mmu_context)
1049
1050 /*
1051 * An undocumented "feature" of 604e requires that the v bit
1052 * be cleared before changing BAT values.
1053 *
1054 * Also, newer IBM firmware does not clear bat3 and 4 so
1055 * this makes sure it's done.
1056 * -- Cort
1057 */
1058 clear_bats:
1059 li r10,0
1060 mfspr r9,SPRN_PVR
1061 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1062 cmpwi r9, 1
1063 beq 1f
1064
1065 mtspr SPRN_DBAT0U,r10
1066 mtspr SPRN_DBAT0L,r10
1067 mtspr SPRN_DBAT1U,r10
1068 mtspr SPRN_DBAT1L,r10
1069 mtspr SPRN_DBAT2U,r10
1070 mtspr SPRN_DBAT2L,r10
1071 mtspr SPRN_DBAT3U,r10
1072 mtspr SPRN_DBAT3L,r10
1073 1:
1074 mtspr SPRN_IBAT0U,r10
1075 mtspr SPRN_IBAT0L,r10
1076 mtspr SPRN_IBAT1U,r10
1077 mtspr SPRN_IBAT1L,r10
1078 mtspr SPRN_IBAT2U,r10
1079 mtspr SPRN_IBAT2L,r10
1080 mtspr SPRN_IBAT3U,r10
1081 mtspr SPRN_IBAT3L,r10
1082 BEGIN_MMU_FTR_SECTION
1083 /* Here's a tweak: at this point, CPU setup have
1084 * not been called yet, so HIGH_BAT_EN may not be
1085 * set in HID0 for the 745x processors. However, it
1086 * seems that doesn't affect our ability to actually
1087 * write to these SPRs.
1088 */
1089 mtspr SPRN_DBAT4U,r10
1090 mtspr SPRN_DBAT4L,r10
1091 mtspr SPRN_DBAT5U,r10
1092 mtspr SPRN_DBAT5L,r10
1093 mtspr SPRN_DBAT6U,r10
1094 mtspr SPRN_DBAT6L,r10
1095 mtspr SPRN_DBAT7U,r10
1096 mtspr SPRN_DBAT7L,r10
1097 mtspr SPRN_IBAT4U,r10
1098 mtspr SPRN_IBAT4L,r10
1099 mtspr SPRN_IBAT5U,r10
1100 mtspr SPRN_IBAT5L,r10
1101 mtspr SPRN_IBAT6U,r10
1102 mtspr SPRN_IBAT6L,r10
1103 mtspr SPRN_IBAT7U,r10
1104 mtspr SPRN_IBAT7L,r10
1105 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1106 blr
1107
1108 flush_tlbs:
1109 lis r10, 0x40
1110 1: addic. r10, r10, -0x1000
1111 tlbie r10
1112 bgt 1b
1113 sync
1114 blr
1115
1116 mmu_off:
1117 addi r4, r3, __after_mmu_off - _start
1118 mfmsr r3
1119 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1120 beqlr
1121 andc r3,r3,r0
1122 mtspr SPRN_SRR0,r4
1123 mtspr SPRN_SRR1,r3
1124 sync
1125 RFI
1126
1127 /*
1128 * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET
1129 * (we keep one for debugging) and on others, we use one 256M BAT.
1130 */
1131 initial_bats:
1132 lis r11,PAGE_OFFSET@h
1133 mfspr r9,SPRN_PVR
1134 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1135 cmpwi 0,r9,1
1136 bne 4f
1137 ori r11,r11,4 /* set up BAT registers for 601 */
1138 li r8,0x7f /* valid, block length = 8MB */
1139 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1140 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1141 addis r11,r11,0x800000@h
1142 addis r8,r8,0x800000@h
1143 mtspr SPRN_IBAT1U,r11
1144 mtspr SPRN_IBAT1L,r8
1145 addis r11,r11,0x800000@h
1146 addis r8,r8,0x800000@h
1147 mtspr SPRN_IBAT2U,r11
1148 mtspr SPRN_IBAT2L,r8
1149 isync
1150 blr
1151
1152 4: tophys(r8,r11)
1153 #ifdef CONFIG_SMP
1154 ori r8,r8,0x12 /* R/W access, M=1 */
1155 #else
1156 ori r8,r8,2 /* R/W access */
1157 #endif /* CONFIG_SMP */
1158 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1159
1160 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1161 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1162 mtspr SPRN_IBAT0L,r8
1163 mtspr SPRN_IBAT0U,r11
1164 isync
1165 blr
1166
1167
1168 #ifdef CONFIG_BOOTX_TEXT
1169 setup_disp_bat:
1170 /*
1171 * setup the display bat prepared for us in prom.c
1172 */
1173 mflr r8
1174 bl reloc_offset
1175 mtlr r8
1176 addis r8,r3,disp_BAT@ha
1177 addi r8,r8,disp_BAT@l
1178 cmpwi cr0,r8,0
1179 beqlr
1180 lwz r11,0(r8)
1181 lwz r8,4(r8)
1182 mfspr r9,SPRN_PVR
1183 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1184 cmpwi 0,r9,1
1185 beq 1f
1186 mtspr SPRN_DBAT3L,r8
1187 mtspr SPRN_DBAT3U,r11
1188 blr
1189 1: mtspr SPRN_IBAT3L,r8
1190 mtspr SPRN_IBAT3U,r11
1191 blr
1192 #endif /* CONFIG_BOOTX_TEXT */
1193
1194 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1195 setup_cpm_bat:
1196 lis r8, 0xf000
1197 ori r8, r8, 0x002a
1198 mtspr SPRN_DBAT1L, r8
1199
1200 lis r11, 0xf000
1201 ori r11, r11, (BL_1M << 2) | 2
1202 mtspr SPRN_DBAT1U, r11
1203
1204 blr
1205 #endif
1206
1207 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
1208 setup_usbgecko_bat:
1209 /* prepare a BAT for early io */
1210 #if defined(CONFIG_GAMECUBE)
1211 lis r8, 0x0c00
1212 #elif defined(CONFIG_WII)
1213 lis r8, 0x0d00
1214 #else
1215 #error Invalid platform for USB Gecko based early debugging.
1216 #endif
1217 /*
1218 * The virtual address used must match the virtual address
1219 * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
1220 */
1221 lis r11, 0xfffe /* top 128K */
1222 ori r8, r8, 0x002a /* uncached, guarded ,rw */
1223 ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */
1224 mtspr SPRN_DBAT1L, r8
1225 mtspr SPRN_DBAT1U, r11
1226 blr
1227 #endif
1228
1229 #ifdef CONFIG_8260
1230 /* Jump into the system reset for the rom.
1231 * We first disable the MMU, and then jump to the ROM reset address.
1232 *
1233 * r3 is the board info structure, r4 is the location for starting.
1234 * I use this for building a small kernel that can load other kernels,
1235 * rather than trying to write or rely on a rom monitor that can tftp load.
1236 */
1237 .globl m8260_gorom
1238 m8260_gorom:
1239 mfmsr r0
1240 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1241 sync
1242 mtmsr r0
1243 sync
1244 mfspr r11, SPRN_HID0
1245 lis r10, 0
1246 ori r10,r10,HID0_ICE|HID0_DCE
1247 andc r11, r11, r10
1248 mtspr SPRN_HID0, r11
1249 isync
1250 li r5, MSR_ME|MSR_RI
1251 lis r6,2f@h
1252 addis r6,r6,-KERNELBASE@h
1253 ori r6,r6,2f@l
1254 mtspr SPRN_SRR0,r6
1255 mtspr SPRN_SRR1,r5
1256 isync
1257 sync
1258 rfi
1259 2:
1260 mtlr r4
1261 blr
1262 #endif
1263
1264
1265 /*
1266 * We put a few things here that have to be page-aligned.
1267 * This stuff goes at the beginning of the data segment,
1268 * which is page-aligned.
1269 */
1270 .data
1271 .globl sdata
1272 sdata:
1273 .globl empty_zero_page
1274 empty_zero_page:
1275 .space 4096
1276 EXPORT_SYMBOL(empty_zero_page)
1277
1278 .globl swapper_pg_dir
1279 swapper_pg_dir:
1280 .space PGD_TABLE_SIZE
1281
1282 /* Room for two PTE pointers, usually the kernel and current user pointers
1283 * to their respective root page table.
1284 */
1285 abatron_pteptrs:
1286 .space 8
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