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Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / kernel / head_32.S
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 *
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
23
24 #include <linux/init.h>
25 #include <asm/reg.h>
26 #include <asm/page.h>
27 #include <asm/mmu.h>
28 #include <asm/pgtable.h>
29 #include <asm/cputable.h>
30 #include <asm/cache.h>
31 #include <asm/thread_info.h>
32 #include <asm/ppc_asm.h>
33 #include <asm/asm-offsets.h>
34 #include <asm/ptrace.h>
35 #include <asm/bug.h>
36 #include <asm/kvm_book3s_asm.h>
37
38 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
39 #define LOAD_BAT(n, reg, RA, RB) \
40 /* see the comment for clear_bats() -- Cort */ \
41 li RA,0; \
42 mtspr SPRN_IBAT##n##U,RA; \
43 mtspr SPRN_DBAT##n##U,RA; \
44 lwz RA,(n*16)+0(reg); \
45 lwz RB,(n*16)+4(reg); \
46 mtspr SPRN_IBAT##n##U,RA; \
47 mtspr SPRN_IBAT##n##L,RB; \
48 beq 1f; \
49 lwz RA,(n*16)+8(reg); \
50 lwz RB,(n*16)+12(reg); \
51 mtspr SPRN_DBAT##n##U,RA; \
52 mtspr SPRN_DBAT##n##L,RB; \
53 1:
54
55 __HEAD
56 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
57 .stabs "head_32.S",N_SO,0,0,0f
58 0:
59 _ENTRY(_stext);
60
61 /*
62 * _start is defined this way because the XCOFF loader in the OpenFirmware
63 * on the powermac expects the entry point to be a procedure descriptor.
64 */
65 _ENTRY(_start);
66 /*
67 * These are here for legacy reasons, the kernel used to
68 * need to look like a coff function entry for the pmac
69 * but we're always started by some kind of bootloader now.
70 * -- Cort
71 */
72 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
73 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
74 nop
75
76 /* PMAC
77 * Enter here with the kernel text, data and bss loaded starting at
78 * 0, running with virtual == physical mapping.
79 * r5 points to the prom entry point (the client interface handler
80 * address). Address translation is turned on, with the prom
81 * managing the hash table. Interrupts are disabled. The stack
82 * pointer (r1) points to just below the end of the half-meg region
83 * from 0x380000 - 0x400000, which is mapped in already.
84 *
85 * If we are booted from MacOS via BootX, we enter with the kernel
86 * image loaded somewhere, and the following values in registers:
87 * r3: 'BooX' (0x426f6f58)
88 * r4: virtual address of boot_infos_t
89 * r5: 0
90 *
91 * PREP
92 * This is jumped to on prep systems right after the kernel is relocated
93 * to its proper place in memory by the boot loader. The expected layout
94 * of the regs is:
95 * r3: ptr to residual data
96 * r4: initrd_start or if no initrd then 0
97 * r5: initrd_end - unused if r4 is 0
98 * r6: Start of command line string
99 * r7: End of command line string
100 *
101 * This just gets a minimal mmu environment setup so we can call
102 * start_here() to do the real work.
103 * -- Cort
104 */
105
106 .globl __start
107 __start:
108 /*
109 * We have to do any OF calls before we map ourselves to KERNELBASE,
110 * because OF may have I/O devices mapped into that area
111 * (particularly on CHRP).
112 */
113 cmpwi 0,r5,0
114 beq 1f
115
116 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
117 /* find out where we are now */
118 bcl 20,31,$+4
119 0: mflr r8 /* r8 = runtime addr here */
120 addis r8,r8,(_stext - 0b)@ha
121 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
122 bl prom_init
123 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
124
125 /* We never return. We also hit that trap if trying to boot
126 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
127 trap
128
129 /*
130 * Check for BootX signature when supporting PowerMac and branch to
131 * appropriate trampoline if it's present
132 */
133 #ifdef CONFIG_PPC_PMAC
134 1: lis r31,0x426f
135 ori r31,r31,0x6f58
136 cmpw 0,r3,r31
137 bne 1f
138 bl bootx_init
139 trap
140 #endif /* CONFIG_PPC_PMAC */
141
142 1: mr r31,r3 /* save device tree ptr */
143 li r24,0 /* cpu # */
144
145 /*
146 * early_init() does the early machine identification and does
147 * the necessary low-level setup and clears the BSS
148 * -- Cort <cort@fsmlabs.com>
149 */
150 bl early_init
151
152 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
153 * the physical address we are running at, returned by early_init()
154 */
155 bl mmu_off
156 __after_mmu_off:
157 bl clear_bats
158 bl flush_tlbs
159
160 bl initial_bats
161 #if defined(CONFIG_BOOTX_TEXT)
162 bl setup_disp_bat
163 #endif
164 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
165 bl setup_cpm_bat
166 #endif
167 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
168 bl setup_usbgecko_bat
169 #endif
170
171 /*
172 * Call setup_cpu for CPU 0 and initialize 6xx Idle
173 */
174 bl reloc_offset
175 li r24,0 /* cpu# */
176 bl call_setup_cpu /* Call setup_cpu for this CPU */
177 #ifdef CONFIG_6xx
178 bl reloc_offset
179 bl init_idle_6xx
180 #endif /* CONFIG_6xx */
181
182
183 /*
184 * We need to run with _start at physical address 0.
185 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
186 * the exception vectors at 0 (and therefore this copy
187 * overwrites OF's exception vectors with our own).
188 * The MMU is off at this point.
189 */
190 bl reloc_offset
191 mr r26,r3
192 addis r4,r3,KERNELBASE@h /* current address of _start */
193 lis r5,PHYSICAL_START@h
194 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
195 bne relocate_kernel
196 /*
197 * we now have the 1st 16M of ram mapped with the bats.
198 * prep needs the mmu to be turned on here, but pmac already has it on.
199 * this shouldn't bother the pmac since it just gets turned on again
200 * as we jump to our code at KERNELBASE. -- Cort
201 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
202 * off, and in other cases, we now turn it off before changing BATs above.
203 */
204 turn_on_mmu:
205 mfmsr r0
206 ori r0,r0,MSR_DR|MSR_IR
207 mtspr SPRN_SRR1,r0
208 lis r0,start_here@h
209 ori r0,r0,start_here@l
210 mtspr SPRN_SRR0,r0
211 SYNC
212 RFI /* enables MMU */
213
214 /*
215 * We need __secondary_hold as a place to hold the other cpus on
216 * an SMP machine, even when we are running a UP kernel.
217 */
218 . = 0xc0 /* for prep bootloader */
219 li r3,1 /* MTX only has 1 cpu */
220 .globl __secondary_hold
221 __secondary_hold:
222 /* tell the master we're here */
223 stw r3,__secondary_hold_acknowledge@l(0)
224 #ifdef CONFIG_SMP
225 100: lwz r4,0(0)
226 /* wait until we're told to start */
227 cmpw 0,r4,r3
228 bne 100b
229 /* our cpu # was at addr 0 - go */
230 mr r24,r3 /* cpu # */
231 b __secondary_start
232 #else
233 b .
234 #endif /* CONFIG_SMP */
235
236 .globl __secondary_hold_spinloop
237 __secondary_hold_spinloop:
238 .long 0
239 .globl __secondary_hold_acknowledge
240 __secondary_hold_acknowledge:
241 .long -1
242
243 /*
244 * Exception entry code. This code runs with address translation
245 * turned off, i.e. using physical addresses.
246 * We assume sprg3 has the physical address of the current
247 * task's thread_struct.
248 */
249 #define EXCEPTION_PROLOG \
250 mtspr SPRN_SPRG_SCRATCH0,r10; \
251 mtspr SPRN_SPRG_SCRATCH1,r11; \
252 mfcr r10; \
253 EXCEPTION_PROLOG_1; \
254 EXCEPTION_PROLOG_2
255
256 #define EXCEPTION_PROLOG_1 \
257 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
258 andi. r11,r11,MSR_PR; \
259 tophys(r11,r1); /* use tophys(r1) if kernel */ \
260 beq 1f; \
261 mfspr r11,SPRN_SPRG_THREAD; \
262 lwz r11,THREAD_INFO-THREAD(r11); \
263 addi r11,r11,THREAD_SIZE; \
264 tophys(r11,r11); \
265 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
266
267
268 #define EXCEPTION_PROLOG_2 \
269 stw r10,_CCR(r11); /* save registers */ \
270 stw r12,GPR12(r11); \
271 stw r9,GPR9(r11); \
272 mfspr r10,SPRN_SPRG_SCRATCH0; \
273 stw r10,GPR10(r11); \
274 mfspr r12,SPRN_SPRG_SCRATCH1; \
275 stw r12,GPR11(r11); \
276 mflr r10; \
277 stw r10,_LINK(r11); \
278 mfspr r12,SPRN_SRR0; \
279 mfspr r9,SPRN_SRR1; \
280 stw r1,GPR1(r11); \
281 stw r1,0(r11); \
282 tovirt(r1,r11); /* set new kernel sp */ \
283 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
284 MTMSRD(r10); /* (except for mach check in rtas) */ \
285 stw r0,GPR0(r11); \
286 lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
287 addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
288 stw r10,8(r11); \
289 SAVE_4GPRS(3, r11); \
290 SAVE_2GPRS(7, r11)
291
292 /*
293 * Note: code which follows this uses cr0.eq (set if from kernel),
294 * r11, r12 (SRR0), and r9 (SRR1).
295 *
296 * Note2: once we have set r1 we are in a position to take exceptions
297 * again, and we could thus set MSR:RI at that point.
298 */
299
300 /*
301 * Exception vectors.
302 */
303 #define EXCEPTION(n, label, hdlr, xfer) \
304 . = n; \
305 DO_KVM n; \
306 label: \
307 EXCEPTION_PROLOG; \
308 addi r3,r1,STACK_FRAME_OVERHEAD; \
309 xfer(n, hdlr)
310
311 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
312 li r10,trap; \
313 stw r10,_TRAP(r11); \
314 li r10,MSR_KERNEL; \
315 copyee(r10, r9); \
316 bl tfer; \
317 i##n: \
318 .long hdlr; \
319 .long ret
320
321 #define COPY_EE(d, s) rlwimi d,s,0,16,16
322 #define NOCOPY(d, s)
323
324 #define EXC_XFER_STD(n, hdlr) \
325 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
326 ret_from_except_full)
327
328 #define EXC_XFER_LITE(n, hdlr) \
329 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
330 ret_from_except)
331
332 #define EXC_XFER_EE(n, hdlr) \
333 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
334 ret_from_except_full)
335
336 #define EXC_XFER_EE_LITE(n, hdlr) \
337 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
338 ret_from_except)
339
340 /* System reset */
341 /* core99 pmac starts the seconary here by changing the vector, and
342 putting it back to what it was (unknown_exception) when done. */
343 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
344
345 /* Machine check */
346 /*
347 * On CHRP, this is complicated by the fact that we could get a
348 * machine check inside RTAS, and we have no guarantee that certain
349 * critical registers will have the values we expect. The set of
350 * registers that might have bad values includes all the GPRs
351 * and all the BATs. We indicate that we are in RTAS by putting
352 * a non-zero value, the address of the exception frame to use,
353 * in SPRG2. The machine check handler checks SPRG2 and uses its
354 * value if it is non-zero. If we ever needed to free up SPRG2,
355 * we could use a field in the thread_info or thread_struct instead.
356 * (Other exception handlers assume that r1 is a valid kernel stack
357 * pointer when we take an exception from supervisor mode.)
358 * -- paulus.
359 */
360 . = 0x200
361 DO_KVM 0x200
362 mtspr SPRN_SPRG_SCRATCH0,r10
363 mtspr SPRN_SPRG_SCRATCH1,r11
364 mfcr r10
365 #ifdef CONFIG_PPC_CHRP
366 mfspr r11,SPRN_SPRG_RTAS
367 cmpwi 0,r11,0
368 bne 7f
369 #endif /* CONFIG_PPC_CHRP */
370 EXCEPTION_PROLOG_1
371 7: EXCEPTION_PROLOG_2
372 addi r3,r1,STACK_FRAME_OVERHEAD
373 #ifdef CONFIG_PPC_CHRP
374 mfspr r4,SPRN_SPRG_RTAS
375 cmpwi cr1,r4,0
376 bne cr1,1f
377 #endif
378 EXC_XFER_STD(0x200, machine_check_exception)
379 #ifdef CONFIG_PPC_CHRP
380 1: b machine_check_in_rtas
381 #endif
382
383 /* Data access exception. */
384 . = 0x300
385 DO_KVM 0x300
386 DataAccess:
387 EXCEPTION_PROLOG
388 mfspr r10,SPRN_DSISR
389 stw r10,_DSISR(r11)
390 andis. r0,r10,0xa470 /* weird error? */
391 bne 1f /* if not, try to put a PTE */
392 mfspr r4,SPRN_DAR /* into the hash table */
393 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
394 bl hash_page
395 1: lwz r5,_DSISR(r11) /* get DSISR value */
396 mfspr r4,SPRN_DAR
397 EXC_XFER_LITE(0x300, handle_page_fault)
398
399
400 /* Instruction access exception. */
401 . = 0x400
402 DO_KVM 0x400
403 InstructionAccess:
404 EXCEPTION_PROLOG
405 andis. r0,r9,0x4000 /* no pte found? */
406 beq 1f /* if so, try to put a PTE */
407 li r3,0 /* into the hash table */
408 mr r4,r12 /* SRR0 is fault address */
409 bl hash_page
410 1: mr r4,r12
411 mr r5,r9
412 EXC_XFER_LITE(0x400, handle_page_fault)
413
414 /* External interrupt */
415 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
416
417 /* Alignment exception */
418 . = 0x600
419 DO_KVM 0x600
420 Alignment:
421 EXCEPTION_PROLOG
422 mfspr r4,SPRN_DAR
423 stw r4,_DAR(r11)
424 mfspr r5,SPRN_DSISR
425 stw r5,_DSISR(r11)
426 addi r3,r1,STACK_FRAME_OVERHEAD
427 EXC_XFER_EE(0x600, alignment_exception)
428
429 /* Program check exception */
430 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
431
432 /* Floating-point unavailable */
433 . = 0x800
434 DO_KVM 0x800
435 FPUnavailable:
436 BEGIN_FTR_SECTION
437 /*
438 * Certain Freescale cores don't have a FPU and treat fp instructions
439 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
440 */
441 b ProgramCheck
442 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
443 EXCEPTION_PROLOG
444 beq 1f
445 bl load_up_fpu /* if from user, just load it up */
446 b fast_exception_return
447 1: addi r3,r1,STACK_FRAME_OVERHEAD
448 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
449
450 /* Decrementer */
451 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
452
453 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
454 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
455
456 /* System call */
457 . = 0xc00
458 DO_KVM 0xc00
459 SystemCall:
460 EXCEPTION_PROLOG
461 EXC_XFER_EE_LITE(0xc00, DoSyscall)
462
463 /* Single step - not used on 601 */
464 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
465 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
466
467 /*
468 * The Altivec unavailable trap is at 0x0f20. Foo.
469 * We effectively remap it to 0x3000.
470 * We include an altivec unavailable exception vector even if
471 * not configured for Altivec, so that you can't panic a
472 * non-altivec kernel running on a machine with altivec just
473 * by executing an altivec instruction.
474 */
475 . = 0xf00
476 DO_KVM 0xf00
477 b PerformanceMonitor
478
479 . = 0xf20
480 DO_KVM 0xf20
481 b AltiVecUnavailable
482
483 /*
484 * Handle TLB miss for instruction on 603/603e.
485 * Note: we get an alternate set of r0 - r3 to use automatically.
486 */
487 . = 0x1000
488 InstructionTLBMiss:
489 /*
490 * r0: scratch
491 * r1: linux style pte ( later becomes ppc hardware pte )
492 * r2: ptr to linux-style pte
493 * r3: scratch
494 */
495 /* Get PTE (linux-style) and check access */
496 mfspr r3,SPRN_IMISS
497 lis r1,PAGE_OFFSET@h /* check if kernel address */
498 cmplw 0,r1,r3
499 mfspr r2,SPRN_SPRG_THREAD
500 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
501 lwz r2,PGDIR(r2)
502 bge- 112f
503 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
504 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
505 lis r2,swapper_pg_dir@ha /* if kernel address, use */
506 addi r2,r2,swapper_pg_dir@l /* kernel page table */
507 112: tophys(r2,r2)
508 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
509 lwz r2,0(r2) /* get pmd entry */
510 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
511 beq- InstructionAddressInvalid /* return if no mapping */
512 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
513 lwz r0,0(r2) /* get linux-style pte */
514 andc. r1,r1,r0 /* check access & ~permission */
515 bne- InstructionAddressInvalid /* return if access not permitted */
516 ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
517 /*
518 * NOTE! We are assuming this is not an SMP system, otherwise
519 * we would need to update the pte atomically with lwarx/stwcx.
520 */
521 stw r0,0(r2) /* update PTE (accessed bit) */
522 /* Convert linux-style PTE to low word of PPC-style PTE */
523 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
524 rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
525 and r1,r1,r2 /* writable if _RW and _DIRTY */
526 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
527 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
528 ori r1,r1,0xe04 /* clear out reserved bits */
529 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
530 BEGIN_FTR_SECTION
531 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
532 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
533 mtspr SPRN_RPA,r1
534 tlbli r3
535 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
536 mtcrf 0x80,r3
537 rfi
538 InstructionAddressInvalid:
539 mfspr r3,SPRN_SRR1
540 rlwinm r1,r3,9,6,6 /* Get load/store bit */
541
542 addis r1,r1,0x2000
543 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
544 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
545 or r2,r2,r1
546 mtspr SPRN_SRR1,r2
547 mfspr r1,SPRN_IMISS /* Get failing address */
548 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
549 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
550 xor r1,r1,r2
551 mtspr SPRN_DAR,r1 /* Set fault address */
552 mfmsr r0 /* Restore "normal" registers */
553 xoris r0,r0,MSR_TGPR>>16
554 mtcrf 0x80,r3 /* Restore CR0 */
555 mtmsr r0
556 b InstructionAccess
557
558 /*
559 * Handle TLB miss for DATA Load operation on 603/603e
560 */
561 . = 0x1100
562 DataLoadTLBMiss:
563 /*
564 * r0: scratch
565 * r1: linux style pte ( later becomes ppc hardware pte )
566 * r2: ptr to linux-style pte
567 * r3: scratch
568 */
569 /* Get PTE (linux-style) and check access */
570 mfspr r3,SPRN_DMISS
571 lis r1,PAGE_OFFSET@h /* check if kernel address */
572 cmplw 0,r1,r3
573 mfspr r2,SPRN_SPRG_THREAD
574 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
575 lwz r2,PGDIR(r2)
576 bge- 112f
577 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
578 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
579 lis r2,swapper_pg_dir@ha /* if kernel address, use */
580 addi r2,r2,swapper_pg_dir@l /* kernel page table */
581 112: tophys(r2,r2)
582 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
583 lwz r2,0(r2) /* get pmd entry */
584 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
585 beq- DataAddressInvalid /* return if no mapping */
586 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
587 lwz r0,0(r2) /* get linux-style pte */
588 andc. r1,r1,r0 /* check access & ~permission */
589 bne- DataAddressInvalid /* return if access not permitted */
590 ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
591 /*
592 * NOTE! We are assuming this is not an SMP system, otherwise
593 * we would need to update the pte atomically with lwarx/stwcx.
594 */
595 stw r0,0(r2) /* update PTE (accessed bit) */
596 /* Convert linux-style PTE to low word of PPC-style PTE */
597 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
598 rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
599 and r1,r1,r2 /* writable if _RW and _DIRTY */
600 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
601 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
602 ori r1,r1,0xe04 /* clear out reserved bits */
603 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
604 BEGIN_FTR_SECTION
605 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
606 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
607 mtspr SPRN_RPA,r1
608 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
609 mtcrf 0x80,r2
610 BEGIN_MMU_FTR_SECTION
611 li r0,1
612 mfspr r1,SPRN_SPRG_603_LRU
613 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
614 slw r0,r0,r2
615 xor r1,r0,r1
616 srw r0,r1,r2
617 mtspr SPRN_SPRG_603_LRU,r1
618 mfspr r2,SPRN_SRR1
619 rlwimi r2,r0,31-14,14,14
620 mtspr SPRN_SRR1,r2
621 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
622 tlbld r3
623 rfi
624 DataAddressInvalid:
625 mfspr r3,SPRN_SRR1
626 rlwinm r1,r3,9,6,6 /* Get load/store bit */
627 addis r1,r1,0x2000
628 mtspr SPRN_DSISR,r1
629 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
630 mtspr SPRN_SRR1,r2
631 mfspr r1,SPRN_DMISS /* Get failing address */
632 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
633 beq 20f /* Jump if big endian */
634 xori r1,r1,3
635 20: mtspr SPRN_DAR,r1 /* Set fault address */
636 mfmsr r0 /* Restore "normal" registers */
637 xoris r0,r0,MSR_TGPR>>16
638 mtcrf 0x80,r3 /* Restore CR0 */
639 mtmsr r0
640 b DataAccess
641
642 /*
643 * Handle TLB miss for DATA Store on 603/603e
644 */
645 . = 0x1200
646 DataStoreTLBMiss:
647 /*
648 * r0: scratch
649 * r1: linux style pte ( later becomes ppc hardware pte )
650 * r2: ptr to linux-style pte
651 * r3: scratch
652 */
653 /* Get PTE (linux-style) and check access */
654 mfspr r3,SPRN_DMISS
655 lis r1,PAGE_OFFSET@h /* check if kernel address */
656 cmplw 0,r1,r3
657 mfspr r2,SPRN_SPRG_THREAD
658 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
659 lwz r2,PGDIR(r2)
660 bge- 112f
661 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
662 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
663 lis r2,swapper_pg_dir@ha /* if kernel address, use */
664 addi r2,r2,swapper_pg_dir@l /* kernel page table */
665 112: tophys(r2,r2)
666 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
667 lwz r2,0(r2) /* get pmd entry */
668 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
669 beq- DataAddressInvalid /* return if no mapping */
670 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
671 lwz r0,0(r2) /* get linux-style pte */
672 andc. r1,r1,r0 /* check access & ~permission */
673 bne- DataAddressInvalid /* return if access not permitted */
674 ori r0,r0,_PAGE_ACCESSED|_PAGE_DIRTY
675 /*
676 * NOTE! We are assuming this is not an SMP system, otherwise
677 * we would need to update the pte atomically with lwarx/stwcx.
678 */
679 stw r0,0(r2) /* update PTE (accessed/dirty bits) */
680 /* Convert linux-style PTE to low word of PPC-style PTE */
681 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
682 li r1,0xe05 /* clear out reserved bits & PP lsb */
683 andc r1,r0,r1 /* PP = user? 2: 0 */
684 BEGIN_FTR_SECTION
685 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
686 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
687 mtspr SPRN_RPA,r1
688 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
689 mtcrf 0x80,r2
690 BEGIN_MMU_FTR_SECTION
691 li r0,1
692 mfspr r1,SPRN_SPRG_603_LRU
693 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
694 slw r0,r0,r2
695 xor r1,r0,r1
696 srw r0,r1,r2
697 mtspr SPRN_SPRG_603_LRU,r1
698 mfspr r2,SPRN_SRR1
699 rlwimi r2,r0,31-14,14,14
700 mtspr SPRN_SRR1,r2
701 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
702 tlbld r3
703 rfi
704
705 #ifndef CONFIG_ALTIVEC
706 #define altivec_assist_exception unknown_exception
707 #endif
708
709 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
710 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
711 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
712 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
713 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
714 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
715 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
716 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
717 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
718 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
719 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
720 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
721 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
722 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
723 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
724 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
725 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
726 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
727 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
728 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
729 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
730 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
731 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
732 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
733 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
734 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
735 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
736 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
737 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
738
739 .globl mol_trampoline
740 .set mol_trampoline, i0x2f00
741
742 . = 0x3000
743
744 AltiVecUnavailable:
745 EXCEPTION_PROLOG
746 #ifdef CONFIG_ALTIVEC
747 beq 1f
748 bl load_up_altivec /* if from user, just load it up */
749 b fast_exception_return
750 #endif /* CONFIG_ALTIVEC */
751 1: addi r3,r1,STACK_FRAME_OVERHEAD
752 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
753
754 PerformanceMonitor:
755 EXCEPTION_PROLOG
756 addi r3,r1,STACK_FRAME_OVERHEAD
757 EXC_XFER_STD(0xf00, performance_monitor_exception)
758
759
760 /*
761 * This code is jumped to from the startup code to copy
762 * the kernel image to physical address PHYSICAL_START.
763 */
764 relocate_kernel:
765 addis r9,r26,klimit@ha /* fetch klimit */
766 lwz r25,klimit@l(r9)
767 addis r25,r25,-KERNELBASE@h
768 lis r3,PHYSICAL_START@h /* Destination base address */
769 li r6,0 /* Destination offset */
770 li r5,0x4000 /* # bytes of memory to copy */
771 bl copy_and_flush /* copy the first 0x4000 bytes */
772 addi r0,r3,4f@l /* jump to the address of 4f */
773 mtctr r0 /* in copy and do the rest. */
774 bctr /* jump to the copy */
775 4: mr r5,r25
776 bl copy_and_flush /* copy the rest */
777 b turn_on_mmu
778
779 /*
780 * Copy routine used to copy the kernel to start at physical address 0
781 * and flush and invalidate the caches as needed.
782 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
783 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
784 */
785 _ENTRY(copy_and_flush)
786 addi r5,r5,-4
787 addi r6,r6,-4
788 4: li r0,L1_CACHE_BYTES/4
789 mtctr r0
790 3: addi r6,r6,4 /* copy a cache line */
791 lwzx r0,r6,r4
792 stwx r0,r6,r3
793 bdnz 3b
794 dcbst r6,r3 /* write it to memory */
795 sync
796 icbi r6,r3 /* flush the icache line */
797 cmplw 0,r6,r5
798 blt 4b
799 sync /* additional sync needed on g4 */
800 isync
801 addi r5,r5,4
802 addi r6,r6,4
803 blr
804
805 #ifdef CONFIG_SMP
806 .globl __secondary_start_mpc86xx
807 __secondary_start_mpc86xx:
808 mfspr r3, SPRN_PIR
809 stw r3, __secondary_hold_acknowledge@l(0)
810 mr r24, r3 /* cpu # */
811 b __secondary_start
812
813 .globl __secondary_start_pmac_0
814 __secondary_start_pmac_0:
815 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
816 li r24,0
817 b 1f
818 li r24,1
819 b 1f
820 li r24,2
821 b 1f
822 li r24,3
823 1:
824 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
825 set to map the 0xf0000000 - 0xffffffff region */
826 mfmsr r0
827 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
828 SYNC
829 mtmsr r0
830 isync
831
832 .globl __secondary_start
833 __secondary_start:
834 /* Copy some CPU settings from CPU 0 */
835 bl __restore_cpu_setup
836
837 lis r3,-KERNELBASE@h
838 mr r4,r24
839 bl call_setup_cpu /* Call setup_cpu for this CPU */
840 #ifdef CONFIG_6xx
841 lis r3,-KERNELBASE@h
842 bl init_idle_6xx
843 #endif /* CONFIG_6xx */
844
845 /* get current_thread_info and current */
846 lis r1,secondary_ti@ha
847 tophys(r1,r1)
848 lwz r1,secondary_ti@l(r1)
849 tophys(r2,r1)
850 lwz r2,TI_TASK(r2)
851
852 /* stack */
853 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
854 li r0,0
855 tophys(r3,r1)
856 stw r0,0(r3)
857
858 /* load up the MMU */
859 bl load_up_mmu
860
861 /* ptr to phys current thread */
862 tophys(r4,r2)
863 addi r4,r4,THREAD /* phys address of our thread_struct */
864 mtspr SPRN_SPRG_THREAD,r4
865 li r3,0
866 mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
867
868 /* enable MMU and jump to start_secondary */
869 li r4,MSR_KERNEL
870 FIX_SRR1(r4,r5)
871 lis r3,start_secondary@h
872 ori r3,r3,start_secondary@l
873 mtspr SPRN_SRR0,r3
874 mtspr SPRN_SRR1,r4
875 SYNC
876 RFI
877 #endif /* CONFIG_SMP */
878
879 #ifdef CONFIG_KVM_BOOK3S_HANDLER
880 #include "../kvm/book3s_rmhandlers.S"
881 #endif
882
883 /*
884 * Those generic dummy functions are kept for CPUs not
885 * included in CONFIG_6xx
886 */
887 #if !defined(CONFIG_6xx)
888 _ENTRY(__save_cpu_setup)
889 blr
890 _ENTRY(__restore_cpu_setup)
891 blr
892 #endif /* !defined(CONFIG_6xx) */
893
894
895 /*
896 * Load stuff into the MMU. Intended to be called with
897 * IR=0 and DR=0.
898 */
899 load_up_mmu:
900 sync /* Force all PTE updates to finish */
901 isync
902 tlbia /* Clear all TLB entries */
903 sync /* wait for tlbia/tlbie to finish */
904 TLBSYNC /* ... on all CPUs */
905 /* Load the SDR1 register (hash table base & size) */
906 lis r6,_SDR1@ha
907 tophys(r6,r6)
908 lwz r6,_SDR1@l(r6)
909 mtspr SPRN_SDR1,r6
910 li r0,16 /* load up segment register values */
911 mtctr r0 /* for context 0 */
912 lis r3,0x2000 /* Ku = 1, VSID = 0 */
913 li r4,0
914 3: mtsrin r3,r4
915 addi r3,r3,0x111 /* increment VSID */
916 addis r4,r4,0x1000 /* address of next segment */
917 bdnz 3b
918
919 /* Load the BAT registers with the values set up by MMU_init.
920 MMU_init takes care of whether we're on a 601 or not. */
921 mfpvr r3
922 srwi r3,r3,16
923 cmpwi r3,1
924 lis r3,BATS@ha
925 addi r3,r3,BATS@l
926 tophys(r3,r3)
927 LOAD_BAT(0,r3,r4,r5)
928 LOAD_BAT(1,r3,r4,r5)
929 LOAD_BAT(2,r3,r4,r5)
930 LOAD_BAT(3,r3,r4,r5)
931 BEGIN_MMU_FTR_SECTION
932 LOAD_BAT(4,r3,r4,r5)
933 LOAD_BAT(5,r3,r4,r5)
934 LOAD_BAT(6,r3,r4,r5)
935 LOAD_BAT(7,r3,r4,r5)
936 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
937 blr
938
939 /*
940 * This is where the main kernel code starts.
941 */
942 start_here:
943 /* ptr to current */
944 lis r2,init_task@h
945 ori r2,r2,init_task@l
946 /* Set up for using our exception vectors */
947 /* ptr to phys current thread */
948 tophys(r4,r2)
949 addi r4,r4,THREAD /* init task's THREAD */
950 mtspr SPRN_SPRG_THREAD,r4
951 li r3,0
952 mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
953
954 /* stack */
955 lis r1,init_thread_union@ha
956 addi r1,r1,init_thread_union@l
957 li r0,0
958 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
959 /*
960 * Do early platform-specific initialization,
961 * and set up the MMU.
962 */
963 li r3,0
964 mr r4,r31
965 bl machine_init
966 bl __save_cpu_setup
967 bl MMU_init
968
969 /*
970 * Go back to running unmapped so we can load up new values
971 * for SDR1 (hash table pointer) and the segment registers
972 * and change to using our exception vectors.
973 */
974 lis r4,2f@h
975 ori r4,r4,2f@l
976 tophys(r4,r4)
977 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
978 FIX_SRR1(r3,r5)
979 mtspr SPRN_SRR0,r4
980 mtspr SPRN_SRR1,r3
981 SYNC
982 RFI
983 /* Load up the kernel context */
984 2: bl load_up_mmu
985
986 #ifdef CONFIG_BDI_SWITCH
987 /* Add helper information for the Abatron bdiGDB debugger.
988 * We do this here because we know the mmu is disabled, and
989 * will be enabled for real in just a few instructions.
990 */
991 lis r5, abatron_pteptrs@h
992 ori r5, r5, abatron_pteptrs@l
993 stw r5, 0xf0(r0) /* This much match your Abatron config */
994 lis r6, swapper_pg_dir@h
995 ori r6, r6, swapper_pg_dir@l
996 tophys(r5, r5)
997 stw r6, 0(r5)
998 #endif /* CONFIG_BDI_SWITCH */
999
1000 /* Now turn on the MMU for real! */
1001 li r4,MSR_KERNEL
1002 FIX_SRR1(r4,r5)
1003 lis r3,start_kernel@h
1004 ori r3,r3,start_kernel@l
1005 mtspr SPRN_SRR0,r3
1006 mtspr SPRN_SRR1,r4
1007 SYNC
1008 RFI
1009
1010 /*
1011 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1012 *
1013 * Set up the segment registers for a new context.
1014 */
1015 _ENTRY(switch_mmu_context)
1016 lwz r3,MMCONTEXTID(r4)
1017 cmpwi cr0,r3,0
1018 blt- 4f
1019 mulli r3,r3,897 /* multiply context by skew factor */
1020 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1021 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1022 li r0,NUM_USER_SEGMENTS
1023 mtctr r0
1024
1025 #ifdef CONFIG_BDI_SWITCH
1026 /* Context switch the PTE pointer for the Abatron BDI2000.
1027 * The PGDIR is passed as second argument.
1028 */
1029 lwz r4,MM_PGD(r4)
1030 lis r5, KERNELBASE@h
1031 lwz r5, 0xf0(r5)
1032 stw r4, 0x4(r5)
1033 #endif
1034 li r4,0
1035 isync
1036 3:
1037 mtsrin r3,r4
1038 addi r3,r3,0x111 /* next VSID */
1039 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1040 addis r4,r4,0x1000 /* address of next segment */
1041 bdnz 3b
1042 sync
1043 isync
1044 blr
1045 4: trap
1046 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1047 blr
1048
1049 /*
1050 * An undocumented "feature" of 604e requires that the v bit
1051 * be cleared before changing BAT values.
1052 *
1053 * Also, newer IBM firmware does not clear bat3 and 4 so
1054 * this makes sure it's done.
1055 * -- Cort
1056 */
1057 clear_bats:
1058 li r10,0
1059 mfspr r9,SPRN_PVR
1060 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1061 cmpwi r9, 1
1062 beq 1f
1063
1064 mtspr SPRN_DBAT0U,r10
1065 mtspr SPRN_DBAT0L,r10
1066 mtspr SPRN_DBAT1U,r10
1067 mtspr SPRN_DBAT1L,r10
1068 mtspr SPRN_DBAT2U,r10
1069 mtspr SPRN_DBAT2L,r10
1070 mtspr SPRN_DBAT3U,r10
1071 mtspr SPRN_DBAT3L,r10
1072 1:
1073 mtspr SPRN_IBAT0U,r10
1074 mtspr SPRN_IBAT0L,r10
1075 mtspr SPRN_IBAT1U,r10
1076 mtspr SPRN_IBAT1L,r10
1077 mtspr SPRN_IBAT2U,r10
1078 mtspr SPRN_IBAT2L,r10
1079 mtspr SPRN_IBAT3U,r10
1080 mtspr SPRN_IBAT3L,r10
1081 BEGIN_MMU_FTR_SECTION
1082 /* Here's a tweak: at this point, CPU setup have
1083 * not been called yet, so HIGH_BAT_EN may not be
1084 * set in HID0 for the 745x processors. However, it
1085 * seems that doesn't affect our ability to actually
1086 * write to these SPRs.
1087 */
1088 mtspr SPRN_DBAT4U,r10
1089 mtspr SPRN_DBAT4L,r10
1090 mtspr SPRN_DBAT5U,r10
1091 mtspr SPRN_DBAT5L,r10
1092 mtspr SPRN_DBAT6U,r10
1093 mtspr SPRN_DBAT6L,r10
1094 mtspr SPRN_DBAT7U,r10
1095 mtspr SPRN_DBAT7L,r10
1096 mtspr SPRN_IBAT4U,r10
1097 mtspr SPRN_IBAT4L,r10
1098 mtspr SPRN_IBAT5U,r10
1099 mtspr SPRN_IBAT5L,r10
1100 mtspr SPRN_IBAT6U,r10
1101 mtspr SPRN_IBAT6L,r10
1102 mtspr SPRN_IBAT7U,r10
1103 mtspr SPRN_IBAT7L,r10
1104 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1105 blr
1106
1107 flush_tlbs:
1108 lis r10, 0x40
1109 1: addic. r10, r10, -0x1000
1110 tlbie r10
1111 bgt 1b
1112 sync
1113 blr
1114
1115 mmu_off:
1116 addi r4, r3, __after_mmu_off - _start
1117 mfmsr r3
1118 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1119 beqlr
1120 andc r3,r3,r0
1121 mtspr SPRN_SRR0,r4
1122 mtspr SPRN_SRR1,r3
1123 sync
1124 RFI
1125
1126 /*
1127 * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET
1128 * (we keep one for debugging) and on others, we use one 256M BAT.
1129 */
1130 initial_bats:
1131 lis r11,PAGE_OFFSET@h
1132 mfspr r9,SPRN_PVR
1133 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1134 cmpwi 0,r9,1
1135 bne 4f
1136 ori r11,r11,4 /* set up BAT registers for 601 */
1137 li r8,0x7f /* valid, block length = 8MB */
1138 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1139 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1140 addis r11,r11,0x800000@h
1141 addis r8,r8,0x800000@h
1142 mtspr SPRN_IBAT1U,r11
1143 mtspr SPRN_IBAT1L,r8
1144 addis r11,r11,0x800000@h
1145 addis r8,r8,0x800000@h
1146 mtspr SPRN_IBAT2U,r11
1147 mtspr SPRN_IBAT2L,r8
1148 isync
1149 blr
1150
1151 4: tophys(r8,r11)
1152 #ifdef CONFIG_SMP
1153 ori r8,r8,0x12 /* R/W access, M=1 */
1154 #else
1155 ori r8,r8,2 /* R/W access */
1156 #endif /* CONFIG_SMP */
1157 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1158
1159 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1160 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1161 mtspr SPRN_IBAT0L,r8
1162 mtspr SPRN_IBAT0U,r11
1163 isync
1164 blr
1165
1166
1167 #ifdef CONFIG_BOOTX_TEXT
1168 setup_disp_bat:
1169 /*
1170 * setup the display bat prepared for us in prom.c
1171 */
1172 mflr r8
1173 bl reloc_offset
1174 mtlr r8
1175 addis r8,r3,disp_BAT@ha
1176 addi r8,r8,disp_BAT@l
1177 cmpwi cr0,r8,0
1178 beqlr
1179 lwz r11,0(r8)
1180 lwz r8,4(r8)
1181 mfspr r9,SPRN_PVR
1182 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1183 cmpwi 0,r9,1
1184 beq 1f
1185 mtspr SPRN_DBAT3L,r8
1186 mtspr SPRN_DBAT3U,r11
1187 blr
1188 1: mtspr SPRN_IBAT3L,r8
1189 mtspr SPRN_IBAT3U,r11
1190 blr
1191 #endif /* CONFIG_BOOTX_TEXT */
1192
1193 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1194 setup_cpm_bat:
1195 lis r8, 0xf000
1196 ori r8, r8, 0x002a
1197 mtspr SPRN_DBAT1L, r8
1198
1199 lis r11, 0xf000
1200 ori r11, r11, (BL_1M << 2) | 2
1201 mtspr SPRN_DBAT1U, r11
1202
1203 blr
1204 #endif
1205
1206 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
1207 setup_usbgecko_bat:
1208 /* prepare a BAT for early io */
1209 #if defined(CONFIG_GAMECUBE)
1210 lis r8, 0x0c00
1211 #elif defined(CONFIG_WII)
1212 lis r8, 0x0d00
1213 #else
1214 #error Invalid platform for USB Gecko based early debugging.
1215 #endif
1216 /*
1217 * The virtual address used must match the virtual address
1218 * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
1219 */
1220 lis r11, 0xfffe /* top 128K */
1221 ori r8, r8, 0x002a /* uncached, guarded ,rw */
1222 ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */
1223 mtspr SPRN_DBAT1L, r8
1224 mtspr SPRN_DBAT1U, r11
1225 blr
1226 #endif
1227
1228 #ifdef CONFIG_8260
1229 /* Jump into the system reset for the rom.
1230 * We first disable the MMU, and then jump to the ROM reset address.
1231 *
1232 * r3 is the board info structure, r4 is the location for starting.
1233 * I use this for building a small kernel that can load other kernels,
1234 * rather than trying to write or rely on a rom monitor that can tftp load.
1235 */
1236 .globl m8260_gorom
1237 m8260_gorom:
1238 mfmsr r0
1239 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1240 sync
1241 mtmsr r0
1242 sync
1243 mfspr r11, SPRN_HID0
1244 lis r10, 0
1245 ori r10,r10,HID0_ICE|HID0_DCE
1246 andc r11, r11, r10
1247 mtspr SPRN_HID0, r11
1248 isync
1249 li r5, MSR_ME|MSR_RI
1250 lis r6,2f@h
1251 addis r6,r6,-KERNELBASE@h
1252 ori r6,r6,2f@l
1253 mtspr SPRN_SRR0,r6
1254 mtspr SPRN_SRR1,r5
1255 isync
1256 sync
1257 rfi
1258 2:
1259 mtlr r4
1260 blr
1261 #endif
1262
1263
1264 /*
1265 * We put a few things here that have to be page-aligned.
1266 * This stuff goes at the beginning of the data segment,
1267 * which is page-aligned.
1268 */
1269 .data
1270 .globl sdata
1271 sdata:
1272 .globl empty_zero_page
1273 empty_zero_page:
1274 .space 4096
1275
1276 .globl swapper_pg_dir
1277 swapper_pg_dir:
1278 .space PGD_TABLE_SIZE
1279
1280 .globl intercept_table
1281 intercept_table:
1282 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1283 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1284 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1285 .long 0, 0, 0, 0, 0, 0, 0, 0
1286 .long 0, 0, 0, 0, 0, 0, 0, 0
1287 .long 0, 0, 0, 0, 0, 0, 0, 0
1288
1289 /* Room for two PTE pointers, usually the kernel and current user pointers
1290 * to their respective root page table.
1291 */
1292 abatron_pteptrs:
1293 .space 8
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