3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
24 #include <linux/init.h>
28 #include <asm/pgtable.h>
29 #include <asm/cputable.h>
30 #include <asm/cache.h>
31 #include <asm/thread_info.h>
32 #include <asm/ppc_asm.h>
33 #include <asm/asm-offsets.h>
34 #include <asm/ptrace.h>
36 #include <asm/kvm_book3s_asm.h>
37 #include <asm/export.h>
38 #include <asm/feature-fixups.h>
42 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
43 #define LOAD_BAT(n, reg, RA, RB) \
44 /* see the comment for clear_bats() -- Cort */ \
46 mtspr SPRN_IBAT##n##U,RA; \
47 mtspr SPRN_DBAT##n##U,RA; \
48 lwz RA,(n*16)+0(reg); \
49 lwz RB,(n*16)+4(reg); \
50 mtspr SPRN_IBAT##n##U,RA; \
51 mtspr SPRN_IBAT##n##L,RB; \
53 lwz RA,(n*16)+8(reg); \
54 lwz RB,(n*16)+12(reg); \
55 mtspr SPRN_DBAT##n##U,RA; \
56 mtspr SPRN_DBAT##n##L,RB; \
60 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
61 .stabs "head_32.S",N_SO,0,0,0f
66 * _start is defined this way because the XCOFF loader in the OpenFirmware
67 * on the powermac expects the entry point to be a procedure descriptor.
71 * These are here for legacy reasons, the kernel used to
72 * need to look like a coff function entry for the pmac
73 * but we're always started by some kind of bootloader now.
76 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
77 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
81 * Enter here with the kernel text, data and bss loaded starting at
82 * 0, running with virtual == physical mapping.
83 * r5 points to the prom entry point (the client interface handler
84 * address). Address translation is turned on, with the prom
85 * managing the hash table. Interrupts are disabled. The stack
86 * pointer (r1) points to just below the end of the half-meg region
87 * from 0x380000 - 0x400000, which is mapped in already.
89 * If we are booted from MacOS via BootX, we enter with the kernel
90 * image loaded somewhere, and the following values in registers:
91 * r3: 'BooX' (0x426f6f58)
92 * r4: virtual address of boot_infos_t
96 * This is jumped to on prep systems right after the kernel is relocated
97 * to its proper place in memory by the boot loader. The expected layout
99 * r3: ptr to residual data
100 * r4: initrd_start or if no initrd then 0
101 * r5: initrd_end - unused if r4 is 0
102 * r6: Start of command line string
103 * r7: End of command line string
105 * This just gets a minimal mmu environment setup so we can call
106 * start_here() to do the real work.
113 * We have to do any OF calls before we map ourselves to KERNELBASE,
114 * because OF may have I/O devices mapped into that area
115 * (particularly on CHRP).
120 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
121 /* find out where we are now */
123 0: mflr r8 /* r8 = runtime addr here */
124 addis r8,r8,(_stext - 0b)@ha
125 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
127 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
129 /* We never return. We also hit that trap if trying to boot
130 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
134 * Check for BootX signature when supporting PowerMac and branch to
135 * appropriate trampoline if it's present
137 #ifdef CONFIG_PPC_PMAC
144 #endif /* CONFIG_PPC_PMAC */
146 1: mr r31,r3 /* save device tree ptr */
150 * early_init() does the early machine identification and does
151 * the necessary low-level setup and clears the BSS
152 * -- Cort <cort@fsmlabs.com>
156 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
157 * the physical address we are running at, returned by early_init()
165 bl load_segment_registers
169 #if defined(CONFIG_BOOTX_TEXT)
172 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
175 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
176 bl setup_usbgecko_bat
180 * Call setup_cpu for CPU 0 and initialize 6xx Idle
184 bl call_setup_cpu /* Call setup_cpu for this CPU */
185 #ifdef CONFIG_PPC_BOOK3S_32
188 #endif /* CONFIG_PPC_BOOK3S_32 */
192 * We need to run with _start at physical address 0.
193 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
194 * the exception vectors at 0 (and therefore this copy
195 * overwrites OF's exception vectors with our own).
196 * The MMU is off at this point.
200 addis r4,r3,KERNELBASE@h /* current address of _start */
201 lis r5,PHYSICAL_START@h
202 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
205 * we now have the 1st 16M of ram mapped with the bats.
206 * prep needs the mmu to be turned on here, but pmac already has it on.
207 * this shouldn't bother the pmac since it just gets turned on again
208 * as we jump to our code at KERNELBASE. -- Cort
209 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
210 * off, and in other cases, we now turn it off before changing BATs above.
214 ori r0,r0,MSR_DR|MSR_IR|MSR_RI
217 ori r0,r0,start_here@l
220 RFI /* enables MMU */
223 * We need __secondary_hold as a place to hold the other cpus on
224 * an SMP machine, even when we are running a UP kernel.
226 . = 0xc0 /* for prep bootloader */
227 li r3,1 /* MTX only has 1 cpu */
228 .globl __secondary_hold
230 /* tell the master we're here */
231 stw r3,__secondary_hold_acknowledge@l(0)
234 /* wait until we're told to start */
237 /* our cpu # was at addr 0 - go */
238 mr r24,r3 /* cpu # */
242 #endif /* CONFIG_SMP */
244 .globl __secondary_hold_spinloop
245 __secondary_hold_spinloop:
247 .globl __secondary_hold_acknowledge
248 __secondary_hold_acknowledge:
252 /* core99 pmac starts the seconary here by changing the vector, and
253 putting it back to what it was (unknown_exception) when done. */
254 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
258 * On CHRP, this is complicated by the fact that we could get a
259 * machine check inside RTAS, and we have no guarantee that certain
260 * critical registers will have the values we expect. The set of
261 * registers that might have bad values includes all the GPRs
262 * and all the BATs. We indicate that we are in RTAS by putting
263 * a non-zero value, the address of the exception frame to use,
264 * in thread.rtas_sp. The machine check handler checks thread.rtas_sp
265 * and uses its value if it is non-zero.
266 * (Other exception handlers assume that r1 is a valid kernel stack
267 * pointer when we take an exception from supervisor mode.)
272 mtspr SPRN_SPRG_SCRATCH0,r10
273 mtspr SPRN_SPRG_SCRATCH1,r11
275 #ifdef CONFIG_PPC_CHRP
276 mfspr r11, SPRN_SPRG_THREAD
277 lwz r11, RTAS_SP(r11)
280 #endif /* CONFIG_PPC_CHRP */
282 7: EXCEPTION_PROLOG_2
283 addi r3,r1,STACK_FRAME_OVERHEAD
284 #ifdef CONFIG_PPC_CHRP
287 EXC_XFER_STD(0x200, machine_check_exception)
288 #ifdef CONFIG_PPC_CHRP
289 1: b machine_check_in_rtas
292 /* Data access exception. */
299 #ifdef CONFIG_PPC_KUAP
300 andis. r0,r10,(DSISR_BAD_FAULT_32S | DSISR_DABRMATCH | DSISR_PROTFAULT)@h
302 andis. r0,r10,(DSISR_BAD_FAULT_32S|DSISR_DABRMATCH)@h
304 bne 1f /* if not, try to put a PTE */
305 mfspr r4,SPRN_DAR /* into the hash table */
306 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
307 BEGIN_MMU_FTR_SECTION
309 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
310 1: lwz r5,_DSISR(r11) /* get DSISR value */
312 EXC_XFER_LITE(0x300, handle_page_fault)
315 /* Instruction access exception. */
320 andis. r0,r9,SRR1_ISI_NOPT@h /* no pte found? */
321 beq 1f /* if so, try to put a PTE */
322 li r3,0 /* into the hash table */
323 mr r4,r12 /* SRR0 is fault address */
324 BEGIN_MMU_FTR_SECTION
326 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
328 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
329 EXC_XFER_LITE(0x400, handle_page_fault)
331 /* External interrupt */
332 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
334 /* Alignment exception */
343 addi r3,r1,STACK_FRAME_OVERHEAD
344 EXC_XFER_STD(0x600, alignment_exception)
346 /* Program check exception */
347 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
349 /* Floating-point unavailable */
355 * Certain Freescale cores don't have a FPU and treat fp instructions
356 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
359 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
362 bl load_up_fpu /* if from user, just load it up */
363 b fast_exception_return
364 1: addi r3,r1,STACK_FRAME_OVERHEAD
365 EXC_XFER_LITE(0x800, kernel_fp_unavailable_exception)
368 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
370 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_STD)
371 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_STD)
379 /* Single step - not used on 601 */
380 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
381 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_STD)
384 * The Altivec unavailable trap is at 0x0f20. Foo.
385 * We effectively remap it to 0x3000.
386 * We include an altivec unavailable exception vector even if
387 * not configured for Altivec, so that you can't panic a
388 * non-altivec kernel running on a machine with altivec just
389 * by executing an altivec instruction.
400 * Handle TLB miss for instruction on 603/603e.
401 * Note: we get an alternate set of r0 - r3 to use automatically.
407 * r1: linux style pte ( later becomes ppc hardware pte )
408 * r2: ptr to linux-style pte
411 /* Get PTE (linux-style) and check access */
413 #if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
414 lis r1,PAGE_OFFSET@h /* check if kernel address */
417 mfspr r2, SPRN_SPRG_PGDIR
419 li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
421 li r1,_PAGE_PRESENT | _PAGE_EXEC
423 #if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
425 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
426 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
428 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
429 lwz r2,0(r2) /* get pmd entry */
430 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
431 beq- InstructionAddressInvalid /* return if no mapping */
432 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
433 lwz r0,0(r2) /* get linux-style pte */
434 andc. r1,r1,r0 /* check access & ~permission */
435 bne- InstructionAddressInvalid /* return if access not permitted */
436 /* Convert linux-style PTE to low word of PPC-style PTE */
437 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
438 ori r1, r1, 0xe06 /* clear out reserved bits */
439 andc r1, r0, r1 /* PP = user? 1 : 0 */
441 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
442 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
445 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
448 InstructionAddressInvalid:
450 rlwinm r1,r3,9,6,6 /* Get load/store bit */
453 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
454 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
457 mfspr r1,SPRN_IMISS /* Get failing address */
458 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
459 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
461 mtspr SPRN_DAR,r1 /* Set fault address */
462 mfmsr r0 /* Restore "normal" registers */
463 xoris r0,r0,MSR_TGPR>>16
464 mtcrf 0x80,r3 /* Restore CR0 */
469 * Handle TLB miss for DATA Load operation on 603/603e
475 * r1: linux style pte ( later becomes ppc hardware pte )
476 * r2: ptr to linux-style pte
479 /* Get PTE (linux-style) and check access */
481 lis r1,PAGE_OFFSET@h /* check if kernel address */
483 mfspr r2, SPRN_SPRG_PGDIR
485 li r1, _PAGE_PRESENT | _PAGE_ACCESSED
490 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
491 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
492 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
493 lwz r2,0(r2) /* get pmd entry */
494 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
495 beq- DataAddressInvalid /* return if no mapping */
496 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
497 lwz r0,0(r2) /* get linux-style pte */
498 andc. r1,r1,r0 /* check access & ~permission */
499 bne- DataAddressInvalid /* return if access not permitted */
501 * NOTE! We are assuming this is not an SMP system, otherwise
502 * we would need to update the pte atomically with lwarx/stwcx.
504 /* Convert linux-style PTE to low word of PPC-style PTE */
505 rlwinm r1,r0,32-9,30,30 /* _PAGE_RW -> PP msb */
506 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
507 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
508 ori r1,r1,0xe04 /* clear out reserved bits */
509 andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */
511 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
512 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
514 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
516 BEGIN_MMU_FTR_SECTION
518 mfspr r1,SPRN_SPRG_603_LRU
519 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
523 mtspr SPRN_SPRG_603_LRU,r1
525 rlwimi r2,r0,31-14,14,14
527 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
532 rlwinm r1,r3,9,6,6 /* Get load/store bit */
535 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
537 mfspr r1,SPRN_DMISS /* Get failing address */
538 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
539 beq 20f /* Jump if big endian */
541 20: mtspr SPRN_DAR,r1 /* Set fault address */
542 mfmsr r0 /* Restore "normal" registers */
543 xoris r0,r0,MSR_TGPR>>16
544 mtcrf 0x80,r3 /* Restore CR0 */
549 * Handle TLB miss for DATA Store on 603/603e
555 * r1: linux style pte ( later becomes ppc hardware pte )
556 * r2: ptr to linux-style pte
559 /* Get PTE (linux-style) and check access */
561 lis r1,PAGE_OFFSET@h /* check if kernel address */
563 mfspr r2, SPRN_SPRG_PGDIR
565 li r1, _PAGE_RW | _PAGE_PRESENT | _PAGE_ACCESSED
567 li r1, _PAGE_RW | _PAGE_PRESENT
570 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
571 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
572 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
573 lwz r2,0(r2) /* get pmd entry */
574 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
575 beq- DataAddressInvalid /* return if no mapping */
576 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
577 lwz r0,0(r2) /* get linux-style pte */
578 andc. r1,r1,r0 /* check access & ~permission */
579 bne- DataAddressInvalid /* return if access not permitted */
581 * NOTE! We are assuming this is not an SMP system, otherwise
582 * we would need to update the pte atomically with lwarx/stwcx.
584 /* Convert linux-style PTE to low word of PPC-style PTE */
585 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
586 li r1,0xe06 /* clear out reserved bits & PP msb */
587 andc r1,r0,r1 /* PP = user? 1: 0 */
589 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
590 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
592 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
594 BEGIN_MMU_FTR_SECTION
596 mfspr r1,SPRN_SPRG_603_LRU
597 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
601 mtspr SPRN_SPRG_603_LRU,r1
603 rlwimi r2,r0,31-14,14,14
605 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
609 #ifndef CONFIG_ALTIVEC
610 #define altivec_assist_exception unknown_exception
613 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_STD)
614 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_STD)
615 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
616 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_STD)
617 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
618 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
619 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
620 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_STD)
621 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_STD)
622 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_STD)
623 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD)
624 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD)
625 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD)
626 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_STD)
627 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_STD)
628 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_STD)
629 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_STD)
630 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_STD)
631 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_STD)
632 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_STD)
633 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_STD)
634 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_STD)
635 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_STD)
636 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_STD)
637 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_STD)
638 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_STD)
639 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_STD)
640 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_STD)
641 EXCEPTION(0x2f00, Trap_2f, unknown_exception, EXC_XFER_STD)
647 #ifdef CONFIG_ALTIVEC
649 bl load_up_altivec /* if from user, just load it up */
650 b fast_exception_return
651 #endif /* CONFIG_ALTIVEC */
652 1: addi r3,r1,STACK_FRAME_OVERHEAD
653 EXC_XFER_LITE(0xf20, altivec_unavailable_exception)
657 addi r3,r1,STACK_FRAME_OVERHEAD
658 EXC_XFER_STD(0xf00, performance_monitor_exception)
662 * This code is jumped to from the startup code to copy
663 * the kernel image to physical address PHYSICAL_START.
666 addis r9,r26,klimit@ha /* fetch klimit */
668 addis r25,r25,-KERNELBASE@h
669 lis r3,PHYSICAL_START@h /* Destination base address */
670 li r6,0 /* Destination offset */
671 li r5,0x4000 /* # bytes of memory to copy */
672 bl copy_and_flush /* copy the first 0x4000 bytes */
673 addi r0,r3,4f@l /* jump to the address of 4f */
674 mtctr r0 /* in copy and do the rest. */
675 bctr /* jump to the copy */
677 bl copy_and_flush /* copy the rest */
681 * Copy routine used to copy the kernel to start at physical address 0
682 * and flush and invalidate the caches as needed.
683 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
684 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
686 _ENTRY(copy_and_flush)
689 4: li r0,L1_CACHE_BYTES/4
691 3: addi r6,r6,4 /* copy a cache line */
695 dcbst r6,r3 /* write it to memory */
697 icbi r6,r3 /* flush the icache line */
700 sync /* additional sync needed on g4 */
707 .globl __secondary_start_mpc86xx
708 __secondary_start_mpc86xx:
710 stw r3, __secondary_hold_acknowledge@l(0)
711 mr r24, r3 /* cpu # */
714 .globl __secondary_start_pmac_0
715 __secondary_start_pmac_0:
716 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
725 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
726 set to map the 0xf0000000 - 0xffffffff region */
728 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
733 .globl __secondary_start
735 /* Copy some CPU settings from CPU 0 */
736 bl __restore_cpu_setup
740 bl call_setup_cpu /* Call setup_cpu for this CPU */
741 #ifdef CONFIG_PPC_BOOK3S_32
744 #endif /* CONFIG_PPC_BOOK3S_32 */
746 /* get current's stack and current */
747 lis r2,secondary_current@ha
749 lwz r2,secondary_current@l(r2)
751 lwz r1,TASK_STACK(r1)
754 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
759 /* load up the MMU */
762 /* ptr to phys current thread */
764 addi r4,r4,THREAD /* phys address of our thread_struct */
765 mtspr SPRN_SPRG_THREAD,r4
766 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
767 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
768 mtspr SPRN_SPRG_PGDIR, r4
770 /* enable MMU and jump to start_secondary */
772 lis r3,start_secondary@h
773 ori r3,r3,start_secondary@l
778 #endif /* CONFIG_SMP */
780 #ifdef CONFIG_KVM_BOOK3S_HANDLER
781 #include "../kvm/book3s_rmhandlers.S"
785 * Those generic dummy functions are kept for CPUs not
786 * included in CONFIG_PPC_BOOK3S_32
788 #if !defined(CONFIG_PPC_BOOK3S_32)
789 _ENTRY(__save_cpu_setup)
791 _ENTRY(__restore_cpu_setup)
793 #endif /* !defined(CONFIG_PPC_BOOK3S_32) */
796 * Load stuff into the MMU. Intended to be called with
801 sync /* Force all PTE updates to finish */
803 tlbia /* Clear all TLB entries */
804 sync /* wait for tlbia/tlbie to finish */
805 TLBSYNC /* ... on all CPUs */
806 /* Load the SDR1 register (hash table base & size) */
807 lis r6, early_hash - PAGE_OFFSET@h
808 ori r6, r6, 3 /* 256kB table */
814 sync /* Force all PTE updates to finish */
816 tlbia /* Clear all TLB entries */
817 sync /* wait for tlbia/tlbie to finish */
818 TLBSYNC /* ... on all CPUs */
819 /* Load the SDR1 register (hash table base & size) */
825 /* Load the BAT registers with the values set up by MMU_init.
826 MMU_init takes care of whether we're on a 601 or not. */
837 BEGIN_MMU_FTR_SECTION
842 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
845 load_segment_registers:
846 li r0, NUM_USER_SEGMENTS /* load up user segment register values */
847 mtctr r0 /* for context 0 */
848 li r3, 0 /* Kp = 0, Ks = 0, VSID = 0 */
849 #ifdef CONFIG_PPC_KUEP
850 oris r3, r3, SR_NX@h /* Set Nx */
852 #ifdef CONFIG_PPC_KUAP
853 oris r3, r3, SR_KS@h /* Set Ks */
857 addi r3, r3, 0x111 /* increment VSID */
858 addis r4, r4, 0x1000 /* address of next segment */
860 li r0, 16 - NUM_USER_SEGMENTS /* load up kernel segment registers */
861 mtctr r0 /* for context 0 */
862 rlwinm r3, r3, 0, ~SR_NX /* Nx = 0 */
863 rlwinm r3, r3, 0, ~SR_KS /* Ks = 0 */
864 oris r3, r3, SR_KP@h /* Kp = 1 */
866 addi r3, r3, 0x111 /* increment VSID */
867 addis r4, r4, 0x1000 /* address of next segment */
872 * This is where the main kernel code starts.
877 ori r2,r2,init_task@l
878 /* Set up for using our exception vectors */
879 /* ptr to phys current thread */
881 addi r4,r4,THREAD /* init task's THREAD */
882 mtspr SPRN_SPRG_THREAD,r4
883 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
884 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
885 mtspr SPRN_SPRG_PGDIR, r4
888 lis r1,init_thread_union@ha
889 addi r1,r1,init_thread_union@l
891 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
893 * Do early platform-specific initialization,
894 * and set up the MMU.
904 BEGIN_MMU_FTR_SECTION
906 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
909 * Go back to running unmapped so we can load up new values
910 * for SDR1 (hash table pointer) and the segment registers
911 * and change to using our exception vectors.
916 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
921 /* Load up the kernel context */
924 #ifdef CONFIG_BDI_SWITCH
925 /* Add helper information for the Abatron bdiGDB debugger.
926 * We do this here because we know the mmu is disabled, and
927 * will be enabled for real in just a few instructions.
929 lis r5, abatron_pteptrs@h
930 ori r5, r5, abatron_pteptrs@l
931 stw r5, 0xf0(r0) /* This much match your Abatron config */
932 lis r6, swapper_pg_dir@h
933 ori r6, r6, swapper_pg_dir@l
936 #endif /* CONFIG_BDI_SWITCH */
938 /* Now turn on the MMU for real! */
940 lis r3,start_kernel@h
941 ori r3,r3,start_kernel@l
948 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
950 * Set up the segment registers for a new context.
952 _ENTRY(switch_mmu_context)
953 lwz r3,MMCONTEXTID(r4)
956 mulli r3,r3,897 /* multiply context by skew factor */
957 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
958 #ifdef CONFIG_PPC_KUEP
959 oris r3, r3, SR_NX@h /* Set Nx */
961 #ifdef CONFIG_PPC_KUAP
962 oris r3, r3, SR_KS@h /* Set Ks */
964 li r0,NUM_USER_SEGMENTS
968 #ifdef CONFIG_BDI_SWITCH
969 /* Context switch the PTE pointer for the Abatron BDI2000.
970 * The PGDIR is passed as second argument.
972 lis r5, abatron_pteptrs@ha
973 stw r4, abatron_pteptrs@l + 0x4(r5)
976 mtspr SPRN_SPRG_PGDIR, r4
981 addi r3,r3,0x111 /* next VSID */
982 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
983 addis r4,r4,0x1000 /* address of next segment */
989 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
991 EXPORT_SYMBOL(switch_mmu_context)
994 * An undocumented "feature" of 604e requires that the v bit
995 * be cleared before changing BAT values.
997 * Also, newer IBM firmware does not clear bat3 and 4 so
998 * this makes sure it's done.
1004 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1008 mtspr SPRN_DBAT0U,r10
1009 mtspr SPRN_DBAT0L,r10
1010 mtspr SPRN_DBAT1U,r10
1011 mtspr SPRN_DBAT1L,r10
1012 mtspr SPRN_DBAT2U,r10
1013 mtspr SPRN_DBAT2L,r10
1014 mtspr SPRN_DBAT3U,r10
1015 mtspr SPRN_DBAT3L,r10
1017 mtspr SPRN_IBAT0U,r10
1018 mtspr SPRN_IBAT0L,r10
1019 mtspr SPRN_IBAT1U,r10
1020 mtspr SPRN_IBAT1L,r10
1021 mtspr SPRN_IBAT2U,r10
1022 mtspr SPRN_IBAT2L,r10
1023 mtspr SPRN_IBAT3U,r10
1024 mtspr SPRN_IBAT3L,r10
1025 BEGIN_MMU_FTR_SECTION
1026 /* Here's a tweak: at this point, CPU setup have
1027 * not been called yet, so HIGH_BAT_EN may not be
1028 * set in HID0 for the 745x processors. However, it
1029 * seems that doesn't affect our ability to actually
1030 * write to these SPRs.
1032 mtspr SPRN_DBAT4U,r10
1033 mtspr SPRN_DBAT4L,r10
1034 mtspr SPRN_DBAT5U,r10
1035 mtspr SPRN_DBAT5L,r10
1036 mtspr SPRN_DBAT6U,r10
1037 mtspr SPRN_DBAT6L,r10
1038 mtspr SPRN_DBAT7U,r10
1039 mtspr SPRN_DBAT7L,r10
1040 mtspr SPRN_IBAT4U,r10
1041 mtspr SPRN_IBAT4L,r10
1042 mtspr SPRN_IBAT5U,r10
1043 mtspr SPRN_IBAT5L,r10
1044 mtspr SPRN_IBAT6U,r10
1045 mtspr SPRN_IBAT6L,r10
1046 mtspr SPRN_IBAT7U,r10
1047 mtspr SPRN_IBAT7L,r10
1048 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1057 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR)
1058 rlwinm r0, r6, 0, ~MSR_RI
1059 rlwinm r0, r0, 0, ~MSR_EE
1069 LOAD_BAT(0, r3, r4, r5)
1070 LOAD_BAT(1, r3, r4, r5)
1071 LOAD_BAT(2, r3, r4, r5)
1072 LOAD_BAT(3, r3, r4, r5)
1073 BEGIN_MMU_FTR_SECTION
1074 LOAD_BAT(4, r3, r4, r5)
1075 LOAD_BAT(5, r3, r4, r5)
1076 LOAD_BAT(6, r3, r4, r5)
1077 LOAD_BAT(7, r3, r4, r5)
1078 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1079 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
1088 1: addic. r10, r10, -0x1000
1095 addi r4, r3, __after_mmu_off - _start
1097 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1106 * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET
1107 * (we keep one for debugging) and on others, we use one 256M BAT.
1110 lis r11,PAGE_OFFSET@h
1112 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1115 ori r11,r11,4 /* set up BAT registers for 601 */
1116 li r8,0x7f /* valid, block length = 8MB */
1117 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1118 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1119 addis r11,r11,0x800000@h
1120 addis r8,r8,0x800000@h
1121 mtspr SPRN_IBAT1U,r11
1122 mtspr SPRN_IBAT1L,r8
1123 addis r11,r11,0x800000@h
1124 addis r8,r8,0x800000@h
1125 mtspr SPRN_IBAT2U,r11
1126 mtspr SPRN_IBAT2L,r8
1132 ori r8,r8,0x12 /* R/W access, M=1 */
1134 ori r8,r8,2 /* R/W access */
1135 #endif /* CONFIG_SMP */
1136 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1138 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1139 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1140 mtspr SPRN_IBAT0L,r8
1141 mtspr SPRN_IBAT0U,r11
1146 #ifdef CONFIG_BOOTX_TEXT
1149 * setup the display bat prepared for us in prom.c
1154 addis r8,r3,disp_BAT@ha
1155 addi r8,r8,disp_BAT@l
1161 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1164 mtspr SPRN_DBAT3L,r8
1165 mtspr SPRN_DBAT3U,r11
1167 1: mtspr SPRN_IBAT3L,r8
1168 mtspr SPRN_IBAT3U,r11
1170 #endif /* CONFIG_BOOTX_TEXT */
1172 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1176 mtspr SPRN_DBAT1L, r8
1179 ori r11, r11, (BL_1M << 2) | 2
1180 mtspr SPRN_DBAT1U, r11
1185 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
1187 /* prepare a BAT for early io */
1188 #if defined(CONFIG_GAMECUBE)
1190 #elif defined(CONFIG_WII)
1193 #error Invalid platform for USB Gecko based early debugging.
1196 * The virtual address used must match the virtual address
1197 * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
1199 lis r11, 0xfffe /* top 128K */
1200 ori r8, r8, 0x002a /* uncached, guarded ,rw */
1201 ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */
1202 mtspr SPRN_DBAT1L, r8
1203 mtspr SPRN_DBAT1U, r11
1208 /* Jump into the system reset for the rom.
1209 * We first disable the MMU, and then jump to the ROM reset address.
1211 * r3 is the board info structure, r4 is the location for starting.
1212 * I use this for building a small kernel that can load other kernels,
1213 * rather than trying to write or rely on a rom monitor that can tftp load.
1218 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1222 mfspr r11, SPRN_HID0
1224 ori r10,r10,HID0_ICE|HID0_DCE
1226 mtspr SPRN_HID0, r11
1228 li r5, MSR_ME|MSR_RI
1230 addis r6,r6,-KERNELBASE@h
1244 * We put a few things here that have to be page-aligned.
1245 * This stuff goes at the beginning of the data segment,
1246 * which is page-aligned.
1251 .globl empty_zero_page
1254 EXPORT_SYMBOL(empty_zero_page)
1256 .globl swapper_pg_dir
1258 .space PGD_TABLE_SIZE
1260 /* Room for two PTE pointers, usually the kernel and current user pointers
1261 * to their respective root page table.