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1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 *
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
14 *
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 */
23
24 #include <linux/threads.h>
25 #include <asm/reg.h>
26 #include <asm/page.h>
27 #include <asm/mmu.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/bug.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/iseries/lpar_map.h>
35 #include <asm/thread_info.h>
36 #include <asm/firmware.h>
37 #include <asm/page_64.h>
38
39 #define DO_SOFT_DISABLE
40
41 /*
42 * We layout physical memory as follows:
43 * 0x0000 - 0x00ff : Secondary processor spin code
44 * 0x0100 - 0x2fff : pSeries Interrupt prologs
45 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
46 * 0x6000 - 0x6fff : Initial (CPU0) segment table
47 * 0x7000 - 0x7fff : FWNMI data area
48 * 0x8000 - : Early init and support code
49 */
50
51 /*
52 * SPRG Usage
53 *
54 * Register Definition
55 *
56 * SPRG0 reserved for hypervisor
57 * SPRG1 temp - used to save gpr
58 * SPRG2 temp - used to save gpr
59 * SPRG3 virt addr of paca
60 */
61
62 /*
63 * Entering into this code we make the following assumptions:
64 * For pSeries:
65 * 1. The MMU is off & open firmware is running in real mode.
66 * 2. The kernel is entered at __start
67 *
68 * For iSeries:
69 * 1. The MMU is on (as it always is for iSeries)
70 * 2. The kernel is entered at system_reset_iSeries
71 */
72
73 .text
74 .globl _stext
75 _stext:
76 _GLOBAL(__start)
77 /* NOP this out unconditionally */
78 BEGIN_FTR_SECTION
79 b .__start_initialization_multiplatform
80 END_FTR_SECTION(0, 1)
81
82 /* Catch branch to 0 in real mode */
83 trap
84
85 /* Secondary processors spin on this value until it goes to 1. */
86 .globl __secondary_hold_spinloop
87 __secondary_hold_spinloop:
88 .llong 0x0
89
90 /* Secondary processors write this value with their cpu # */
91 /* after they enter the spin loop immediately below. */
92 .globl __secondary_hold_acknowledge
93 __secondary_hold_acknowledge:
94 .llong 0x0
95
96 #ifdef CONFIG_PPC_ISERIES
97 /*
98 * At offset 0x20, there is a pointer to iSeries LPAR data.
99 * This is required by the hypervisor
100 */
101 . = 0x20
102 .llong hvReleaseData-KERNELBASE
103 #endif /* CONFIG_PPC_ISERIES */
104
105 . = 0x60
106 /*
107 * The following code is used to hold secondary processors
108 * in a spin loop after they have entered the kernel, but
109 * before the bulk of the kernel has been relocated. This code
110 * is relocated to physical address 0x60 before prom_init is run.
111 * All of it must fit below the first exception vector at 0x100.
112 */
113 _GLOBAL(__secondary_hold)
114 mfmsr r24
115 ori r24,r24,MSR_RI
116 mtmsrd r24 /* RI on */
117
118 /* Grab our physical cpu number */
119 mr r24,r3
120
121 /* Tell the master cpu we're here */
122 /* Relocation is off & we are located at an address less */
123 /* than 0x100, so only need to grab low order offset. */
124 std r24,__secondary_hold_acknowledge@l(0)
125 sync
126
127 /* All secondary cpus wait here until told to start. */
128 100: ld r4,__secondary_hold_spinloop@l(0)
129 cmpdi 0,r4,1
130 bne 100b
131
132 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
133 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
134 mtctr r4
135 mr r3,r24
136 bctr
137 #else
138 BUG_OPCODE
139 #endif
140
141 /* This value is used to mark exception frames on the stack. */
142 .section ".toc","aw"
143 exception_marker:
144 .tc ID_72656773_68657265[TC],0x7265677368657265
145 .text
146
147 /*
148 * The following macros define the code that appears as
149 * the prologue to each of the exception handlers. They
150 * are split into two parts to allow a single kernel binary
151 * to be used for pSeries and iSeries.
152 * LOL. One day... - paulus
153 */
154
155 /*
156 * We make as much of the exception code common between native
157 * exception handlers (including pSeries LPAR) and iSeries LPAR
158 * implementations as possible.
159 */
160
161 /*
162 * This is the start of the interrupt handlers for pSeries
163 * This code runs with relocation off.
164 */
165 #define EX_R9 0
166 #define EX_R10 8
167 #define EX_R11 16
168 #define EX_R12 24
169 #define EX_R13 32
170 #define EX_SRR0 40
171 #define EX_DAR 48
172 #define EX_DSISR 56
173 #define EX_CCR 60
174 #define EX_R3 64
175 #define EX_LR 72
176
177 /*
178 * We're short on space and time in the exception prolog, so we can't
179 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
180 * low halfword of the address, but for Kdump we need the whole low
181 * word.
182 */
183 #ifdef CONFIG_CRASH_DUMP
184 #define LOAD_HANDLER(reg, label) \
185 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
186 ori reg,reg,(label)@l; /* .. and the rest */
187 #else
188 #define LOAD_HANDLER(reg, label) \
189 ori reg,reg,(label)@l; /* virt addr of handler ... */
190 #endif
191
192 /*
193 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
194 * The firmware calls the registered system_reset_fwnmi and
195 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
196 * a 32bit application at the time of the event.
197 * This firmware bug is present on POWER4 and JS20.
198 */
199 #define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \
200 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
201 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
202 std r10,area+EX_R10(r13); \
203 std r11,area+EX_R11(r13); \
204 std r12,area+EX_R12(r13); \
205 mfspr r9,SPRN_SPRG1; \
206 std r9,area+EX_R13(r13); \
207 mfcr r9; \
208 clrrdi r12,r13,32; /* get high part of &label */ \
209 mfmsr r10; \
210 /* force 64bit mode */ \
211 li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \
212 rldimi r10,r11,61,0; /* insert into top 3 bits */ \
213 /* done 64bit mode */ \
214 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
215 LOAD_HANDLER(r12,label) \
216 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
217 mtspr SPRN_SRR0,r12; \
218 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
219 mtspr SPRN_SRR1,r10; \
220 rfid; \
221 b . /* prevent speculative execution */
222
223 #define EXCEPTION_PROLOG_PSERIES(area, label) \
224 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
225 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
226 std r10,area+EX_R10(r13); \
227 std r11,area+EX_R11(r13); \
228 std r12,area+EX_R12(r13); \
229 mfspr r9,SPRN_SPRG1; \
230 std r9,area+EX_R13(r13); \
231 mfcr r9; \
232 clrrdi r12,r13,32; /* get high part of &label */ \
233 mfmsr r10; \
234 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
235 LOAD_HANDLER(r12,label) \
236 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
237 mtspr SPRN_SRR0,r12; \
238 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
239 mtspr SPRN_SRR1,r10; \
240 rfid; \
241 b . /* prevent speculative execution */
242
243 /*
244 * This is the start of the interrupt handlers for iSeries
245 * This code runs with relocation on.
246 */
247 #define EXCEPTION_PROLOG_ISERIES_1(area) \
248 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
249 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
250 std r10,area+EX_R10(r13); \
251 std r11,area+EX_R11(r13); \
252 std r12,area+EX_R12(r13); \
253 mfspr r9,SPRN_SPRG1; \
254 std r9,area+EX_R13(r13); \
255 mfcr r9
256
257 #define EXCEPTION_PROLOG_ISERIES_2 \
258 mfmsr r10; \
259 ld r12,PACALPPACAPTR(r13); \
260 ld r11,LPPACASRR0(r12); \
261 ld r12,LPPACASRR1(r12); \
262 ori r10,r10,MSR_RI; \
263 mtmsrd r10,1
264
265 /*
266 * The common exception prolog is used for all except a few exceptions
267 * such as a segment miss on a kernel address. We have to be prepared
268 * to take another exception from the point where we first touch the
269 * kernel stack onwards.
270 *
271 * On entry r13 points to the paca, r9-r13 are saved in the paca,
272 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
273 * SRR1, and relocation is on.
274 */
275 #define EXCEPTION_PROLOG_COMMON(n, area) \
276 andi. r10,r12,MSR_PR; /* See if coming from user */ \
277 mr r10,r1; /* Save r1 */ \
278 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
279 beq- 1f; \
280 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
281 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
282 bge- cr1,2f; /* abort if it is */ \
283 b 3f; \
284 2: li r1,(n); /* will be reloaded later */ \
285 sth r1,PACA_TRAP_SAVE(r13); \
286 b bad_stack; \
287 3: std r9,_CCR(r1); /* save CR in stackframe */ \
288 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
289 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
290 std r10,0(r1); /* make stack chain pointer */ \
291 std r0,GPR0(r1); /* save r0 in stackframe */ \
292 std r10,GPR1(r1); /* save r1 in stackframe */ \
293 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
294 std r2,GPR2(r1); /* save r2 in stackframe */ \
295 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
296 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
297 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
298 ld r10,area+EX_R10(r13); \
299 std r9,GPR9(r1); \
300 std r10,GPR10(r1); \
301 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
302 ld r10,area+EX_R12(r13); \
303 ld r11,area+EX_R13(r13); \
304 std r9,GPR11(r1); \
305 std r10,GPR12(r1); \
306 std r11,GPR13(r1); \
307 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
308 mflr r9; /* save LR in stackframe */ \
309 std r9,_LINK(r1); \
310 mfctr r10; /* save CTR in stackframe */ \
311 std r10,_CTR(r1); \
312 lbz r10,PACASOFTIRQEN(r13); \
313 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
314 std r10,SOFTE(r1); \
315 std r11,_XER(r1); \
316 li r9,(n)+1; \
317 std r9,_TRAP(r1); /* set trap number */ \
318 li r10,0; \
319 ld r11,exception_marker@toc(r2); \
320 std r10,RESULT(r1); /* clear regs->result */ \
321 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
322
323 /*
324 * Exception vectors.
325 */
326 #define STD_EXCEPTION_PSERIES(n, label) \
327 . = n; \
328 .globl label##_pSeries; \
329 label##_pSeries: \
330 HMT_MEDIUM; \
331 mtspr SPRN_SPRG1,r13; /* save r13 */ \
332 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
333
334 #define HSTD_EXCEPTION_PSERIES(n, label) \
335 . = n; \
336 .globl label##_pSeries; \
337 label##_pSeries: \
338 HMT_MEDIUM; \
339 mtspr SPRN_SPRG1,r20; /* save r20 */ \
340 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
341 mtspr SPRN_SRR0,r20; \
342 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
343 mtspr SPRN_SRR1,r20; \
344 mfspr r20,SPRN_SPRG1; /* restore r20 */ \
345 mtspr SPRN_SPRG1,r13; /* save r13 */ \
346 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
347
348
349 #define MASKABLE_EXCEPTION_PSERIES(n, label) \
350 . = n; \
351 .globl label##_pSeries; \
352 label##_pSeries: \
353 HMT_MEDIUM; \
354 mtspr SPRN_SPRG1,r13; /* save r13 */ \
355 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
356 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
357 std r10,PACA_EXGEN+EX_R10(r13); \
358 lbz r10,PACASOFTIRQEN(r13); \
359 mfcr r9; \
360 cmpwi r10,0; \
361 beq masked_interrupt; \
362 mfspr r10,SPRN_SPRG1; \
363 std r10,PACA_EXGEN+EX_R13(r13); \
364 std r11,PACA_EXGEN+EX_R11(r13); \
365 std r12,PACA_EXGEN+EX_R12(r13); \
366 clrrdi r12,r13,32; /* get high part of &label */ \
367 mfmsr r10; \
368 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
369 LOAD_HANDLER(r12,label##_common) \
370 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
371 mtspr SPRN_SRR0,r12; \
372 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
373 mtspr SPRN_SRR1,r10; \
374 rfid; \
375 b . /* prevent speculative execution */
376
377 #define STD_EXCEPTION_ISERIES(n, label, area) \
378 .globl label##_iSeries; \
379 label##_iSeries: \
380 HMT_MEDIUM; \
381 mtspr SPRN_SPRG1,r13; /* save r13 */ \
382 EXCEPTION_PROLOG_ISERIES_1(area); \
383 EXCEPTION_PROLOG_ISERIES_2; \
384 b label##_common
385
386 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
387 .globl label##_iSeries; \
388 label##_iSeries: \
389 HMT_MEDIUM; \
390 mtspr SPRN_SPRG1,r13; /* save r13 */ \
391 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
392 lbz r10,PACASOFTIRQEN(r13); \
393 cmpwi 0,r10,0; \
394 beq- label##_iSeries_masked; \
395 EXCEPTION_PROLOG_ISERIES_2; \
396 b label##_common; \
397
398 #ifdef CONFIG_PPC_ISERIES
399 #define DISABLE_INTS \
400 li r11,0; \
401 stb r11,PACASOFTIRQEN(r13); \
402 BEGIN_FW_FTR_SECTION; \
403 stb r11,PACAHARDIRQEN(r13); \
404 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
405 BEGIN_FW_FTR_SECTION; \
406 mfmsr r10; \
407 ori r10,r10,MSR_EE; \
408 mtmsrd r10,1; \
409 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
410
411 #else
412 #define DISABLE_INTS \
413 li r11,0; \
414 stb r11,PACASOFTIRQEN(r13); \
415 stb r11,PACAHARDIRQEN(r13)
416
417 #endif /* CONFIG_PPC_ISERIES */
418
419 #define ENABLE_INTS \
420 ld r12,_MSR(r1); \
421 mfmsr r11; \
422 rlwimi r11,r12,0,MSR_EE; \
423 mtmsrd r11,1
424
425 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
426 .align 7; \
427 .globl label##_common; \
428 label##_common: \
429 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
430 DISABLE_INTS; \
431 bl .save_nvgprs; \
432 addi r3,r1,STACK_FRAME_OVERHEAD; \
433 bl hdlr; \
434 b .ret_from_except
435
436 /*
437 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
438 * in the idle task and therefore need the special idle handling.
439 */
440 #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
441 .align 7; \
442 .globl label##_common; \
443 label##_common: \
444 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
445 FINISH_NAP; \
446 DISABLE_INTS; \
447 bl .save_nvgprs; \
448 addi r3,r1,STACK_FRAME_OVERHEAD; \
449 bl hdlr; \
450 b .ret_from_except
451
452 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
453 .align 7; \
454 .globl label##_common; \
455 label##_common: \
456 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
457 FINISH_NAP; \
458 DISABLE_INTS; \
459 bl .ppc64_runlatch_on; \
460 addi r3,r1,STACK_FRAME_OVERHEAD; \
461 bl hdlr; \
462 b .ret_from_except_lite
463
464 /*
465 * When the idle code in power4_idle puts the CPU into NAP mode,
466 * it has to do so in a loop, and relies on the external interrupt
467 * and decrementer interrupt entry code to get it out of the loop.
468 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
469 * to signal that it is in the loop and needs help to get out.
470 */
471 #ifdef CONFIG_PPC_970_NAP
472 #define FINISH_NAP \
473 BEGIN_FTR_SECTION \
474 clrrdi r11,r1,THREAD_SHIFT; \
475 ld r9,TI_LOCAL_FLAGS(r11); \
476 andi. r10,r9,_TLF_NAPPING; \
477 bnel power4_fixup_nap; \
478 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
479 #else
480 #define FINISH_NAP
481 #endif
482
483 /*
484 * Start of pSeries system interrupt routines
485 */
486 . = 0x100
487 .globl __start_interrupts
488 __start_interrupts:
489
490 STD_EXCEPTION_PSERIES(0x100, system_reset)
491
492 . = 0x200
493 _machine_check_pSeries:
494 HMT_MEDIUM
495 mtspr SPRN_SPRG1,r13 /* save r13 */
496 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
497
498 . = 0x300
499 .globl data_access_pSeries
500 data_access_pSeries:
501 HMT_MEDIUM
502 mtspr SPRN_SPRG1,r13
503 BEGIN_FTR_SECTION
504 mtspr SPRN_SPRG2,r12
505 mfspr r13,SPRN_DAR
506 mfspr r12,SPRN_DSISR
507 srdi r13,r13,60
508 rlwimi r13,r12,16,0x20
509 mfcr r12
510 cmpwi r13,0x2c
511 beq do_stab_bolted_pSeries
512 mtcrf 0x80,r12
513 mfspr r12,SPRN_SPRG2
514 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
515 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
516
517 . = 0x380
518 .globl data_access_slb_pSeries
519 data_access_slb_pSeries:
520 HMT_MEDIUM
521 mtspr SPRN_SPRG1,r13
522 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
523 std r3,PACA_EXSLB+EX_R3(r13)
524 mfspr r3,SPRN_DAR
525 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
526 mfcr r9
527 #ifdef __DISABLED__
528 /* Keep that around for when we re-implement dynamic VSIDs */
529 cmpdi r3,0
530 bge slb_miss_user_pseries
531 #endif /* __DISABLED__ */
532 std r10,PACA_EXSLB+EX_R10(r13)
533 std r11,PACA_EXSLB+EX_R11(r13)
534 std r12,PACA_EXSLB+EX_R12(r13)
535 mfspr r10,SPRN_SPRG1
536 std r10,PACA_EXSLB+EX_R13(r13)
537 mfspr r12,SPRN_SRR1 /* and SRR1 */
538 b .slb_miss_realmode /* Rel. branch works in real mode */
539
540 STD_EXCEPTION_PSERIES(0x400, instruction_access)
541
542 . = 0x480
543 .globl instruction_access_slb_pSeries
544 instruction_access_slb_pSeries:
545 HMT_MEDIUM
546 mtspr SPRN_SPRG1,r13
547 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
548 std r3,PACA_EXSLB+EX_R3(r13)
549 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
550 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
551 mfcr r9
552 #ifdef __DISABLED__
553 /* Keep that around for when we re-implement dynamic VSIDs */
554 cmpdi r3,0
555 bge slb_miss_user_pseries
556 #endif /* __DISABLED__ */
557 std r10,PACA_EXSLB+EX_R10(r13)
558 std r11,PACA_EXSLB+EX_R11(r13)
559 std r12,PACA_EXSLB+EX_R12(r13)
560 mfspr r10,SPRN_SPRG1
561 std r10,PACA_EXSLB+EX_R13(r13)
562 mfspr r12,SPRN_SRR1 /* and SRR1 */
563 b .slb_miss_realmode /* Rel. branch works in real mode */
564
565 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
566 STD_EXCEPTION_PSERIES(0x600, alignment)
567 STD_EXCEPTION_PSERIES(0x700, program_check)
568 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
569 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
570 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
571 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
572
573 . = 0xc00
574 .globl system_call_pSeries
575 system_call_pSeries:
576 HMT_MEDIUM
577 mr r9,r13
578 mfmsr r10
579 mfspr r13,SPRN_SPRG3
580 mfspr r11,SPRN_SRR0
581 clrrdi r12,r13,32
582 oris r12,r12,system_call_common@h
583 ori r12,r12,system_call_common@l
584 mtspr SPRN_SRR0,r12
585 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
586 mfspr r12,SPRN_SRR1
587 mtspr SPRN_SRR1,r10
588 rfid
589 b . /* prevent speculative execution */
590
591 STD_EXCEPTION_PSERIES(0xd00, single_step)
592 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
593
594 /* We need to deal with the Altivec unavailable exception
595 * here which is at 0xf20, thus in the middle of the
596 * prolog code of the PerformanceMonitor one. A little
597 * trickery is thus necessary
598 */
599 . = 0xf00
600 b performance_monitor_pSeries
601
602 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
603
604 #ifdef CONFIG_CBE_RAS
605 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
606 #endif /* CONFIG_CBE_RAS */
607 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
608 #ifdef CONFIG_CBE_RAS
609 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
610 #endif /* CONFIG_CBE_RAS */
611 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
612 #ifdef CONFIG_CBE_RAS
613 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
614 #endif /* CONFIG_CBE_RAS */
615
616 . = 0x3000
617
618 /*** pSeries interrupt support ***/
619
620 /* moved from 0xf00 */
621 STD_EXCEPTION_PSERIES(., performance_monitor)
622
623 /*
624 * An interrupt came in while soft-disabled; clear EE in SRR1,
625 * clear paca->hard_enabled and return.
626 */
627 masked_interrupt:
628 stb r10,PACAHARDIRQEN(r13)
629 mtcrf 0x80,r9
630 ld r9,PACA_EXGEN+EX_R9(r13)
631 mfspr r10,SPRN_SRR1
632 rldicl r10,r10,48,1 /* clear MSR_EE */
633 rotldi r10,r10,16
634 mtspr SPRN_SRR1,r10
635 ld r10,PACA_EXGEN+EX_R10(r13)
636 mfspr r13,SPRN_SPRG1
637 rfid
638 b .
639
640 .align 7
641 do_stab_bolted_pSeries:
642 mtcrf 0x80,r12
643 mfspr r12,SPRN_SPRG2
644 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
645
646 /*
647 * We have some room here we use that to put
648 * the peries slb miss user trampoline code so it's reasonably
649 * away from slb_miss_user_common to avoid problems with rfid
650 *
651 * This is used for when the SLB miss handler has to go virtual,
652 * which doesn't happen for now anymore but will once we re-implement
653 * dynamic VSIDs for shared page tables
654 */
655 #ifdef __DISABLED__
656 slb_miss_user_pseries:
657 std r10,PACA_EXGEN+EX_R10(r13)
658 std r11,PACA_EXGEN+EX_R11(r13)
659 std r12,PACA_EXGEN+EX_R12(r13)
660 mfspr r10,SPRG1
661 ld r11,PACA_EXSLB+EX_R9(r13)
662 ld r12,PACA_EXSLB+EX_R3(r13)
663 std r10,PACA_EXGEN+EX_R13(r13)
664 std r11,PACA_EXGEN+EX_R9(r13)
665 std r12,PACA_EXGEN+EX_R3(r13)
666 clrrdi r12,r13,32
667 mfmsr r10
668 mfspr r11,SRR0 /* save SRR0 */
669 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
670 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
671 mtspr SRR0,r12
672 mfspr r12,SRR1 /* and SRR1 */
673 mtspr SRR1,r10
674 rfid
675 b . /* prevent spec. execution */
676 #endif /* __DISABLED__ */
677
678 /*
679 * Vectors for the FWNMI option. Share common code.
680 */
681 .globl system_reset_fwnmi
682 .align 7
683 system_reset_fwnmi:
684 HMT_MEDIUM
685 mtspr SPRN_SPRG1,r13 /* save r13 */
686 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
687
688 .globl machine_check_fwnmi
689 .align 7
690 machine_check_fwnmi:
691 HMT_MEDIUM
692 mtspr SPRN_SPRG1,r13 /* save r13 */
693 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
694
695 #ifdef CONFIG_PPC_ISERIES
696 /*** ISeries-LPAR interrupt handlers ***/
697
698 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
699
700 .globl data_access_iSeries
701 data_access_iSeries:
702 mtspr SPRN_SPRG1,r13
703 BEGIN_FTR_SECTION
704 mtspr SPRN_SPRG2,r12
705 mfspr r13,SPRN_DAR
706 mfspr r12,SPRN_DSISR
707 srdi r13,r13,60
708 rlwimi r13,r12,16,0x20
709 mfcr r12
710 cmpwi r13,0x2c
711 beq .do_stab_bolted_iSeries
712 mtcrf 0x80,r12
713 mfspr r12,SPRN_SPRG2
714 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
715 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
716 EXCEPTION_PROLOG_ISERIES_2
717 b data_access_common
718
719 .do_stab_bolted_iSeries:
720 mtcrf 0x80,r12
721 mfspr r12,SPRN_SPRG2
722 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
723 EXCEPTION_PROLOG_ISERIES_2
724 b .do_stab_bolted
725
726 .globl data_access_slb_iSeries
727 data_access_slb_iSeries:
728 mtspr SPRN_SPRG1,r13 /* save r13 */
729 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
730 std r3,PACA_EXSLB+EX_R3(r13)
731 mfspr r3,SPRN_DAR
732 std r9,PACA_EXSLB+EX_R9(r13)
733 mfcr r9
734 #ifdef __DISABLED__
735 cmpdi r3,0
736 bge slb_miss_user_iseries
737 #endif
738 std r10,PACA_EXSLB+EX_R10(r13)
739 std r11,PACA_EXSLB+EX_R11(r13)
740 std r12,PACA_EXSLB+EX_R12(r13)
741 mfspr r10,SPRN_SPRG1
742 std r10,PACA_EXSLB+EX_R13(r13)
743 ld r12,PACALPPACAPTR(r13)
744 ld r12,LPPACASRR1(r12)
745 b .slb_miss_realmode
746
747 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
748
749 .globl instruction_access_slb_iSeries
750 instruction_access_slb_iSeries:
751 mtspr SPRN_SPRG1,r13 /* save r13 */
752 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
753 std r3,PACA_EXSLB+EX_R3(r13)
754 ld r3,PACALPPACAPTR(r13)
755 ld r3,LPPACASRR0(r3) /* get SRR0 value */
756 std r9,PACA_EXSLB+EX_R9(r13)
757 mfcr r9
758 #ifdef __DISABLED__
759 cmpdi r3,0
760 bge .slb_miss_user_iseries
761 #endif
762 std r10,PACA_EXSLB+EX_R10(r13)
763 std r11,PACA_EXSLB+EX_R11(r13)
764 std r12,PACA_EXSLB+EX_R12(r13)
765 mfspr r10,SPRN_SPRG1
766 std r10,PACA_EXSLB+EX_R13(r13)
767 ld r12,PACALPPACAPTR(r13)
768 ld r12,LPPACASRR1(r12)
769 b .slb_miss_realmode
770
771 #ifdef __DISABLED__
772 slb_miss_user_iseries:
773 std r10,PACA_EXGEN+EX_R10(r13)
774 std r11,PACA_EXGEN+EX_R11(r13)
775 std r12,PACA_EXGEN+EX_R12(r13)
776 mfspr r10,SPRG1
777 ld r11,PACA_EXSLB+EX_R9(r13)
778 ld r12,PACA_EXSLB+EX_R3(r13)
779 std r10,PACA_EXGEN+EX_R13(r13)
780 std r11,PACA_EXGEN+EX_R9(r13)
781 std r12,PACA_EXGEN+EX_R3(r13)
782 EXCEPTION_PROLOG_ISERIES_2
783 b slb_miss_user_common
784 #endif
785
786 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
787 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
788 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
789 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
790 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
791 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
792 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
793
794 .globl system_call_iSeries
795 system_call_iSeries:
796 mr r9,r13
797 mfspr r13,SPRN_SPRG3
798 EXCEPTION_PROLOG_ISERIES_2
799 b system_call_common
800
801 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
802 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
803 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
804
805 decrementer_iSeries_masked:
806 /* We may not have a valid TOC pointer in here. */
807 li r11,1
808 ld r12,PACALPPACAPTR(r13)
809 stb r11,LPPACADECRINT(r12)
810 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
811 lwz r12,0(r12)
812 mtspr SPRN_DEC,r12
813 /* fall through */
814
815 hardware_interrupt_iSeries_masked:
816 mtcrf 0x80,r9 /* Restore regs */
817 ld r12,PACALPPACAPTR(r13)
818 ld r11,LPPACASRR0(r12)
819 ld r12,LPPACASRR1(r12)
820 mtspr SPRN_SRR0,r11
821 mtspr SPRN_SRR1,r12
822 ld r9,PACA_EXGEN+EX_R9(r13)
823 ld r10,PACA_EXGEN+EX_R10(r13)
824 ld r11,PACA_EXGEN+EX_R11(r13)
825 ld r12,PACA_EXGEN+EX_R12(r13)
826 ld r13,PACA_EXGEN+EX_R13(r13)
827 rfid
828 b . /* prevent speculative execution */
829 #endif /* CONFIG_PPC_ISERIES */
830
831 /*** Common interrupt handlers ***/
832
833 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
834
835 /*
836 * Machine check is different because we use a different
837 * save area: PACA_EXMC instead of PACA_EXGEN.
838 */
839 .align 7
840 .globl machine_check_common
841 machine_check_common:
842 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
843 FINISH_NAP
844 DISABLE_INTS
845 bl .save_nvgprs
846 addi r3,r1,STACK_FRAME_OVERHEAD
847 bl .machine_check_exception
848 b .ret_from_except
849
850 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
851 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
852 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
853 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
854 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
855 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
856 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
857 #ifdef CONFIG_ALTIVEC
858 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
859 #else
860 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
861 #endif
862 #ifdef CONFIG_CBE_RAS
863 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
864 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
865 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
866 #endif /* CONFIG_CBE_RAS */
867
868 /*
869 * Here we have detected that the kernel stack pointer is bad.
870 * R9 contains the saved CR, r13 points to the paca,
871 * r10 contains the (bad) kernel stack pointer,
872 * r11 and r12 contain the saved SRR0 and SRR1.
873 * We switch to using an emergency stack, save the registers there,
874 * and call kernel_bad_stack(), which panics.
875 */
876 bad_stack:
877 ld r1,PACAEMERGSP(r13)
878 subi r1,r1,64+INT_FRAME_SIZE
879 std r9,_CCR(r1)
880 std r10,GPR1(r1)
881 std r11,_NIP(r1)
882 std r12,_MSR(r1)
883 mfspr r11,SPRN_DAR
884 mfspr r12,SPRN_DSISR
885 std r11,_DAR(r1)
886 std r12,_DSISR(r1)
887 mflr r10
888 mfctr r11
889 mfxer r12
890 std r10,_LINK(r1)
891 std r11,_CTR(r1)
892 std r12,_XER(r1)
893 SAVE_GPR(0,r1)
894 SAVE_GPR(2,r1)
895 SAVE_4GPRS(3,r1)
896 SAVE_2GPRS(7,r1)
897 SAVE_10GPRS(12,r1)
898 SAVE_10GPRS(22,r1)
899 lhz r12,PACA_TRAP_SAVE(r13)
900 std r12,_TRAP(r1)
901 addi r11,r1,INT_FRAME_SIZE
902 std r11,0(r1)
903 li r12,0
904 std r12,0(r11)
905 ld r2,PACATOC(r13)
906 1: addi r3,r1,STACK_FRAME_OVERHEAD
907 bl .kernel_bad_stack
908 b 1b
909
910 /*
911 * Return from an exception with minimal checks.
912 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
913 * If interrupts have been enabled, or anything has been
914 * done that might have changed the scheduling status of
915 * any task or sent any task a signal, you should use
916 * ret_from_except or ret_from_except_lite instead of this.
917 */
918 fast_exc_return_irq: /* restores irq state too */
919 ld r3,SOFTE(r1)
920 ld r12,_MSR(r1)
921 stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */
922 rldicl r4,r12,49,63 /* get MSR_EE to LSB */
923 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
924 b 1f
925
926 .globl fast_exception_return
927 fast_exception_return:
928 ld r12,_MSR(r1)
929 1: ld r11,_NIP(r1)
930 andi. r3,r12,MSR_RI /* check if RI is set */
931 beq- unrecov_fer
932
933 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
934 andi. r3,r12,MSR_PR
935 beq 2f
936 ACCOUNT_CPU_USER_EXIT(r3, r4)
937 2:
938 #endif
939
940 ld r3,_CCR(r1)
941 ld r4,_LINK(r1)
942 ld r5,_CTR(r1)
943 ld r6,_XER(r1)
944 mtcr r3
945 mtlr r4
946 mtctr r5
947 mtxer r6
948 REST_GPR(0, r1)
949 REST_8GPRS(2, r1)
950
951 mfmsr r10
952 rldicl r10,r10,48,1 /* clear EE */
953 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */
954 mtmsrd r10,1
955
956 mtspr SPRN_SRR1,r12
957 mtspr SPRN_SRR0,r11
958 REST_4GPRS(10, r1)
959 ld r1,GPR1(r1)
960 rfid
961 b . /* prevent speculative execution */
962
963 unrecov_fer:
964 bl .save_nvgprs
965 1: addi r3,r1,STACK_FRAME_OVERHEAD
966 bl .unrecoverable_exception
967 b 1b
968
969 /*
970 * Here r13 points to the paca, r9 contains the saved CR,
971 * SRR0 and SRR1 are saved in r11 and r12,
972 * r9 - r13 are saved in paca->exgen.
973 */
974 .align 7
975 .globl data_access_common
976 data_access_common:
977 mfspr r10,SPRN_DAR
978 std r10,PACA_EXGEN+EX_DAR(r13)
979 mfspr r10,SPRN_DSISR
980 stw r10,PACA_EXGEN+EX_DSISR(r13)
981 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
982 ld r3,PACA_EXGEN+EX_DAR(r13)
983 lwz r4,PACA_EXGEN+EX_DSISR(r13)
984 li r5,0x300
985 b .do_hash_page /* Try to handle as hpte fault */
986
987 .align 7
988 .globl instruction_access_common
989 instruction_access_common:
990 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
991 ld r3,_NIP(r1)
992 andis. r4,r12,0x5820
993 li r5,0x400
994 b .do_hash_page /* Try to handle as hpte fault */
995
996 /*
997 * Here is the common SLB miss user that is used when going to virtual
998 * mode for SLB misses, that is currently not used
999 */
1000 #ifdef __DISABLED__
1001 .align 7
1002 .globl slb_miss_user_common
1003 slb_miss_user_common:
1004 mflr r10
1005 std r3,PACA_EXGEN+EX_DAR(r13)
1006 stw r9,PACA_EXGEN+EX_CCR(r13)
1007 std r10,PACA_EXGEN+EX_LR(r13)
1008 std r11,PACA_EXGEN+EX_SRR0(r13)
1009 bl .slb_allocate_user
1010
1011 ld r10,PACA_EXGEN+EX_LR(r13)
1012 ld r3,PACA_EXGEN+EX_R3(r13)
1013 lwz r9,PACA_EXGEN+EX_CCR(r13)
1014 ld r11,PACA_EXGEN+EX_SRR0(r13)
1015 mtlr r10
1016 beq- slb_miss_fault
1017
1018 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1019 beq- unrecov_user_slb
1020 mfmsr r10
1021
1022 .machine push
1023 .machine "power4"
1024 mtcrf 0x80,r9
1025 .machine pop
1026
1027 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
1028 mtmsrd r10,1
1029
1030 mtspr SRR0,r11
1031 mtspr SRR1,r12
1032
1033 ld r9,PACA_EXGEN+EX_R9(r13)
1034 ld r10,PACA_EXGEN+EX_R10(r13)
1035 ld r11,PACA_EXGEN+EX_R11(r13)
1036 ld r12,PACA_EXGEN+EX_R12(r13)
1037 ld r13,PACA_EXGEN+EX_R13(r13)
1038 rfid
1039 b .
1040
1041 slb_miss_fault:
1042 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
1043 ld r4,PACA_EXGEN+EX_DAR(r13)
1044 li r5,0
1045 std r4,_DAR(r1)
1046 std r5,_DSISR(r1)
1047 b handle_page_fault
1048
1049 unrecov_user_slb:
1050 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
1051 DISABLE_INTS
1052 bl .save_nvgprs
1053 1: addi r3,r1,STACK_FRAME_OVERHEAD
1054 bl .unrecoverable_exception
1055 b 1b
1056
1057 #endif /* __DISABLED__ */
1058
1059
1060 /*
1061 * r13 points to the PACA, r9 contains the saved CR,
1062 * r12 contain the saved SRR1, SRR0 is still ready for return
1063 * r3 has the faulting address
1064 * r9 - r13 are saved in paca->exslb.
1065 * r3 is saved in paca->slb_r3
1066 * We assume we aren't going to take any exceptions during this procedure.
1067 */
1068 _GLOBAL(slb_miss_realmode)
1069 mflr r10
1070
1071 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1072 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1073
1074 bl .slb_allocate_realmode
1075
1076 /* All done -- return from exception. */
1077
1078 ld r10,PACA_EXSLB+EX_LR(r13)
1079 ld r3,PACA_EXSLB+EX_R3(r13)
1080 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1081 #ifdef CONFIG_PPC_ISERIES
1082 BEGIN_FW_FTR_SECTION
1083 ld r11,PACALPPACAPTR(r13)
1084 ld r11,LPPACASRR0(r11) /* get SRR0 value */
1085 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1086 #endif /* CONFIG_PPC_ISERIES */
1087
1088 mtlr r10
1089
1090 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1091 beq- unrecov_slb
1092
1093 .machine push
1094 .machine "power4"
1095 mtcrf 0x80,r9
1096 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1097 .machine pop
1098
1099 #ifdef CONFIG_PPC_ISERIES
1100 BEGIN_FW_FTR_SECTION
1101 mtspr SPRN_SRR0,r11
1102 mtspr SPRN_SRR1,r12
1103 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1104 #endif /* CONFIG_PPC_ISERIES */
1105 ld r9,PACA_EXSLB+EX_R9(r13)
1106 ld r10,PACA_EXSLB+EX_R10(r13)
1107 ld r11,PACA_EXSLB+EX_R11(r13)
1108 ld r12,PACA_EXSLB+EX_R12(r13)
1109 ld r13,PACA_EXSLB+EX_R13(r13)
1110 rfid
1111 b . /* prevent speculative execution */
1112
1113 unrecov_slb:
1114 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1115 DISABLE_INTS
1116 bl .save_nvgprs
1117 1: addi r3,r1,STACK_FRAME_OVERHEAD
1118 bl .unrecoverable_exception
1119 b 1b
1120
1121 .align 7
1122 .globl hardware_interrupt_common
1123 .globl hardware_interrupt_entry
1124 hardware_interrupt_common:
1125 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1126 FINISH_NAP
1127 hardware_interrupt_entry:
1128 DISABLE_INTS
1129 bl .ppc64_runlatch_on
1130 addi r3,r1,STACK_FRAME_OVERHEAD
1131 bl .do_IRQ
1132 b .ret_from_except_lite
1133
1134 #ifdef CONFIG_PPC_970_NAP
1135 power4_fixup_nap:
1136 andc r9,r9,r10
1137 std r9,TI_LOCAL_FLAGS(r11)
1138 ld r10,_LINK(r1) /* make idle task do the */
1139 std r10,_NIP(r1) /* equivalent of a blr */
1140 blr
1141 #endif
1142
1143 .align 7
1144 .globl alignment_common
1145 alignment_common:
1146 mfspr r10,SPRN_DAR
1147 std r10,PACA_EXGEN+EX_DAR(r13)
1148 mfspr r10,SPRN_DSISR
1149 stw r10,PACA_EXGEN+EX_DSISR(r13)
1150 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1151 ld r3,PACA_EXGEN+EX_DAR(r13)
1152 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1153 std r3,_DAR(r1)
1154 std r4,_DSISR(r1)
1155 bl .save_nvgprs
1156 addi r3,r1,STACK_FRAME_OVERHEAD
1157 ENABLE_INTS
1158 bl .alignment_exception
1159 b .ret_from_except
1160
1161 .align 7
1162 .globl program_check_common
1163 program_check_common:
1164 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1165 bl .save_nvgprs
1166 addi r3,r1,STACK_FRAME_OVERHEAD
1167 ENABLE_INTS
1168 bl .program_check_exception
1169 b .ret_from_except
1170
1171 .align 7
1172 .globl fp_unavailable_common
1173 fp_unavailable_common:
1174 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1175 bne 1f /* if from user, just load it up */
1176 bl .save_nvgprs
1177 addi r3,r1,STACK_FRAME_OVERHEAD
1178 ENABLE_INTS
1179 bl .kernel_fp_unavailable_exception
1180 BUG_OPCODE
1181 1: b .load_up_fpu
1182
1183 .align 7
1184 .globl altivec_unavailable_common
1185 altivec_unavailable_common:
1186 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1187 #ifdef CONFIG_ALTIVEC
1188 BEGIN_FTR_SECTION
1189 bne .load_up_altivec /* if from user, just load it up */
1190 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1191 #endif
1192 bl .save_nvgprs
1193 addi r3,r1,STACK_FRAME_OVERHEAD
1194 ENABLE_INTS
1195 bl .altivec_unavailable_exception
1196 b .ret_from_except
1197
1198 #ifdef CONFIG_ALTIVEC
1199 /*
1200 * load_up_altivec(unused, unused, tsk)
1201 * Disable VMX for the task which had it previously,
1202 * and save its vector registers in its thread_struct.
1203 * Enables the VMX for use in the kernel on return.
1204 * On SMP we know the VMX is free, since we give it up every
1205 * switch (ie, no lazy save of the vector registers).
1206 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1207 */
1208 _STATIC(load_up_altivec)
1209 mfmsr r5 /* grab the current MSR */
1210 oris r5,r5,MSR_VEC@h
1211 mtmsrd r5 /* enable use of VMX now */
1212 isync
1213
1214 /*
1215 * For SMP, we don't do lazy VMX switching because it just gets too
1216 * horrendously complex, especially when a task switches from one CPU
1217 * to another. Instead we call giveup_altvec in switch_to.
1218 * VRSAVE isn't dealt with here, that is done in the normal context
1219 * switch code. Note that we could rely on vrsave value to eventually
1220 * avoid saving all of the VREGs here...
1221 */
1222 #ifndef CONFIG_SMP
1223 ld r3,last_task_used_altivec@got(r2)
1224 ld r4,0(r3)
1225 cmpdi 0,r4,0
1226 beq 1f
1227 /* Save VMX state to last_task_used_altivec's THREAD struct */
1228 addi r4,r4,THREAD
1229 SAVE_32VRS(0,r5,r4)
1230 mfvscr vr0
1231 li r10,THREAD_VSCR
1232 stvx vr0,r10,r4
1233 /* Disable VMX for last_task_used_altivec */
1234 ld r5,PT_REGS(r4)
1235 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1236 lis r6,MSR_VEC@h
1237 andc r4,r4,r6
1238 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1239 1:
1240 #endif /* CONFIG_SMP */
1241 /* Hack: if we get an altivec unavailable trap with VRSAVE
1242 * set to all zeros, we assume this is a broken application
1243 * that fails to set it properly, and thus we switch it to
1244 * all 1's
1245 */
1246 mfspr r4,SPRN_VRSAVE
1247 cmpdi 0,r4,0
1248 bne+ 1f
1249 li r4,-1
1250 mtspr SPRN_VRSAVE,r4
1251 1:
1252 /* enable use of VMX after return */
1253 ld r4,PACACURRENT(r13)
1254 addi r5,r4,THREAD /* Get THREAD */
1255 oris r12,r12,MSR_VEC@h
1256 std r12,_MSR(r1)
1257 li r4,1
1258 li r10,THREAD_VSCR
1259 stw r4,THREAD_USED_VR(r5)
1260 lvx vr0,r10,r5
1261 mtvscr vr0
1262 REST_32VRS(0,r4,r5)
1263 #ifndef CONFIG_SMP
1264 /* Update last_task_used_math to 'current' */
1265 subi r4,r5,THREAD /* Back to 'current' */
1266 std r4,0(r3)
1267 #endif /* CONFIG_SMP */
1268 /* restore registers and return */
1269 b fast_exception_return
1270 #endif /* CONFIG_ALTIVEC */
1271
1272 /*
1273 * Hash table stuff
1274 */
1275 .align 7
1276 _GLOBAL(do_hash_page)
1277 std r3,_DAR(r1)
1278 std r4,_DSISR(r1)
1279
1280 andis. r0,r4,0xa450 /* weird error? */
1281 bne- handle_page_fault /* if not, try to insert a HPTE */
1282 BEGIN_FTR_SECTION
1283 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1284 bne- do_ste_alloc /* If so handle it */
1285 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1286
1287 /*
1288 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1289 * accessing a userspace segment (even from the kernel). We assume
1290 * kernel addresses always have the high bit set.
1291 */
1292 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1293 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1294 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1295 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1296 ori r4,r4,1 /* add _PAGE_PRESENT */
1297 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1298
1299 /*
1300 * On iSeries, we soft-disable interrupts here, then
1301 * hard-enable interrupts so that the hash_page code can spin on
1302 * the hash_table_lock without problems on a shared processor.
1303 */
1304 DISABLE_INTS
1305
1306 /*
1307 * r3 contains the faulting address
1308 * r4 contains the required access permissions
1309 * r5 contains the trap number
1310 *
1311 * at return r3 = 0 for success
1312 */
1313 bl .hash_page /* build HPTE if possible */
1314 cmpdi r3,0 /* see if hash_page succeeded */
1315
1316 #ifdef DO_SOFT_DISABLE
1317 BEGIN_FW_FTR_SECTION
1318 /*
1319 * If we had interrupts soft-enabled at the point where the
1320 * DSI/ISI occurred, and an interrupt came in during hash_page,
1321 * handle it now.
1322 * We jump to ret_from_except_lite rather than fast_exception_return
1323 * because ret_from_except_lite will check for and handle pending
1324 * interrupts if necessary.
1325 */
1326 beq 13f
1327 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1328 #endif
1329 BEGIN_FW_FTR_SECTION
1330 /*
1331 * Here we have interrupts hard-disabled, so it is sufficient
1332 * to restore paca->{soft,hard}_enable and get out.
1333 */
1334 beq fast_exc_return_irq /* Return from exception on success */
1335 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1336
1337 /* For a hash failure, we don't bother re-enabling interrupts */
1338 ble- 12f
1339
1340 /*
1341 * hash_page couldn't handle it, set soft interrupt enable back
1342 * to what it was before the trap. Note that .local_irq_restore
1343 * handles any interrupts pending at this point.
1344 */
1345 ld r3,SOFTE(r1)
1346 bl .local_irq_restore
1347 b 11f
1348
1349 /* Here we have a page fault that hash_page can't handle. */
1350 handle_page_fault:
1351 ENABLE_INTS
1352 11: ld r4,_DAR(r1)
1353 ld r5,_DSISR(r1)
1354 addi r3,r1,STACK_FRAME_OVERHEAD
1355 bl .do_page_fault
1356 cmpdi r3,0
1357 beq+ 13f
1358 bl .save_nvgprs
1359 mr r5,r3
1360 addi r3,r1,STACK_FRAME_OVERHEAD
1361 lwz r4,_DAR(r1)
1362 bl .bad_page_fault
1363 b .ret_from_except
1364
1365 13: b .ret_from_except_lite
1366
1367 /* We have a page fault that hash_page could handle but HV refused
1368 * the PTE insertion
1369 */
1370 12: bl .save_nvgprs
1371 addi r3,r1,STACK_FRAME_OVERHEAD
1372 lwz r4,_DAR(r1)
1373 bl .low_hash_fault
1374 b .ret_from_except
1375
1376 /* here we have a segment miss */
1377 do_ste_alloc:
1378 bl .ste_allocate /* try to insert stab entry */
1379 cmpdi r3,0
1380 bne- handle_page_fault
1381 b fast_exception_return
1382
1383 /*
1384 * r13 points to the PACA, r9 contains the saved CR,
1385 * r11 and r12 contain the saved SRR0 and SRR1.
1386 * r9 - r13 are saved in paca->exslb.
1387 * We assume we aren't going to take any exceptions during this procedure.
1388 * We assume (DAR >> 60) == 0xc.
1389 */
1390 .align 7
1391 _GLOBAL(do_stab_bolted)
1392 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1393 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1394
1395 /* Hash to the primary group */
1396 ld r10,PACASTABVIRT(r13)
1397 mfspr r11,SPRN_DAR
1398 srdi r11,r11,28
1399 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1400
1401 /* Calculate VSID */
1402 /* This is a kernel address, so protovsid = ESID */
1403 ASM_VSID_SCRAMBLE(r11, r9)
1404 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1405
1406 /* Search the primary group for a free entry */
1407 1: ld r11,0(r10) /* Test valid bit of the current ste */
1408 andi. r11,r11,0x80
1409 beq 2f
1410 addi r10,r10,16
1411 andi. r11,r10,0x70
1412 bne 1b
1413
1414 /* Stick for only searching the primary group for now. */
1415 /* At least for now, we use a very simple random castout scheme */
1416 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1417 mftb r11
1418 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1419 ori r11,r11,0x10
1420
1421 /* r10 currently points to an ste one past the group of interest */
1422 /* make it point to the randomly selected entry */
1423 subi r10,r10,128
1424 or r10,r10,r11 /* r10 is the entry to invalidate */
1425
1426 isync /* mark the entry invalid */
1427 ld r11,0(r10)
1428 rldicl r11,r11,56,1 /* clear the valid bit */
1429 rotldi r11,r11,8
1430 std r11,0(r10)
1431 sync
1432
1433 clrrdi r11,r11,28 /* Get the esid part of the ste */
1434 slbie r11
1435
1436 2: std r9,8(r10) /* Store the vsid part of the ste */
1437 eieio
1438
1439 mfspr r11,SPRN_DAR /* Get the new esid */
1440 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1441 ori r11,r11,0x90 /* Turn on valid and kp */
1442 std r11,0(r10) /* Put new entry back into the stab */
1443
1444 sync
1445
1446 /* All done -- return from exception. */
1447 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1448 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1449
1450 andi. r10,r12,MSR_RI
1451 beq- unrecov_slb
1452
1453 mtcrf 0x80,r9 /* restore CR */
1454
1455 mfmsr r10
1456 clrrdi r10,r10,2
1457 mtmsrd r10,1
1458
1459 mtspr SPRN_SRR0,r11
1460 mtspr SPRN_SRR1,r12
1461 ld r9,PACA_EXSLB+EX_R9(r13)
1462 ld r10,PACA_EXSLB+EX_R10(r13)
1463 ld r11,PACA_EXSLB+EX_R11(r13)
1464 ld r12,PACA_EXSLB+EX_R12(r13)
1465 ld r13,PACA_EXSLB+EX_R13(r13)
1466 rfid
1467 b . /* prevent speculative execution */
1468
1469 /*
1470 * Space for CPU0's segment table.
1471 *
1472 * On iSeries, the hypervisor must fill in at least one entry before
1473 * we get control (with relocate on). The address is given to the hv
1474 * as a page number (see xLparMap below), so this must be at a
1475 * fixed address (the linker can't compute (u64)&initial_stab >>
1476 * PAGE_SHIFT).
1477 */
1478 . = STAB0_OFFSET /* 0x6000 */
1479 .globl initial_stab
1480 initial_stab:
1481 .space 4096
1482
1483 /*
1484 * Data area reserved for FWNMI option.
1485 * This address (0x7000) is fixed by the RPA.
1486 */
1487 .= 0x7000
1488 .globl fwnmi_data_area
1489 fwnmi_data_area:
1490
1491 /* iSeries does not use the FWNMI stuff, so it is safe to put
1492 * this here, even if we later allow kernels that will boot on
1493 * both pSeries and iSeries */
1494 #ifdef CONFIG_PPC_ISERIES
1495 . = LPARMAP_PHYS
1496 .globl xLparMap
1497 xLparMap:
1498 .quad HvEsidsToMap /* xNumberEsids */
1499 .quad HvRangesToMap /* xNumberRanges */
1500 .quad STAB0_PAGE /* xSegmentTableOffs */
1501 .zero 40 /* xRsvd */
1502 /* xEsids (HvEsidsToMap entries of 2 quads) */
1503 .quad PAGE_OFFSET_ESID /* xKernelEsid */
1504 .quad PAGE_OFFSET_VSID /* xKernelVsid */
1505 .quad VMALLOC_START_ESID /* xKernelEsid */
1506 .quad VMALLOC_START_VSID /* xKernelVsid */
1507 /* xRanges (HvRangesToMap entries of 3 quads) */
1508 .quad HvPagesToMap /* xPages */
1509 .quad 0 /* xOffset */
1510 .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
1511
1512 #endif /* CONFIG_PPC_ISERIES */
1513
1514 . = 0x8000
1515
1516 /*
1517 * On pSeries and most other platforms, secondary processors spin
1518 * in the following code.
1519 * At entry, r3 = this processor's number (physical cpu id)
1520 */
1521 _GLOBAL(generic_secondary_smp_init)
1522 mr r24,r3
1523
1524 /* turn on 64-bit mode */
1525 bl .enable_64b_mode
1526
1527 /* Set up a paca value for this processor. Since we have the
1528 * physical cpu id in r24, we need to search the pacas to find
1529 * which logical id maps to our physical one.
1530 */
1531 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1532 li r5,0 /* logical cpu id */
1533 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1534 cmpw r6,r24 /* Compare to our id */
1535 beq 2f
1536 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1537 addi r5,r5,1
1538 cmpwi r5,NR_CPUS
1539 blt 1b
1540
1541 mr r3,r24 /* not found, copy phys to r3 */
1542 b .kexec_wait /* next kernel might do better */
1543
1544 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1545 /* From now on, r24 is expected to be logical cpuid */
1546 mr r24,r5
1547 3: HMT_LOW
1548 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1549 /* start. */
1550 sync
1551
1552 #ifndef CONFIG_SMP
1553 b 3b /* Never go on non-SMP */
1554 #else
1555 cmpwi 0,r23,0
1556 beq 3b /* Loop until told to go */
1557
1558 /* See if we need to call a cpu state restore handler */
1559 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1560 ld r23,0(r23)
1561 ld r23,CPU_SPEC_RESTORE(r23)
1562 cmpdi 0,r23,0
1563 beq 4f
1564 ld r23,0(r23)
1565 mtctr r23
1566 bctrl
1567
1568 4: /* Create a temp kernel stack for use before relocation is on. */
1569 ld r1,PACAEMERGSP(r13)
1570 subi r1,r1,STACK_FRAME_OVERHEAD
1571
1572 b __secondary_start
1573 #endif
1574
1575 _STATIC(__mmu_off)
1576 mfmsr r3
1577 andi. r0,r3,MSR_IR|MSR_DR
1578 beqlr
1579 andc r3,r3,r0
1580 mtspr SPRN_SRR0,r4
1581 mtspr SPRN_SRR1,r3
1582 sync
1583 rfid
1584 b . /* prevent speculative execution */
1585
1586
1587 /*
1588 * Here is our main kernel entry point. We support currently 2 kind of entries
1589 * depending on the value of r5.
1590 *
1591 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1592 * in r3...r7
1593 *
1594 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1595 * DT block, r4 is a physical pointer to the kernel itself
1596 *
1597 */
1598 _GLOBAL(__start_initialization_multiplatform)
1599 /*
1600 * Are we booted from a PROM Of-type client-interface ?
1601 */
1602 cmpldi cr0,r5,0
1603 beq 1f
1604 b .__boot_from_prom /* yes -> prom */
1605 1:
1606 /* Save parameters */
1607 mr r31,r3
1608 mr r30,r4
1609
1610 /* Make sure we are running in 64 bits mode */
1611 bl .enable_64b_mode
1612
1613 /* Setup some critical 970 SPRs before switching MMU off */
1614 mfspr r0,SPRN_PVR
1615 srwi r0,r0,16
1616 cmpwi r0,0x39 /* 970 */
1617 beq 1f
1618 cmpwi r0,0x3c /* 970FX */
1619 beq 1f
1620 cmpwi r0,0x44 /* 970MP */
1621 beq 1f
1622 cmpwi r0,0x45 /* 970GX */
1623 bne 2f
1624 1: bl .__cpu_preinit_ppc970
1625 2:
1626
1627 /* Switch off MMU if not already */
1628 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1629 add r4,r4,r30
1630 bl .__mmu_off
1631 b .__after_prom_start
1632
1633 _INIT_STATIC(__boot_from_prom)
1634 /* Save parameters */
1635 mr r31,r3
1636 mr r30,r4
1637 mr r29,r5
1638 mr r28,r6
1639 mr r27,r7
1640
1641 /*
1642 * Align the stack to 16-byte boundary
1643 * Depending on the size and layout of the ELF sections in the initial
1644 * boot binary, the stack pointer will be unalignet on PowerMac
1645 */
1646 rldicr r1,r1,0,59
1647
1648 /* Make sure we are running in 64 bits mode */
1649 bl .enable_64b_mode
1650
1651 /* put a relocation offset into r3 */
1652 bl .reloc_offset
1653
1654 LOAD_REG_IMMEDIATE(r2,__toc_start)
1655 addi r2,r2,0x4000
1656 addi r2,r2,0x4000
1657
1658 /* Relocate the TOC from a virt addr to a real addr */
1659 add r2,r2,r3
1660
1661 /* Restore parameters */
1662 mr r3,r31
1663 mr r4,r30
1664 mr r5,r29
1665 mr r6,r28
1666 mr r7,r27
1667
1668 /* Do all of the interaction with OF client interface */
1669 bl .prom_init
1670 /* We never return */
1671 trap
1672
1673 _STATIC(__after_prom_start)
1674
1675 /*
1676 * We need to run with __start at physical address PHYSICAL_START.
1677 * This will leave some code in the first 256B of
1678 * real memory, which are reserved for software use.
1679 * The remainder of the first page is loaded with the fixed
1680 * interrupt vectors. The next two pages are filled with
1681 * unknown exception placeholders.
1682 *
1683 * Note: This process overwrites the OF exception vectors.
1684 * r26 == relocation offset
1685 * r27 == KERNELBASE
1686 */
1687 bl .reloc_offset
1688 mr r26,r3
1689 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1690
1691 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1692
1693 // XXX FIXME: Use phys returned by OF (r30)
1694 add r4,r27,r26 /* source addr */
1695 /* current address of _start */
1696 /* i.e. where we are running */
1697 /* the source addr */
1698
1699 cmpdi r4,0 /* In some cases the loader may */
1700 bne 1f
1701 b .start_here_multiplatform /* have already put us at zero */
1702 /* so we can skip the copy. */
1703 1: LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1704 sub r5,r5,r27
1705
1706 li r6,0x100 /* Start offset, the first 0x100 */
1707 /* bytes were copied earlier. */
1708
1709 bl .copy_and_flush /* copy the first n bytes */
1710 /* this includes the code being */
1711 /* executed here. */
1712
1713 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1714 mtctr r0 /* that we just made/relocated */
1715 bctr
1716
1717 4: LOAD_REG_IMMEDIATE(r5,klimit)
1718 add r5,r5,r26
1719 ld r5,0(r5) /* get the value of klimit */
1720 sub r5,r5,r27
1721 bl .copy_and_flush /* copy the rest */
1722 b .start_here_multiplatform
1723
1724 /*
1725 * Copy routine used to copy the kernel to start at physical address 0
1726 * and flush and invalidate the caches as needed.
1727 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1728 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1729 *
1730 * Note: this routine *only* clobbers r0, r6 and lr
1731 */
1732 _GLOBAL(copy_and_flush)
1733 addi r5,r5,-8
1734 addi r6,r6,-8
1735 4: li r0,8 /* Use the smallest common */
1736 /* denominator cache line */
1737 /* size. This results in */
1738 /* extra cache line flushes */
1739 /* but operation is correct. */
1740 /* Can't get cache line size */
1741 /* from NACA as it is being */
1742 /* moved too. */
1743
1744 mtctr r0 /* put # words/line in ctr */
1745 3: addi r6,r6,8 /* copy a cache line */
1746 ldx r0,r6,r4
1747 stdx r0,r6,r3
1748 bdnz 3b
1749 dcbst r6,r3 /* write it to memory */
1750 sync
1751 icbi r6,r3 /* flush the icache line */
1752 cmpld 0,r6,r5
1753 blt 4b
1754 sync
1755 addi r5,r5,8
1756 addi r6,r6,8
1757 blr
1758
1759 .align 8
1760 copy_to_here:
1761
1762 #ifdef CONFIG_SMP
1763 #ifdef CONFIG_PPC_PMAC
1764 /*
1765 * On PowerMac, secondary processors starts from the reset vector, which
1766 * is temporarily turned into a call to one of the functions below.
1767 */
1768 .section ".text";
1769 .align 2 ;
1770
1771 .globl __secondary_start_pmac_0
1772 __secondary_start_pmac_0:
1773 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1774 li r24,0
1775 b 1f
1776 li r24,1
1777 b 1f
1778 li r24,2
1779 b 1f
1780 li r24,3
1781 1:
1782
1783 _GLOBAL(pmac_secondary_start)
1784 /* turn on 64-bit mode */
1785 bl .enable_64b_mode
1786
1787 /* Copy some CPU settings from CPU 0 */
1788 bl .__restore_cpu_ppc970
1789
1790 /* pSeries do that early though I don't think we really need it */
1791 mfmsr r3
1792 ori r3,r3,MSR_RI
1793 mtmsrd r3 /* RI on */
1794
1795 /* Set up a paca value for this processor. */
1796 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1797 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1798 add r13,r13,r4 /* for this processor. */
1799 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1800
1801 /* Create a temp kernel stack for use before relocation is on. */
1802 ld r1,PACAEMERGSP(r13)
1803 subi r1,r1,STACK_FRAME_OVERHEAD
1804
1805 b __secondary_start
1806
1807 #endif /* CONFIG_PPC_PMAC */
1808
1809 /*
1810 * This function is called after the master CPU has released the
1811 * secondary processors. The execution environment is relocation off.
1812 * The paca for this processor has the following fields initialized at
1813 * this point:
1814 * 1. Processor number
1815 * 2. Segment table pointer (virtual address)
1816 * On entry the following are set:
1817 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1818 * r24 = cpu# (in Linux terms)
1819 * r13 = paca virtual address
1820 * SPRG3 = paca virtual address
1821 */
1822 .globl __secondary_start
1823 __secondary_start:
1824 /* Set thread priority to MEDIUM */
1825 HMT_MEDIUM
1826
1827 /* Load TOC */
1828 ld r2,PACATOC(r13)
1829
1830 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1831 bl .early_setup_secondary
1832
1833 /* Initialize the kernel stack. Just a repeat for iSeries. */
1834 LOAD_REG_ADDR(r3, current_set)
1835 sldi r28,r24,3 /* get current_set[cpu#] */
1836 ldx r1,r3,r28
1837 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1838 std r1,PACAKSAVE(r13)
1839
1840 /* Clear backchain so we get nice backtraces */
1841 li r7,0
1842 mtlr r7
1843
1844 /* enable MMU and jump to start_secondary */
1845 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1846 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1847 #ifdef CONFIG_PPC_ISERIES
1848 BEGIN_FW_FTR_SECTION
1849 ori r4,r4,MSR_EE
1850 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1851 #endif
1852 BEGIN_FW_FTR_SECTION
1853 stb r7,PACASOFTIRQEN(r13)
1854 stb r7,PACAHARDIRQEN(r13)
1855 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1856
1857 mtspr SPRN_SRR0,r3
1858 mtspr SPRN_SRR1,r4
1859 rfid
1860 b . /* prevent speculative execution */
1861
1862 /*
1863 * Running with relocation on at this point. All we want to do is
1864 * zero the stack back-chain pointer before going into C code.
1865 */
1866 _GLOBAL(start_secondary_prolog)
1867 li r3,0
1868 std r3,0(r1) /* Zero the stack frame pointer */
1869 bl .start_secondary
1870 b .
1871 #endif
1872
1873 /*
1874 * This subroutine clobbers r11 and r12
1875 */
1876 _GLOBAL(enable_64b_mode)
1877 mfmsr r11 /* grab the current MSR */
1878 li r12,1
1879 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1880 or r11,r11,r12
1881 li r12,1
1882 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1883 or r11,r11,r12
1884 mtmsrd r11
1885 isync
1886 blr
1887
1888 /*
1889 * This is where the main kernel code starts.
1890 */
1891 _INIT_STATIC(start_here_multiplatform)
1892 /* get a new offset, now that the kernel has moved. */
1893 bl .reloc_offset
1894 mr r26,r3
1895
1896 /* Clear out the BSS. It may have been done in prom_init,
1897 * already but that's irrelevant since prom_init will soon
1898 * be detached from the kernel completely. Besides, we need
1899 * to clear it now for kexec-style entry.
1900 */
1901 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1902 LOAD_REG_IMMEDIATE(r8,__bss_start)
1903 sub r11,r11,r8 /* bss size */
1904 addi r11,r11,7 /* round up to an even double word */
1905 rldicl. r11,r11,61,3 /* shift right by 3 */
1906 beq 4f
1907 addi r8,r8,-8
1908 li r0,0
1909 mtctr r11 /* zero this many doublewords */
1910 3: stdu r0,8(r8)
1911 bdnz 3b
1912 4:
1913
1914 mfmsr r6
1915 ori r6,r6,MSR_RI
1916 mtmsrd r6 /* RI on */
1917
1918 /* The following gets the stack and TOC set up with the regs */
1919 /* pointing to the real addr of the kernel stack. This is */
1920 /* all done to support the C function call below which sets */
1921 /* up the htab. This is done because we have relocated the */
1922 /* kernel but are still running in real mode. */
1923
1924 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1925 add r3,r3,r26
1926
1927 /* set up a stack pointer (physical address) */
1928 addi r1,r3,THREAD_SIZE
1929 li r0,0
1930 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1931
1932 /* set up the TOC (physical address) */
1933 LOAD_REG_IMMEDIATE(r2,__toc_start)
1934 addi r2,r2,0x4000
1935 addi r2,r2,0x4000
1936 add r2,r2,r26
1937
1938 /* Do very early kernel initializations, including initial hash table,
1939 * stab and slb setup before we turn on relocation. */
1940
1941 /* Restore parameters passed from prom_init/kexec */
1942 mr r3,r31
1943 bl .early_setup
1944
1945 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1946 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1947 mtspr SPRN_SRR0,r3
1948 mtspr SPRN_SRR1,r4
1949 rfid
1950 b . /* prevent speculative execution */
1951
1952 /* This is where all platforms converge execution */
1953 _INIT_GLOBAL(start_here_common)
1954 /* relocation is on at this point */
1955
1956 /* The following code sets up the SP and TOC now that we are */
1957 /* running with translation enabled. */
1958
1959 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1960
1961 /* set up the stack */
1962 addi r1,r3,THREAD_SIZE
1963 li r0,0
1964 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1965
1966 /* ptr to current */
1967 LOAD_REG_IMMEDIATE(r4, init_task)
1968 std r4,PACACURRENT(r13)
1969
1970 /* Load the TOC */
1971 ld r2,PACATOC(r13)
1972 std r1,PACAKSAVE(r13)
1973
1974 bl .setup_system
1975
1976 /* Load up the kernel context */
1977 5:
1978 li r5,0
1979 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
1980 #ifdef CONFIG_PPC_ISERIES
1981 BEGIN_FW_FTR_SECTION
1982 mfmsr r5
1983 ori r5,r5,MSR_EE /* Hard Enabled */
1984 mtmsrd r5
1985 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1986 #endif
1987 BEGIN_FW_FTR_SECTION
1988 stb r5,PACAHARDIRQEN(r13)
1989 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1990
1991 bl .start_kernel
1992
1993 /* Not reached */
1994 BUG_OPCODE
1995
1996 /*
1997 * We put a few things here that have to be page-aligned.
1998 * This stuff goes at the beginning of the bss, which is page-aligned.
1999 */
2000 .section ".bss"
2001
2002 .align PAGE_SHIFT
2003
2004 .globl empty_zero_page
2005 empty_zero_page:
2006 .space PAGE_SIZE
2007
2008 .globl swapper_pg_dir
2009 swapper_pg_dir:
2010 .space PAGE_SIZE
2011
2012 /*
2013 * This space gets a copy of optional info passed to us by the bootstrap
2014 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2015 */
2016 .globl cmd_line
2017 cmd_line:
2018 .space COMMAND_LINE_SIZE
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