arch/powerpc/kernel/head_8xx.S

   1 /*
   2  *  PowerPC version
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
   5  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   6  *  Low-level exception handlers and MMU support
   7  *  rewritten by Paul Mackerras.
   8  *    Copyright (C) 1996 Paul Mackerras.
   9  *  MPC8xx modifications by Dan Malek
  10  *    Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
  11  *
  12  *  This file contains low-level support and setup for PowerPC 8xx
  13  *  embedded processors, including trap and interrupt dispatch.
  14  *
  15  *  This program is free software; you can redistribute it and/or
  16  *  modify it under the terms of the GNU General Public License
  17  *  as published by the Free Software Foundation; either version
  18  *  2 of the License, or (at your option) any later version.
  19  *
  20  */
  21
  22 #include <linux/init.h>
  23 #include <asm/processor.h>
  24 #include <asm/page.h>
  25 #include <asm/mmu.h>
  26 #include <asm/cache.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/cputable.h>
  29 #include <asm/thread_info.h>
  30 #include <asm/ppc_asm.h>
  31 #include <asm/asm-offsets.h>
  32 #include <asm/ptrace.h>
  33 #include <asm/fixmap.h>
  34
  35 /* Macro to make the code more readable. */
  36 #ifdef CONFIG_8xx_CPU6
  37 #define SPRN_MI_TWC_ADDR        0x2b80
  38 #define SPRN_MI_RPN_ADDR        0x2d80
  39 #define SPRN_MD_TWC_ADDR        0x3b80
  40 #define SPRN_MD_RPN_ADDR        0x3d80
  41
  42 #define MTSPR_CPU6(spr, reg, treg)      \
  43         li      treg, spr##_ADDR;       \
  44         stw     treg, 12(r0);           \
  45         lwz     treg, 12(r0);           \
  46         mtspr   spr, reg
  47 #else
  48 #define MTSPR_CPU6(spr, reg, treg)      \
  49         mtspr   spr, reg
  50 #endif
  51
  52 /* Macro to test if an address is a kernel address */
  53 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
  54 #define IS_KERNEL(tmp, addr)            \
  55         andis.  tmp, addr, 0x8000       /* Address >= 0x80000000 */
  56 #define BRANCH_UNLESS_KERNEL(label)     beq     label
  57 #else
  58 #define IS_KERNEL(tmp, addr)            \
  59         rlwinm  tmp, addr, 16, 16, 31;  \
  60         cmpli   cr0, tmp, PAGE_OFFSET >> 16
  61 #define BRANCH_UNLESS_KERNEL(label)     blt     label
  62 #endif
  63
  64
  65 /*
  66  * Value for the bits that have fixed value in RPN entries.
  67  * Also used for tagging DAR for DTLBerror.
  68  */
  69 #ifdef CONFIG_PPC_16K_PAGES
  70 #define RPN_PATTERN     (0x00f0 | MD_SPS16K)
  71 #else
  72 #define RPN_PATTERN     0x00f0
  73 #endif
  74
  75         __HEAD
  76 _ENTRY(_stext);
  77 _ENTRY(_start);
  78
  79 /* MPC8xx
  80  * This port was done on an MBX board with an 860.  Right now I only
  81  * support an ELF compressed (zImage) boot from EPPC-Bug because the
  82  * code there loads up some registers before calling us:
  83  *   r3: ptr to board info data
  84  *   r4: initrd_start or if no initrd then 0
  85  *   r5: initrd_end - unused if r4 is 0
  86  *   r6: Start of command line string
  87  *   r7: End of command line string
  88  *
  89  * I decided to use conditional compilation instead of checking PVR and
  90  * adding more processor specific branches around code I don't need.
  91  * Since this is an embedded processor, I also appreciate any memory
  92  * savings I can get.
  93  *
  94  * The MPC8xx does not have any BATs, but it supports large page sizes.
  95  * We first initialize the MMU to support 8M byte pages, then load one
  96  * entry into each of the instruction and data TLBs to map the first
  97  * 8M 1:1.  I also mapped an additional I/O space 1:1 so we can get to
  98  * the "internal" processor registers before MMU_init is called.
  99  *
 100  *      -- Dan
 101  */
 102         .globl  __start
 103 __start:
 104         mr      r31,r3                  /* save device tree ptr */
 105
 106         /* We have to turn on the MMU right away so we get cache modes
 107          * set correctly.
 108          */
 109         bl      initial_mmu
 110
 111 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
 112  * ready to work.
 113  */
 114
 115 turn_on_mmu:
 116         mfmsr   r0
 117         ori     r0,r0,MSR_DR|MSR_IR
 118         mtspr   SPRN_SRR1,r0
 119         lis     r0,start_here@h
 120         ori     r0,r0,start_here@l
 121         mtspr   SPRN_SRR0,r0
 122         SYNC
 123         rfi                             /* enables MMU */
 124
 125 /*
 126  * Exception entry code.  This code runs with address translation
 127  * turned off, i.e. using physical addresses.
 128  * We assume sprg3 has the physical address of the current
 129  * task's thread_struct.
 130  */
 131 #define EXCEPTION_PROLOG        \
 132         EXCEPTION_PROLOG_0;     \
 133         mfcr    r10;            \
 134         EXCEPTION_PROLOG_1;     \
 135         EXCEPTION_PROLOG_2
 136
 137 #define EXCEPTION_PROLOG_0      \
 138         mtspr   SPRN_SPRG_SCRATCH0,r10; \
 139         mtspr   SPRN_SPRG_SCRATCH1,r11
 140
 141 #define EXCEPTION_PROLOG_1      \
 142         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel */ \
 143         andi.   r11,r11,MSR_PR; \
 144         tophys(r11,r1);                 /* use tophys(r1) if kernel */ \
 145         beq     1f;             \
 146         mfspr   r11,SPRN_SPRG_THREAD;   \
 147         lwz     r11,THREAD_INFO-THREAD(r11);    \
 148         addi    r11,r11,THREAD_SIZE;    \
 149         tophys(r11,r11);        \
 150 1:      subi    r11,r11,INT_FRAME_SIZE  /* alloc exc. frame */
 151
 152
 153 #define EXCEPTION_PROLOG_2      \
 154         stw     r10,_CCR(r11);          /* save registers */ \
 155         stw     r12,GPR12(r11); \
 156         stw     r9,GPR9(r11);   \
 157         mfspr   r10,SPRN_SPRG_SCRATCH0; \
 158         stw     r10,GPR10(r11); \
 159         mfspr   r12,SPRN_SPRG_SCRATCH1; \
 160         stw     r12,GPR11(r11); \
 161         mflr    r10;            \
 162         stw     r10,_LINK(r11); \
 163         mfspr   r12,SPRN_SRR0;  \
 164         mfspr   r9,SPRN_SRR1;   \
 165         stw     r1,GPR1(r11);   \
 166         stw     r1,0(r11);      \
 167         tovirt(r1,r11);                 /* set new kernel sp */ \
 168         li      r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
 169         MTMSRD(r10);                    /* (except for mach check in rtas) */ \
 170         stw     r0,GPR0(r11);   \
 171         SAVE_4GPRS(3, r11);     \
 172         SAVE_2GPRS(7, r11)
 173
 174 /*
 175  * Exception exit code.
 176  */
 177 #define EXCEPTION_EPILOG_0      \
 178         mfspr   r10,SPRN_SPRG_SCRATCH0; \
 179         mfspr   r11,SPRN_SPRG_SCRATCH1
 180
 181 /*
 182  * Note: code which follows this uses cr0.eq (set if from kernel),
 183  * r11, r12 (SRR0), and r9 (SRR1).
 184  *
 185  * Note2: once we have set r1 we are in a position to take exceptions
 186  * again, and we could thus set MSR:RI at that point.
 187  */
 188
 189 /*
 190  * Exception vectors.
 191  */
 192 #define EXCEPTION(n, label, hdlr, xfer)         \
 193         . = n;                                  \
 194 label:                                          \
 195         EXCEPTION_PROLOG;                       \
 196         addi    r3,r1,STACK_FRAME_OVERHEAD;     \
 197         xfer(n, hdlr)
 198
 199 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret)     \
 200         li      r10,trap;                                       \
 201         stw     r10,_TRAP(r11);                                 \
 202         li      r10,MSR_KERNEL;                                 \
 203         copyee(r10, r9);                                        \
 204         bl      tfer;                                           \
 205 i##n:                                                           \
 206         .long   hdlr;                                           \
 207         .long   ret
 208
 209 #define COPY_EE(d, s)           rlwimi d,s,0,16,16
 210 #define NOCOPY(d, s)
 211
 212 #define EXC_XFER_STD(n, hdlr)           \
 213         EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
 214                           ret_from_except_full)
 215
 216 #define EXC_XFER_LITE(n, hdlr)          \
 217         EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
 218                           ret_from_except)
 219
 220 #define EXC_XFER_EE(n, hdlr)            \
 221         EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
 222                           ret_from_except_full)
 223
 224 #define EXC_XFER_EE_LITE(n, hdlr)       \
 225         EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
 226                           ret_from_except)
 227
 228 /* System reset */
 229         EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
 230
 231 /* Machine check */
 232         . = 0x200
 233 MachineCheck:
 234         EXCEPTION_PROLOG
 235         mfspr r4,SPRN_DAR
 236         stw r4,_DAR(r11)
 237         li r5,RPN_PATTERN
 238         mtspr SPRN_DAR,r5       /* Tag DAR, to be used in DTLB Error */
 239         mfspr r5,SPRN_DSISR
 240         stw r5,_DSISR(r11)
 241         addi r3,r1,STACK_FRAME_OVERHEAD
 242         EXC_XFER_STD(0x200, machine_check_exception)
 243
 244 /* Data access exception.
 245  * This is "never generated" by the MPC8xx.
 246  */
 247         . = 0x300
 248 DataAccess:
 249
 250 /* Instruction access exception.
 251  * This is "never generated" by the MPC8xx.
 252  */
 253         . = 0x400
 254 InstructionAccess:
 255
 256 /* External interrupt */
 257         EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
 258
 259 /* Alignment exception */
 260         . = 0x600
 261 Alignment:
 262         EXCEPTION_PROLOG
 263         mfspr   r4,SPRN_DAR
 264         stw     r4,_DAR(r11)
 265         li      r5,RPN_PATTERN
 266         mtspr   SPRN_DAR,r5     /* Tag DAR, to be used in DTLB Error */
 267         mfspr   r5,SPRN_DSISR
 268         stw     r5,_DSISR(r11)
 269         addi    r3,r1,STACK_FRAME_OVERHEAD
 270         EXC_XFER_EE(0x600, alignment_exception)
 271
 272 /* Program check exception */
 273         EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
 274
 275 /* No FPU on MPC8xx.  This exception is not supposed to happen.
 276 */
 277         EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
 278
 279 /* Decrementer */
 280         EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
 281
 282         EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
 283         EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
 284
 285 /* System call */
 286         . = 0xc00
 287 SystemCall:
 288         EXCEPTION_PROLOG
 289         EXC_XFER_EE_LITE(0xc00, DoSyscall)
 290
 291 /* Single step - not used on 601 */
 292         EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
 293         EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
 294         EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
 295
 296 /* On the MPC8xx, this is a software emulation interrupt.  It occurs
 297  * for all unimplemented and illegal instructions.
 298  */
 299         EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
 300
 301         . = 0x1100
 302 /*
 303  * For the MPC8xx, this is a software tablewalk to load the instruction
 304  * TLB.  The task switch loads the M_TW register with the pointer to the first
 305  * level table.
 306  * If we discover there is no second level table (value is zero) or if there
 307  * is an invalid pte, we load that into the TLB, which causes another fault
 308  * into the TLB Error interrupt where we can handle such problems.
 309  * We have to use the MD_xxx registers for the tablewalk because the
 310  * equivalent MI_xxx registers only perform the attribute functions.
 311  */
 312
 313 #ifdef CONFIG_8xx_CPU15
 314 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)      \
 315         addi    tmp, addr, PAGE_SIZE;   \
 316         tlbie   tmp;                    \
 317         addi    tmp, addr, -PAGE_SIZE;  \
 318         tlbie   tmp
 319 #else
 320 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
 321 #endif
 322
 323 InstructionTLBMiss:
 324 #if defined(CONFIG_8xx_CPU6) || defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
 325         mtspr   SPRN_SPRG_SCRATCH2, r3
 326 #endif
 327         EXCEPTION_PROLOG_0
 328
 329         /* If we are faulting a kernel address, we have to use the
 330          * kernel page tables.
 331          */
 332         mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
 333         INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
 334 #if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
 335         /* Only modules will cause ITLB Misses as we always
 336          * pin the first 8MB of kernel memory */
 337         mfcr    r3
 338         IS_KERNEL(r11, r10)
 339 #endif
 340         mfspr   r11, SPRN_M_TW  /* Get level 1 table */
 341 #if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
 342         BRANCH_UNLESS_KERNEL(3f)
 343         lis     r11, (swapper_pg_dir-PAGE_OFFSET)@ha
 344 3:
 345         mtcr    r3
 346 #endif
 347         /* Insert level 1 index */
 348         rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
 349         lwz     r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)        /* Get the level 1 entry */
 350
 351         /* Extract level 2 index */
 352         rlwinm  r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
 353         rlwimi  r10, r11, 0, 0, 32 - PAGE_SHIFT - 1     /* Add level 2 base */
 354         lwz     r10, 0(r10)     /* Get the pte */
 355
 356         /* Insert the APG into the TWC from the Linux PTE. */
 357         rlwimi  r11, r10, 0, 25, 26
 358         /* Load the MI_TWC with the attributes for this "segment." */
 359         MTSPR_CPU6(SPRN_MI_TWC, r11, r3)        /* Set segment attributes */
 360
 361 #ifdef CONFIG_SWAP
 362         rlwinm  r11, r10, 32-5, _PAGE_PRESENT
 363         and     r11, r11, r10
 364         rlwimi  r10, r11, 0, _PAGE_PRESENT
 365 #endif
 366         li      r11, RPN_PATTERN
 367         /* The Linux PTE won't go exactly into the MMU TLB.
 368          * Software indicator bits 20-23 and 28 must be clear.
 369          * Software indicator bits 24, 25, 26, and 27 must be
 370          * set.  All other Linux PTE bits control the behavior
 371          * of the MMU.
 372          */
 373         rlwimi  r10, r11, 0, 0x0ff8     /* Set 24-27, clear 20-23,28 */
 374         MTSPR_CPU6(SPRN_MI_RPN, r10, r3)        /* Update TLB entry */
 375
 376         /* Restore registers */
 377 #if defined(CONFIG_8xx_CPU6) || defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
 378         mfspr   r3, SPRN_SPRG_SCRATCH2
 379 #endif
 380         EXCEPTION_EPILOG_0
 381         rfi
 382
 383         . = 0x1200
 384 DataStoreTLBMiss:
 385         EXCEPTION_PROLOG_0
 386         mfcr    r10
 387
 388         /* If we are faulting a kernel address, we have to use the
 389          * kernel page tables.
 390          */
 391         mfspr   r11, SPRN_MD_EPN
 392         rlwinm  r11, r11, 16, 0xfff8
 393 #ifndef CONFIG_PIN_TLB_IMMR
 394         cmpli   cr0, r11, VIRT_IMMR_BASE@h
 395 #endif
 396         cmpli   cr7, r11, PAGE_OFFSET@h
 397 #ifndef CONFIG_PIN_TLB_IMMR
 398 _ENTRY(DTLBMiss_jmp)
 399         beq-    DTLBMissIMMR
 400 #endif
 401         bge-    cr7, DTLBMissLinear
 402
 403         mfspr   r11, SPRN_M_TW  /* Get level 1 table */
 404 3:
 405         mtcr    r10
 406 #ifdef CONFIG_8xx_CPU6
 407         mtspr   SPRN_SPRG_SCRATCH2, r3
 408 #endif
 409         mfspr   r10, SPRN_MD_EPN
 410
 411         /* Insert level 1 index */
 412         rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
 413         lwz     r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)        /* Get the level 1 entry */
 414
 415         /* We have a pte table, so load fetch the pte from the table.
 416          */
 417         /* Extract level 2 index */
 418         rlwinm  r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
 419         rlwimi  r10, r11, 0, 0, 32 - PAGE_SHIFT - 1     /* Add level 2 base */
 420         lwz     r10, 0(r10)     /* Get the pte */
 421
 422         /* Insert the Guarded flag and APG into the TWC from the Linux PTE.
 423          * It is bit 26-27 of both the Linux PTE and the TWC (at least
 424          * I got that right :-).  It will be better when we can put
 425          * this into the Linux pgd/pmd and load it in the operation
 426          * above.
 427          */
 428         rlwimi  r11, r10, 0, 26, 27
 429         /* Insert the WriteThru flag into the TWC from the Linux PTE.
 430          * It is bit 25 in the Linux PTE and bit 30 in the TWC
 431          */
 432         rlwimi  r11, r10, 32-5, 30, 30
 433         MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
 434
 435         /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
 436          * We also need to know if the insn is a load/store, so:
 437          * Clear _PAGE_PRESENT and load that which will
 438          * trap into DTLB Error with store bit set accordinly.
 439          */
 440         /* PRESENT=0x1, ACCESSED=0x20
 441          * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
 442          * r10 = (r10 & ~PRESENT) | r11;
 443          */
 444 #ifdef CONFIG_SWAP
 445         rlwinm  r11, r10, 32-5, _PAGE_PRESENT
 446         and     r11, r11, r10
 447         rlwimi  r10, r11, 0, _PAGE_PRESENT
 448 #endif
 449         /* The Linux PTE won't go exactly into the MMU TLB.
 450          * Software indicator bits 22 and 28 must be clear.
 451          * Software indicator bits 24, 25, 26, and 27 must be
 452          * set.  All other Linux PTE bits control the behavior
 453          * of the MMU.
 454          */
 455         li      r11, RPN_PATTERN
 456         rlwimi  r10, r11, 0, 24, 28     /* Set 24-27, clear 28 */
 457         rlwimi  r10, r11, 0, 20, 20     /* clear 20 */
 458         MTSPR_CPU6(SPRN_MD_RPN, r10, r3)        /* Update TLB entry */
 459
 460         /* Restore registers */
 461 #ifdef CONFIG_8xx_CPU6
 462         mfspr   r3, SPRN_SPRG_SCRATCH2
 463 #endif
 464         mtspr   SPRN_DAR, r11   /* Tag DAR */
 465         EXCEPTION_EPILOG_0
 466         rfi
 467
 468
 469 /* This is an instruction TLB error on the MPC8xx.  This could be due
 470  * to many reasons, such as executing guarded memory or illegal instruction
 471  * addresses.  There is nothing to do but handle a big time error fault.
 472  */
 473         . = 0x1300
 474 InstructionTLBError:
 475         EXCEPTION_PROLOG
 476         mr      r4,r12
 477         mr      r5,r9
 478         andis.  r10,r5,0x4000
 479         beq+    1f
 480         tlbie   r4
 481         /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
 482 1:      EXC_XFER_LITE(0x400, handle_page_fault)
 483
 484 /* This is the data TLB error on the MPC8xx.  This could be due to
 485  * many reasons, including a dirty update to a pte.  We bail out to
 486  * a higher level function that can handle it.
 487  */
 488         . = 0x1400
 489 DataTLBError:
 490         EXCEPTION_PROLOG_0
 491         mfcr    r10
 492
 493         mfspr   r11, SPRN_DAR
 494         cmpwi   cr0, r11, RPN_PATTERN
 495         beq-    FixupDAR        /* must be a buggy dcbX, icbi insn. */
 496 DARFixed:/* Return from dcbx instruction bug workaround */
 497         EXCEPTION_PROLOG_1
 498         EXCEPTION_PROLOG_2
 499         mfspr   r5,SPRN_DSISR
 500         stw     r5,_DSISR(r11)
 501         mfspr   r4,SPRN_DAR
 502         andis.  r10,r5,0x4000
 503         beq+    1f
 504         tlbie   r4
 505 1:      li      r10,RPN_PATTERN
 506         mtspr   SPRN_DAR,r10    /* Tag DAR, to be used in DTLB Error */
 507         /* 0x300 is DataAccess exception, needed by bad_page_fault() */
 508         EXC_XFER_LITE(0x300, handle_page_fault)
 509
 510         EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
 511         EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
 512         EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
 513         EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
 514         EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
 515         EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
 516         EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
 517
 518 /* On the MPC8xx, these next four traps are used for development
 519  * support of breakpoints and such.  Someday I will get around to
 520  * using them.
 521  */
 522         EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
 523         EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
 524         EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
 525         EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
 526
 527         . = 0x2000
 528
 529 /*
 530  * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM.
 531  * not enough space in the DataStoreTLBMiss area.
 532  */
 533 DTLBMissIMMR:
 534         mtcr    r10
 535         /* Set 512k byte guarded page and mark it valid */
 536         li      r10, MD_PS512K | MD_GUARDED | MD_SVALID
 537         MTSPR_CPU6(SPRN_MD_TWC, r10, r11)
 538         mfspr   r10, SPRN_IMMR                  /* Get current IMMR */
 539         rlwinm  r10, r10, 0, 0xfff80000         /* Get 512 kbytes boundary */
 540         ori     r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
 541                           _PAGE_PRESENT | _PAGE_NO_CACHE
 542         MTSPR_CPU6(SPRN_MD_RPN, r10, r11)       /* Update TLB entry */
 543
 544         li      r11, RPN_PATTERN
 545         mtspr   SPRN_DAR, r11   /* Tag DAR */
 546         EXCEPTION_EPILOG_0
 547         rfi
 548
 549 DTLBMissLinear:
 550 _ENTRY(DTLBMiss_cmp)
 551         cmpli   cr0, r11, (PAGE_OFFSET + 0x1800000)@h
 552         lis     r11, (swapper_pg_dir-PAGE_OFFSET)@ha
 553         bge-    3b
 554
 555         mtcr    r10
 556         /* Set 8M byte page and mark it valid */
 557         li      r10, MD_PS8MEG | MD_SVALID
 558         MTSPR_CPU6(SPRN_MD_TWC, r10, r11)
 559         mfspr   r10, SPRN_MD_EPN
 560         rlwinm  r10, r10, 0, 0x0f800000         /* 8xx supports max 256Mb RAM */
 561         ori     r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
 562                           _PAGE_PRESENT
 563         MTSPR_CPU6(SPRN_MD_RPN, r10, r11)       /* Update TLB entry */
 564
 565         li      r11, RPN_PATTERN
 566         mtspr   SPRN_DAR, r11   /* Tag DAR */
 567         EXCEPTION_EPILOG_0
 568         rfi
 569
 570 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
 571  * by decoding the registers used by the dcbx instruction and adding them.
 572  * DAR is set to the calculated address.
 573  */
 574  /* define if you don't want to use self modifying code */
 575 #define NO_SELF_MODIFYING_CODE
 576 FixupDAR:/* Entry point for dcbx workaround. */
 577         mtspr   SPRN_SPRG_SCRATCH2, r10
 578         /* fetch instruction from memory. */
 579         mfspr   r10, SPRN_SRR0
 580         IS_KERNEL(r11, r10)
 581         mfspr   r11, SPRN_M_TW  /* Get level 1 table */
 582         BRANCH_UNLESS_KERNEL(3f)
 583         rlwinm  r11, r10, 16, 0xfff8
 584 _ENTRY(FixupDAR_cmp)
 585         cmpli   cr7, r11, (PAGE_OFFSET + 0x1800000)@h
 586         blt-    cr7, 200f
 587         lis     r11, (swapper_pg_dir-PAGE_OFFSET)@ha
 588         /* Insert level 1 index */
 589 3:      rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
 590         lwz     r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)        /* Get the level 1 entry */
 591         rlwinm  r11, r11,0,0,19 /* Extract page descriptor page address */
 592         /* Insert level 2 index */
 593         rlwimi  r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
 594         lwz     r11, 0(r11)     /* Get the pte */
 595         /* concat physical page address(r11) and page offset(r10) */
 596         rlwimi  r11, r10, 0, 32 - PAGE_SHIFT, 31
 597 201:    lwz     r11,0(r11)
 598 /* Check if it really is a dcbx instruction. */
 599 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
 600  * no need to include them here */
 601         xoris   r10, r11, 0x7c00        /* check if major OP code is 31 */
 602         rlwinm  r10, r10, 0, 21, 5
 603         cmpwi   cr0, r10, 2028  /* Is dcbz? */
 604         beq+    142f
 605         cmpwi   cr0, r10, 940   /* Is dcbi? */
 606         beq+    142f
 607         cmpwi   cr0, r10, 108   /* Is dcbst? */
 608         beq+    144f            /* Fix up store bit! */
 609         cmpwi   cr0, r10, 172   /* Is dcbf? */
 610         beq+    142f
 611         cmpwi   cr0, r10, 1964  /* Is icbi? */
 612         beq+    142f
 613 141:    mfspr   r10,SPRN_SPRG_SCRATCH2
 614         b       DARFixed        /* Nope, go back to normal TLB processing */
 615
 616         /* create physical page address from effective address */
 617 200:    tophys(r11, r10)
 618         b       201b
 619
 620 144:    mfspr   r10, SPRN_DSISR
 621         rlwinm  r10, r10,0,7,5  /* Clear store bit for buggy dcbst insn */
 622         mtspr   SPRN_DSISR, r10
 623 142:    /* continue, it was a dcbx, dcbi instruction. */
 624 #ifndef NO_SELF_MODIFYING_CODE
 625         andis.  r10,r11,0x1f    /* test if reg RA is r0 */
 626         li      r10,modified_instr@l
 627         dcbtst  r0,r10          /* touch for store */
 628         rlwinm  r11,r11,0,0,20  /* Zero lower 10 bits */
 629         oris    r11,r11,640     /* Transform instr. to a "add r10,RA,RB" */
 630         ori     r11,r11,532
 631         stw     r11,0(r10)      /* store add/and instruction */
 632         dcbf    0,r10           /* flush new instr. to memory. */
 633         icbi    0,r10           /* invalidate instr. cache line */
 634         mfspr   r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
 635         mfspr   r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
 636         isync                   /* Wait until new instr is loaded from memory */
 637 modified_instr:
 638         .space  4               /* this is where the add instr. is stored */
 639         bne+    143f
 640         subf    r10,r0,r10      /* r10=r10-r0, only if reg RA is r0 */
 641 143:    mtdar   r10             /* store faulting EA in DAR */
 642         mfspr   r10,SPRN_SPRG_SCRATCH2
 643         b       DARFixed        /* Go back to normal TLB handling */
 644 #else
 645         mfctr   r10
 646         mtdar   r10                     /* save ctr reg in DAR */
 647         rlwinm  r10, r11, 24, 24, 28    /* offset into jump table for reg RB */
 648         addi    r10, r10, 150f@l        /* add start of table */
 649         mtctr   r10                     /* load ctr with jump address */
 650         xor     r10, r10, r10           /* sum starts at zero */
 651         bctr                            /* jump into table */
 652 150:
 653         add     r10, r10, r0    ;b      151f
 654         add     r10, r10, r1    ;b      151f
 655         add     r10, r10, r2    ;b      151f
 656         add     r10, r10, r3    ;b      151f
 657         add     r10, r10, r4    ;b      151f
 658         add     r10, r10, r5    ;b      151f
 659         add     r10, r10, r6    ;b      151f
 660         add     r10, r10, r7    ;b      151f
 661         add     r10, r10, r8    ;b      151f
 662         add     r10, r10, r9    ;b      151f
 663         mtctr   r11     ;b      154f    /* r10 needs special handling */
 664         mtctr   r11     ;b      153f    /* r11 needs special handling */
 665         add     r10, r10, r12   ;b      151f
 666         add     r10, r10, r13   ;b      151f
 667         add     r10, r10, r14   ;b      151f
 668         add     r10, r10, r15   ;b      151f
 669         add     r10, r10, r16   ;b      151f
 670         add     r10, r10, r17   ;b      151f
 671         add     r10, r10, r18   ;b      151f
 672         add     r10, r10, r19   ;b      151f
 673         add     r10, r10, r20   ;b      151f
 674         add     r10, r10, r21   ;b      151f
 675         add     r10, r10, r22   ;b      151f
 676         add     r10, r10, r23   ;b      151f
 677         add     r10, r10, r24   ;b      151f
 678         add     r10, r10, r25   ;b      151f
 679         add     r10, r10, r26   ;b      151f
 680         add     r10, r10, r27   ;b      151f
 681         add     r10, r10, r28   ;b      151f
 682         add     r10, r10, r29   ;b      151f
 683         add     r10, r10, r30   ;b      151f
 684         add     r10, r10, r31
 685 151:
 686         rlwinm. r11,r11,19,24,28        /* offset into jump table for reg RA */
 687         beq     152f                    /* if reg RA is zero, don't add it */
 688         addi    r11, r11, 150b@l        /* add start of table */
 689         mtctr   r11                     /* load ctr with jump address */
 690         rlwinm  r11,r11,0,16,10         /* make sure we don't execute this more than once */
 691         bctr                            /* jump into table */
 692 152:
 693         mfdar   r11
 694         mtctr   r11                     /* restore ctr reg from DAR */
 695         mtdar   r10                     /* save fault EA to DAR */
 696         mfspr   r10,SPRN_SPRG_SCRATCH2
 697         b       DARFixed                /* Go back to normal TLB handling */
 698
 699         /* special handling for r10,r11 since these are modified already */
 700 153:    mfspr   r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
 701         add     r10, r10, r11   /* add it */
 702         mfctr   r11             /* restore r11 */
 703         b       151b
 704 154:    mfspr   r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
 705         add     r10, r10, r11   /* add it */
 706         mfctr   r11             /* restore r11 */
 707         b       151b
 708 #endif
 709
 710 /*
 711  * This is where the main kernel code starts.
 712  */
 713 start_here:
 714         /* ptr to current */
 715         lis     r2,init_task@h
 716         ori     r2,r2,init_task@l
 717
 718         /* ptr to phys current thread */
 719         tophys(r4,r2)
 720         addi    r4,r4,THREAD    /* init task's THREAD */
 721         mtspr   SPRN_SPRG_THREAD,r4
 722
 723         /* stack */
 724         lis     r1,init_thread_union@ha
 725         addi    r1,r1,init_thread_union@l
 726         li      r0,0
 727         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 728
 729         bl      early_init      /* We have to do this with MMU on */
 730
 731 /*
 732  * Decide what sort of machine this is and initialize the MMU.
 733  */
 734         li      r3,0
 735         mr      r4,r31
 736         bl      machine_init
 737         bl      MMU_init
 738
 739 /*
 740  * Go back to running unmapped so we can load up new values
 741  * and change to using our exception vectors.
 742  * On the 8xx, all we have to do is invalidate the TLB to clear
 743  * the old 8M byte TLB mappings and load the page table base register.
 744  */
 745         /* The right way to do this would be to track it down through
 746          * init's THREAD like the context switch code does, but this is
 747          * easier......until someone changes init's static structures.
 748          */
 749         lis     r6, swapper_pg_dir@ha
 750         tophys(r6,r6)
 751 #ifdef CONFIG_8xx_CPU6
 752         lis     r4, cpu6_errata_word@h
 753         ori     r4, r4, cpu6_errata_word@l
 754         li      r3, 0x3f80
 755         stw     r3, 12(r4)
 756         lwz     r3, 12(r4)
 757 #endif
 758         mtspr   SPRN_M_TW, r6
 759         lis     r4,2f@h
 760         ori     r4,r4,2f@l
 761         tophys(r4,r4)
 762         li      r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
 763         mtspr   SPRN_SRR0,r4
 764         mtspr   SPRN_SRR1,r3
 765         rfi
 766 /* Load up the kernel context */
 767 2:
 768         SYNC                    /* Force all PTE updates to finish */
 769         tlbia                   /* Clear all TLB entries */
 770         sync                    /* wait for tlbia/tlbie to finish */
 771         TLBSYNC                 /* ... on all CPUs */
 772
 773         /* set up the PTE pointers for the Abatron bdiGDB.
 774         */
 775         tovirt(r6,r6)
 776         lis     r5, abatron_pteptrs@h
 777         ori     r5, r5, abatron_pteptrs@l
 778         stw     r5, 0xf0(r0)    /* Must match your Abatron config file */
 779         tophys(r5,r5)
 780         stw     r6, 0(r5)
 781
 782 /* Now turn on the MMU for real! */
 783         li      r4,MSR_KERNEL
 784         lis     r3,start_kernel@h
 785         ori     r3,r3,start_kernel@l
 786         mtspr   SPRN_SRR0,r3
 787         mtspr   SPRN_SRR1,r4
 788         rfi                     /* enable MMU and jump to start_kernel */
 789
 790 /* Set up the initial MMU state so we can do the first level of
 791  * kernel initialization.  This maps the first 8 MBytes of memory 1:1
 792  * virtual to physical.  Also, set the cache mode since that is defined
 793  * by TLB entries and perform any additional mapping (like of the IMMR).
 794  * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
 795  * 24 Mbytes of data, and the 512k IMMR space.  Anything not covered by
 796  * these mappings is mapped by page tables.
 797  */
 798 initial_mmu:
 799         li      r8, 0
 800         mtspr   SPRN_MI_CTR, r8         /* remove PINNED ITLB entries */
 801         lis     r10, MD_RESETVAL@h
 802 #ifndef CONFIG_8xx_COPYBACK
 803         oris    r10, r10, MD_WTDEF@h
 804 #endif
 805         mtspr   SPRN_MD_CTR, r10        /* remove PINNED DTLB entries */
 806
 807         tlbia                   /* Invalidate all TLB entries */
 808 /* Always pin the first 8 MB ITLB to prevent ITLB
 809    misses while mucking around with SRR0/SRR1 in asm
 810 */
 811         lis     r8, MI_RSV4I@h
 812         ori     r8, r8, 0x1c00
 813
 814         mtspr   SPRN_MI_CTR, r8 /* Set instruction MMU control */
 815
 816 #ifdef CONFIG_PIN_TLB
 817         oris    r10, r10, MD_RSV4I@h
 818         mtspr   SPRN_MD_CTR, r10        /* Set data TLB control */
 819 #endif
 820
 821         /* Now map the lower 8 Meg into the ITLB. */
 822         lis     r8, KERNELBASE@h        /* Create vaddr for TLB */
 823         ori     r8, r8, MI_EVALID       /* Mark it valid */
 824         mtspr   SPRN_MI_EPN, r8
 825         li      r8, MI_PS8MEG | (2 << 5)        /* Set 8M byte page, APG 2 */
 826         ori     r8, r8, MI_SVALID       /* Make it valid */
 827         mtspr   SPRN_MI_TWC, r8
 828         li      r8, MI_BOOTINIT         /* Create RPN for address 0 */
 829         mtspr   SPRN_MI_RPN, r8         /* Store TLB entry */
 830
 831         lis     r8, MI_APG_INIT@h       /* Set protection modes */
 832         ori     r8, r8, MI_APG_INIT@l
 833         mtspr   SPRN_MI_AP, r8
 834         lis     r8, MD_APG_INIT@h
 835         ori     r8, r8, MD_APG_INIT@l
 836         mtspr   SPRN_MD_AP, r8
 837
 838         /* Map a 512k page for the IMMR to get the processor
 839          * internal registers (among other things).
 840          */
 841 #ifdef CONFIG_PIN_TLB_IMMR
 842         ori     r10, r10, 0x1c00
 843         mtspr   SPRN_MD_CTR, r10
 844
 845         mfspr   r9, 638                 /* Get current IMMR */
 846         andis.  r9, r9, 0xfff8          /* Get 512 kbytes boundary */
 847
 848         lis     r8, VIRT_IMMR_BASE@h    /* Create vaddr for TLB */
 849         ori     r8, r8, MD_EVALID       /* Mark it valid */
 850         mtspr   SPRN_MD_EPN, r8
 851         li      r8, MD_PS512K | MD_GUARDED      /* Set 512k byte page */
 852         ori     r8, r8, MD_SVALID       /* Make it valid */
 853         mtspr   SPRN_MD_TWC, r8
 854         mr      r8, r9                  /* Create paddr for TLB */
 855         ori     r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
 856         mtspr   SPRN_MD_RPN, r8
 857 #endif
 858
 859         /* Since the cache is enabled according to the information we
 860          * just loaded into the TLB, invalidate and enable the caches here.
 861          * We should probably check/set other modes....later.
 862          */
 863         lis     r8, IDC_INVALL@h
 864         mtspr   SPRN_IC_CST, r8
 865         mtspr   SPRN_DC_CST, r8
 866         lis     r8, IDC_ENABLE@h
 867         mtspr   SPRN_IC_CST, r8
 868 #ifdef CONFIG_8xx_COPYBACK
 869         mtspr   SPRN_DC_CST, r8
 870 #else
 871         /* For a debug option, I left this here to easily enable
 872          * the write through cache mode
 873          */
 874         lis     r8, DC_SFWT@h
 875         mtspr   SPRN_DC_CST, r8
 876         lis     r8, IDC_ENABLE@h
 877         mtspr   SPRN_DC_CST, r8
 878 #endif
 879         blr
 880
 881
 882 /*
 883  * We put a few things here that have to be page-aligned.
 884  * This stuff goes at the beginning of the data segment,
 885  * which is page-aligned.
 886  */
 887         .data
 888         .globl  sdata
 889 sdata:
 890         .globl  empty_zero_page
 891         .align  PAGE_SHIFT
 892 empty_zero_page:
 893         .space  PAGE_SIZE
 894
 895         .globl  swapper_pg_dir
 896 swapper_pg_dir:
 897         .space  PGD_TABLE_SIZE
 898
 899 /* Room for two PTE table poiners, usually the kernel and current user
 900  * pointer to their respective root page table (pgdir).
 901  */
 902 abatron_pteptrs:
 903         .space  8
 904
 905 #ifdef CONFIG_8xx_CPU6
 906         .globl  cpu6_errata_word
 907 cpu6_errata_word:
 908         .space  16
 909 #endif
 910