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1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __HEAD_BOOKE_H__
3 #define __HEAD_BOOKE_H__
4
5 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
6 #include <asm/kvm_asm.h>
7 #include <asm/kvm_booke_hv_asm.h>
8
9 /*
10 * Macros used for common Book-e exception handling
11 */
12
13 #define SET_IVOR(vector_number, vector_label) \
14 li r26,vector_label@l; \
15 mtspr SPRN_IVOR##vector_number,r26; \
16 sync
17
18 #if (THREAD_SHIFT < 15)
19 #define ALLOC_STACK_FRAME(reg, val) \
20 addi reg,reg,val
21 #else
22 #define ALLOC_STACK_FRAME(reg, val) \
23 addis reg,reg,val@ha; \
24 addi reg,reg,val@l
25 #endif
26
27 /*
28 * Macro used to get to thread save registers.
29 * Note that entries 0-3 are used for the prolog code, and the remaining
30 * entries are available for specific exception use in the event a handler
31 * requires more than 4 scratch registers.
32 */
33 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
34
35 #ifdef CONFIG_PPC_FSL_BOOK3E
36 #define BOOKE_CLEAR_BTB(reg) \
37 START_BTB_FLUSH_SECTION \
38 BTB_FLUSH(reg) \
39 END_BTB_FLUSH_SECTION
40 #else
41 #define BOOKE_CLEAR_BTB(reg)
42 #endif
43
44
45 #define NORMAL_EXCEPTION_PROLOG(intno) \
46 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
47 mfspr r10, SPRN_SPRG_THREAD; \
48 stw r11, THREAD_NORMSAVE(0)(r10); \
49 stw r13, THREAD_NORMSAVE(2)(r10); \
50 mfcr r13; /* save CR in r13 for now */\
51 mfspr r11, SPRN_SRR1; \
52 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \
53 andi. r11, r11, MSR_PR; /* check whether user or kernel */\
54 mr r11, r1; \
55 beq 1f; \
56 BOOKE_CLEAR_BTB(r11) \
57 /* if from user, start at top of this thread's kernel stack */ \
58 lwz r11, TASK_STACK - THREAD(r10); \
59 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
60 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
61 stw r13, _CCR(r11); /* save various registers */ \
62 stw r12,GPR12(r11); \
63 stw r9,GPR9(r11); \
64 mfspr r13, SPRN_SPRG_RSCRATCH0; \
65 stw r13, GPR10(r11); \
66 lwz r12, THREAD_NORMSAVE(0)(r10); \
67 stw r12,GPR11(r11); \
68 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
69 mflr r10; \
70 stw r10,_LINK(r11); \
71 mfspr r12,SPRN_SRR0; \
72 stw r1, GPR1(r11); \
73 mfspr r9,SPRN_SRR1; \
74 stw r1, 0(r11); \
75 mr r1, r11; \
76 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
77 stw r0,GPR0(r11); \
78 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
79 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
80 stw r10, 8(r11); \
81 SAVE_4GPRS(3, r11); \
82 SAVE_2GPRS(7, r11)
83
84 /* To handle the additional exception priority levels on 40x and Book-E
85 * processors we allocate a stack per additional priority level.
86 *
87 * On 40x critical is the only additional level
88 * On 44x/e500 we have critical and machine check
89 * On e200 we have critical and debug (machine check occurs via critical)
90 *
91 * Additionally we reserve a SPRG for each priority level so we can free up a
92 * GPR to use as the base for indirect access to the exception stacks. This
93 * is necessary since the MMU is always on, for Book-E parts, and the stacks
94 * are offset from KERNELBASE.
95 *
96 * There is some space optimization to be had here if desired. However
97 * to allow for a common kernel with support for debug exceptions either
98 * going to critical or their own debug level we aren't currently
99 * providing configurations that micro-optimize space usage.
100 */
101
102 #define MC_STACK_BASE mcheckirq_ctx
103 #define CRIT_STACK_BASE critirq_ctx
104
105 /* only on e500mc/e200 */
106 #define DBG_STACK_BASE dbgirq_ctx
107
108 #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
109
110 #ifdef CONFIG_SMP
111 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
112 mfspr r8,SPRN_PIR; \
113 slwi r8,r8,2; \
114 addis r8,r8,level##_STACK_BASE@ha; \
115 lwz r8,level##_STACK_BASE@l(r8); \
116 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
117 #else
118 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
119 lis r8,level##_STACK_BASE@ha; \
120 lwz r8,level##_STACK_BASE@l(r8); \
121 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
122 #endif
123
124 /*
125 * Exception prolog for critical/machine check exceptions. This is a
126 * little different from the normal exception prolog above since a
127 * critical/machine check exception can potentially occur at any point
128 * during normal exception processing. Thus we cannot use the same SPRG
129 * registers as the normal prolog above. Instead we use a portion of the
130 * critical/machine check exception stack at low physical addresses.
131 */
132 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \
133 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
134 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
135 stw r9,GPR9(r8); /* save various registers */\
136 mfcr r9; /* save CR in r9 for now */\
137 stw r10,GPR10(r8); \
138 stw r11,GPR11(r8); \
139 stw r9,_CCR(r8); /* save CR on stack */\
140 mfspr r11,exc_level_srr1; /* check whether user or kernel */\
141 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \
142 BOOKE_CLEAR_BTB(r10) \
143 andi. r11,r11,MSR_PR; \
144 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
145 lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
146 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
147 beq 1f; \
148 /* COMING FROM USER MODE */ \
149 stw r9,_CCR(r11); /* save CR */\
150 lwz r10,GPR10(r8); /* copy regs from exception stack */\
151 lwz r9,GPR9(r8); \
152 stw r10,GPR10(r11); \
153 lwz r10,GPR11(r8); \
154 stw r9,GPR9(r11); \
155 stw r10,GPR11(r11); \
156 b 2f; \
157 /* COMING FROM PRIV MODE */ \
158 1: mr r11, r8; \
159 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
160 stw r12,GPR12(r11); /* save various registers */\
161 mflr r10; \
162 stw r10,_LINK(r11); \
163 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
164 stw r12,_DEAR(r11); /* since they may have had stuff */\
165 mfspr r9,SPRN_ESR; /* in them at the point where the */\
166 stw r9,_ESR(r11); /* exception was taken */\
167 mfspr r12,exc_level_srr0; \
168 stw r1,GPR1(r11); \
169 mfspr r9,exc_level_srr1; \
170 stw r1,0(r11); \
171 mr r1,r11; \
172 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
173 stw r0,GPR0(r11); \
174 SAVE_4GPRS(3, r11); \
175 SAVE_2GPRS(7, r11)
176
177 #define CRITICAL_EXCEPTION_PROLOG(intno) \
178 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)
179 #define DEBUG_EXCEPTION_PROLOG \
180 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
181 #define MCHECK_EXCEPTION_PROLOG \
182 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \
183 SPRN_MCSRR0, SPRN_MCSRR1)
184
185 /*
186 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
187 * being delivered to the host. This exception can only happen
188 * inside a KVM guest -- so we just handle up to the DO_KVM rather
189 * than try to fit this into one of the existing prolog macros.
190 */
191 #define GUEST_DOORBELL_EXCEPTION \
192 START_EXCEPTION(GuestDoorbell); \
193 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
194 mfspr r10, SPRN_SPRG_THREAD; \
195 stw r11, THREAD_NORMSAVE(0)(r10); \
196 mfspr r11, SPRN_SRR1; \
197 stw r13, THREAD_NORMSAVE(2)(r10); \
198 mfcr r13; /* save CR in r13 for now */\
199 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \
200 trap
201
202 /*
203 * Exception vectors.
204 */
205 #define START_EXCEPTION(label) \
206 .align 5; \
207 label:
208
209 #define EXCEPTION(n, intno, label, hdlr, xfer) \
210 START_EXCEPTION(label); \
211 NORMAL_EXCEPTION_PROLOG(intno); \
212 addi r3,r1,STACK_FRAME_OVERHEAD; \
213 xfer(n, hdlr)
214
215 #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \
216 START_EXCEPTION(label); \
217 CRITICAL_EXCEPTION_PROLOG(intno); \
218 addi r3,r1,STACK_FRAME_OVERHEAD; \
219 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
220 NOCOPY, crit_transfer_to_handler, \
221 ret_from_crit_exc)
222
223 #define MCHECK_EXCEPTION(n, label, hdlr) \
224 START_EXCEPTION(label); \
225 MCHECK_EXCEPTION_PROLOG; \
226 mfspr r5,SPRN_ESR; \
227 stw r5,_ESR(r11); \
228 addi r3,r1,STACK_FRAME_OVERHEAD; \
229 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
230 NOCOPY, mcheck_transfer_to_handler, \
231 ret_from_mcheck_exc)
232
233 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
234 li r10,trap; \
235 stw r10,_TRAP(r11); \
236 lis r10,msr@h; \
237 ori r10,r10,msr@l; \
238 copyee(r10, r9); \
239 bl tfer; \
240 .long hdlr; \
241 .long ret
242
243 #define COPY_EE(d, s) rlwimi d,s,0,16,16
244 #define NOCOPY(d, s)
245
246 #define EXC_XFER_STD(n, hdlr) \
247 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
248 ret_from_except_full)
249
250 #define EXC_XFER_LITE(n, hdlr) \
251 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
252 ret_from_except)
253
254 #define EXC_XFER_EE(n, hdlr) \
255 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
256 ret_from_except_full)
257
258 #define EXC_XFER_EE_LITE(n, hdlr) \
259 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
260 ret_from_except)
261
262 /* Check for a single step debug exception while in an exception
263 * handler before state has been saved. This is to catch the case
264 * where an instruction that we are trying to single step causes
265 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
266 * the exception handler generates a single step debug exception.
267 *
268 * If we get a debug trap on the first instruction of an exception handler,
269 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
270 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
271 * The exception handler was handling a non-critical interrupt, so it will
272 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
273 * the MSR_DE bit set.
274 */
275 #define DEBUG_DEBUG_EXCEPTION \
276 START_EXCEPTION(DebugDebug); \
277 DEBUG_EXCEPTION_PROLOG; \
278 \
279 /* \
280 * If there is a single step or branch-taken exception in an \
281 * exception entry sequence, it was probably meant to apply to \
282 * the code where the exception occurred (since exception entry \
283 * doesn't turn off DE automatically). We simulate the effect \
284 * of turning off DE on entry to an exception handler by turning \
285 * off DE in the DSRR1 value and clearing the debug status. \
286 */ \
287 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
288 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
289 beq+ 2f; \
290 \
291 lis r10,interrupt_base@h; /* check if exception in vectors */ \
292 ori r10,r10,interrupt_base@l; \
293 cmplw r12,r10; \
294 blt+ 2f; /* addr below exception vectors */ \
295 \
296 lis r10,interrupt_end@h; \
297 ori r10,r10,interrupt_end@l; \
298 cmplw r12,r10; \
299 bgt+ 2f; /* addr above exception vectors */ \
300 \
301 /* here it looks like we got an inappropriate debug exception. */ \
302 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
303 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
304 mtspr SPRN_DBSR,r10; \
305 /* restore state and get out */ \
306 lwz r10,_CCR(r11); \
307 lwz r0,GPR0(r11); \
308 lwz r1,GPR1(r11); \
309 mtcrf 0x80,r10; \
310 mtspr SPRN_DSRR0,r12; \
311 mtspr SPRN_DSRR1,r9; \
312 lwz r9,GPR9(r11); \
313 lwz r12,GPR12(r11); \
314 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
315 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
316 lwz r10,GPR10(r8); \
317 lwz r11,GPR11(r8); \
318 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
319 \
320 PPC_RFDI; \
321 b .; \
322 \
323 /* continue normal handling for a debug exception... */ \
324 2: mfspr r4,SPRN_DBSR; \
325 addi r3,r1,STACK_FRAME_OVERHEAD; \
326 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
327
328 #define DEBUG_CRIT_EXCEPTION \
329 START_EXCEPTION(DebugCrit); \
330 CRITICAL_EXCEPTION_PROLOG(DEBUG); \
331 \
332 /* \
333 * If there is a single step or branch-taken exception in an \
334 * exception entry sequence, it was probably meant to apply to \
335 * the code where the exception occurred (since exception entry \
336 * doesn't turn off DE automatically). We simulate the effect \
337 * of turning off DE on entry to an exception handler by turning \
338 * off DE in the CSRR1 value and clearing the debug status. \
339 */ \
340 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
341 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
342 beq+ 2f; \
343 \
344 lis r10,interrupt_base@h; /* check if exception in vectors */ \
345 ori r10,r10,interrupt_base@l; \
346 cmplw r12,r10; \
347 blt+ 2f; /* addr below exception vectors */ \
348 \
349 lis r10,interrupt_end@h; \
350 ori r10,r10,interrupt_end@l; \
351 cmplw r12,r10; \
352 bgt+ 2f; /* addr above exception vectors */ \
353 \
354 /* here it looks like we got an inappropriate debug exception. */ \
355 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
356 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
357 mtspr SPRN_DBSR,r10; \
358 /* restore state and get out */ \
359 lwz r10,_CCR(r11); \
360 lwz r0,GPR0(r11); \
361 lwz r1,GPR1(r11); \
362 mtcrf 0x80,r10; \
363 mtspr SPRN_CSRR0,r12; \
364 mtspr SPRN_CSRR1,r9; \
365 lwz r9,GPR9(r11); \
366 lwz r12,GPR12(r11); \
367 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
368 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
369 lwz r10,GPR10(r8); \
370 lwz r11,GPR11(r8); \
371 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
372 \
373 rfci; \
374 b .; \
375 \
376 /* continue normal handling for a critical exception... */ \
377 2: mfspr r4,SPRN_DBSR; \
378 addi r3,r1,STACK_FRAME_OVERHEAD; \
379 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
380
381 #define DATA_STORAGE_EXCEPTION \
382 START_EXCEPTION(DataStorage) \
383 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE); \
384 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
385 stw r5,_ESR(r11); \
386 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
387 EXC_XFER_LITE(0x0300, handle_page_fault)
388
389 #define INSTRUCTION_STORAGE_EXCEPTION \
390 START_EXCEPTION(InstructionStorage) \
391 NORMAL_EXCEPTION_PROLOG(INST_STORAGE); \
392 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
393 stw r5,_ESR(r11); \
394 mr r4,r12; /* Pass SRR0 as arg2 */ \
395 li r5,0; /* Pass zero as arg3 */ \
396 EXC_XFER_LITE(0x0400, handle_page_fault)
397
398 #define ALIGNMENT_EXCEPTION \
399 START_EXCEPTION(Alignment) \
400 NORMAL_EXCEPTION_PROLOG(ALIGNMENT); \
401 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
402 stw r4,_DEAR(r11); \
403 addi r3,r1,STACK_FRAME_OVERHEAD; \
404 EXC_XFER_EE(0x0600, alignment_exception)
405
406 #define PROGRAM_EXCEPTION \
407 START_EXCEPTION(Program) \
408 NORMAL_EXCEPTION_PROLOG(PROGRAM); \
409 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
410 stw r4,_ESR(r11); \
411 addi r3,r1,STACK_FRAME_OVERHEAD; \
412 EXC_XFER_STD(0x0700, program_check_exception)
413
414 #define DECREMENTER_EXCEPTION \
415 START_EXCEPTION(Decrementer) \
416 NORMAL_EXCEPTION_PROLOG(DECREMENTER); \
417 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
418 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
419 addi r3,r1,STACK_FRAME_OVERHEAD; \
420 EXC_XFER_LITE(0x0900, timer_interrupt)
421
422 #define FP_UNAVAILABLE_EXCEPTION \
423 START_EXCEPTION(FloatingPointUnavailable) \
424 NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL); \
425 beq 1f; \
426 bl load_up_fpu; /* if from user, just load it up */ \
427 b fast_exception_return; \
428 1: addi r3,r1,STACK_FRAME_OVERHEAD; \
429 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
430
431 #ifndef __ASSEMBLY__
432 struct exception_regs {
433 unsigned long mas0;
434 unsigned long mas1;
435 unsigned long mas2;
436 unsigned long mas3;
437 unsigned long mas6;
438 unsigned long mas7;
439 unsigned long srr0;
440 unsigned long srr1;
441 unsigned long csrr0;
442 unsigned long csrr1;
443 unsigned long dsrr0;
444 unsigned long dsrr1;
445 unsigned long saved_ksp_limit;
446 };
447
448 /* ensure this structure is always sized to a multiple of the stack alignment */
449 #define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16)
450
451 #endif /* __ASSEMBLY__ */
452 #endif /* __HEAD_BOOKE_H__ */
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