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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Kernel execution entry point code.
4 *
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
6 * Initial PowerPC version.
7 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Rewritten for PReP
9 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
10 * Low-level exception handers, MMU support, and rewrite.
11 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
12 * PowerPC 8xx modifications.
13 * Copyright (c) 1998-1999 TiVo, Inc.
14 * PowerPC 403GCX modifications.
15 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
16 * PowerPC 403GCX/405GP modifications.
17 * Copyright 2000 MontaVista Software Inc.
18 * PPC405 modifications
19 * PowerPC 403GCX/405GP modifications.
20 * Author: MontaVista Software, Inc.
21 * frank_rowand@mvista.com or source@mvista.com
22 * debbie_chu@mvista.com
23 * Copyright 2002-2004 MontaVista Software, Inc.
24 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
25 * Copyright 2004 Freescale Semiconductor, Inc
26 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 */
28
29 #include <linux/init.h>
30 #include <linux/threads.h>
31 #include <asm/processor.h>
32 #include <asm/page.h>
33 #include <asm/mmu.h>
34 #include <linux/pgtable.h>
35 #include <asm/cputable.h>
36 #include <asm/thread_info.h>
37 #include <asm/ppc_asm.h>
38 #include <asm/asm-offsets.h>
39 #include <asm/cache.h>
40 #include <asm/ptrace.h>
41 #include <asm/export.h>
42 #include <asm/feature-fixups.h>
43 #include "head_booke.h"
44
45 /* As with the other PowerPC ports, it is expected that when code
46 * execution begins here, the following registers contain valid, yet
47 * optional, information:
48 *
49 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
50 * r4 - Starting address of the init RAM disk
51 * r5 - Ending address of the init RAM disk
52 * r6 - Start of kernel command line string (e.g. "mem=128")
53 * r7 - End of kernel command line string
54 *
55 */
56 __HEAD
57 _ENTRY(_stext);
58 _ENTRY(_start);
59 /*
60 * Reserve a word at a fixed location to store the address
61 * of abatron_pteptrs
62 */
63 nop
64
65 /* Translate device tree address to physical, save in r30/r31 */
66 bl get_phys_addr
67 mr r30,r3
68 mr r31,r4
69
70 li r25,0 /* phys kernel start (low) */
71 li r24,0 /* CPU number */
72 li r23,0 /* phys kernel start (high) */
73
74 #ifdef CONFIG_RELOCATABLE
75 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
76
77 /* Translate _stext address to physical, save in r23/r25 */
78 bl get_phys_addr
79 mr r23,r3
80 mr r25,r4
81
82 bl 0f
83 0: mflr r8
84 addis r3,r8,(is_second_reloc - 0b)@ha
85 lwz r19,(is_second_reloc - 0b)@l(r3)
86
87 /* Check if this is the second relocation. */
88 cmpwi r19,1
89 bne 1f
90
91 /*
92 * For the second relocation, we already get the real memstart_addr
93 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
94 * then the virtual address of start kernel should be:
95 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
96 * Since the offset between kernstart_addr and memstart_addr should
97 * never be beyond 1G, so we can just use the lower 32bit of them
98 * for the calculation.
99 */
100 lis r3,PAGE_OFFSET@h
101
102 addis r4,r8,(kernstart_addr - 0b)@ha
103 addi r4,r4,(kernstart_addr - 0b)@l
104 lwz r5,4(r4)
105
106 addis r6,r8,(memstart_addr - 0b)@ha
107 addi r6,r6,(memstart_addr - 0b)@l
108 lwz r7,4(r6)
109
110 subf r5,r7,r5
111 add r3,r3,r5
112 b 2f
113
114 1:
115 /*
116 * We have the runtime (virutal) address of our base.
117 * We calculate our shift of offset from a 64M page.
118 * We could map the 64M page we belong to at PAGE_OFFSET and
119 * get going from there.
120 */
121 lis r4,KERNELBASE@h
122 ori r4,r4,KERNELBASE@l
123 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
124 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
125 subf r3,r5,r6 /* r3 = r6 - r5 */
126 add r3,r4,r3 /* Required Virtual Address */
127
128 2: bl relocate
129
130 /*
131 * For the second relocation, we already set the right tlb entries
132 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
133 */
134 cmpwi r19,1
135 beq set_ivor
136 #endif
137
138 /* We try to not make any assumptions about how the boot loader
139 * setup or used the TLBs. We invalidate all mappings from the
140 * boot loader and load a single entry in TLB1[0] to map the
141 * first 64M of kernel memory. Any boot info passed from the
142 * bootloader needs to live in this first 64M.
143 *
144 * Requirement on bootloader:
145 * - The page we're executing in needs to reside in TLB1 and
146 * have IPROT=1. If not an invalidate broadcast could
147 * evict the entry we're currently executing in.
148 *
149 * r3 = Index of TLB1 were executing in
150 * r4 = Current MSR[IS]
151 * r5 = Index of TLB1 temp mapping
152 *
153 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
154 * if needed
155 */
156
157 _ENTRY(__early_start)
158 LOAD_REG_ADDR_PIC(r20, kernstart_virt_addr)
159 lwz r20,0(r20)
160
161 #define ENTRY_MAPPING_BOOT_SETUP
162 #include "fsl_booke_entry_mapping.S"
163 #undef ENTRY_MAPPING_BOOT_SETUP
164
165 set_ivor:
166 /* Establish the interrupt vector offsets */
167 SET_IVOR(0, CriticalInput);
168 SET_IVOR(1, MachineCheck);
169 SET_IVOR(2, DataStorage);
170 SET_IVOR(3, InstructionStorage);
171 SET_IVOR(4, ExternalInput);
172 SET_IVOR(5, Alignment);
173 SET_IVOR(6, Program);
174 SET_IVOR(7, FloatingPointUnavailable);
175 SET_IVOR(8, SystemCall);
176 SET_IVOR(9, AuxillaryProcessorUnavailable);
177 SET_IVOR(10, Decrementer);
178 SET_IVOR(11, FixedIntervalTimer);
179 SET_IVOR(12, WatchdogTimer);
180 SET_IVOR(13, DataTLBError);
181 SET_IVOR(14, InstructionTLBError);
182 SET_IVOR(15, DebugCrit);
183
184 /* Establish the interrupt vector base */
185 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
186 mtspr SPRN_IVPR,r4
187
188 /* Setup the defaults for TLB entries */
189 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
190 #ifdef CONFIG_E200
191 oris r2,r2,MAS4_TLBSELD(1)@h
192 #endif
193 mtspr SPRN_MAS4, r2
194
195 #if !defined(CONFIG_BDI_SWITCH)
196 /*
197 * The Abatron BDI JTAG debugger does not tolerate others
198 * mucking with the debug registers.
199 */
200 lis r2,DBCR0_IDM@h
201 mtspr SPRN_DBCR0,r2
202 isync
203 /* clear any residual debug events */
204 li r2,-1
205 mtspr SPRN_DBSR,r2
206 #endif
207
208 #ifdef CONFIG_SMP
209 /* Check to see if we're the second processor, and jump
210 * to the secondary_start code if so
211 */
212 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
213 lwz r24, 0(r24)
214 cmpwi r24, -1
215 mfspr r24,SPRN_PIR
216 bne __secondary_start
217 #endif
218
219 /*
220 * This is where the main kernel code starts.
221 */
222
223 /* ptr to current */
224 lis r2,init_task@h
225 ori r2,r2,init_task@l
226
227 /* ptr to current thread */
228 addi r4,r2,THREAD /* init task's THREAD */
229 mtspr SPRN_SPRG_THREAD,r4
230
231 /* stack */
232 lis r1,init_thread_union@h
233 ori r1,r1,init_thread_union@l
234 li r0,0
235 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
236
237 #ifdef CONFIG_SMP
238 stw r24, TASK_CPU(r2)
239 #endif
240
241 bl early_init
242
243 #ifdef CONFIG_KASAN
244 bl kasan_early_init
245 #endif
246 #ifdef CONFIG_RELOCATABLE
247 mr r3,r30
248 mr r4,r31
249 #ifdef CONFIG_PHYS_64BIT
250 mr r5,r23
251 mr r6,r25
252 #else
253 mr r5,r25
254 #endif
255 bl relocate_init
256 #endif
257
258 #ifdef CONFIG_DYNAMIC_MEMSTART
259 lis r3,kernstart_addr@ha
260 la r3,kernstart_addr@l(r3)
261 #ifdef CONFIG_PHYS_64BIT
262 stw r23,0(r3)
263 stw r25,4(r3)
264 #else
265 stw r25,0(r3)
266 #endif
267 #endif
268
269 /*
270 * Decide what sort of machine this is and initialize the MMU.
271 */
272 mr r3,r30
273 mr r4,r31
274 bl machine_init
275 bl MMU_init
276
277 /* Setup PTE pointers for the Abatron bdiGDB */
278 lis r6, swapper_pg_dir@h
279 ori r6, r6, swapper_pg_dir@l
280 lis r5, abatron_pteptrs@h
281 ori r5, r5, abatron_pteptrs@l
282 lis r3, kernstart_virt_addr@ha
283 lwz r4, kernstart_virt_addr@l(r3)
284 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
285 stw r6, 0(r5)
286
287 /* Let's move on */
288 lis r4,start_kernel@h
289 ori r4,r4,start_kernel@l
290 lis r3,MSR_KERNEL@h
291 ori r3,r3,MSR_KERNEL@l
292 mtspr SPRN_SRR0,r4
293 mtspr SPRN_SRR1,r3
294 rfi /* change context and jump to start_kernel */
295
296 /* Macros to hide the PTE size differences
297 *
298 * FIND_PTE -- walks the page tables given EA & pgdir pointer
299 * r10 -- EA of fault
300 * r11 -- PGDIR pointer
301 * r12 -- free
302 * label 2: is the bailout case
303 *
304 * if we find the pte (fall through):
305 * r11 is low pte word
306 * r12 is pointer to the pte
307 * r10 is the pshift from the PGD, if we're a hugepage
308 */
309 #ifdef CONFIG_PTE_64BIT
310 #ifdef CONFIG_HUGETLB_PAGE
311 #define FIND_PTE \
312 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
313 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
314 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
315 blt 1000f; /* Normal non-huge page */ \
316 beq 2f; /* Bail if no table */ \
317 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
318 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
319 xor r12, r10, r11; /* drop size bits from pointer */ \
320 b 1001f; \
321 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
322 li r10, 0; /* clear r10 */ \
323 1001: lwz r11, 4(r12); /* Get pte entry */
324 #else
325 #define FIND_PTE \
326 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
327 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
328 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
329 beq 2f; /* Bail if no table */ \
330 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
331 lwz r11, 4(r12); /* Get pte entry */
332 #endif /* HUGEPAGE */
333 #else /* !PTE_64BIT */
334 #define FIND_PTE \
335 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
336 lwz r11, 0(r11); /* Get L1 entry */ \
337 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
338 beq 2f; /* Bail if no table */ \
339 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
340 lwz r11, 0(r12); /* Get Linux PTE */
341 #endif
342
343 /*
344 * Interrupt vector entry code
345 *
346 * The Book E MMUs are always on so we don't need to handle
347 * interrupts in real mode as with previous PPC processors. In
348 * this case we handle interrupts in the kernel virtual address
349 * space.
350 *
351 * Interrupt vectors are dynamically placed relative to the
352 * interrupt prefix as determined by the address of interrupt_base.
353 * The interrupt vectors offsets are programmed using the labels
354 * for each interrupt vector entry.
355 *
356 * Interrupt vectors must be aligned on a 16 byte boundary.
357 * We align on a 32 byte cache line boundary for good measure.
358 */
359
360 interrupt_base:
361 /* Critical Input Interrupt */
362 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
363
364 /* Machine Check Interrupt */
365 #ifdef CONFIG_E200
366 /* no RFMCI, MCSRRs on E200 */
367 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
368 machine_check_exception)
369 #else
370 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
371 #endif
372
373 /* Data Storage Interrupt */
374 START_EXCEPTION(DataStorage)
375 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
376 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
377 stw r5,_ESR(r11)
378 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
379 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
380 bne 1f
381 stw r4, _DEAR(r11)
382 EXC_XFER_LITE(0x0300, handle_page_fault)
383 1:
384 addi r3,r1,STACK_FRAME_OVERHEAD
385 EXC_XFER_LITE(0x0300, CacheLockingException)
386
387 /* Instruction Storage Interrupt */
388 INSTRUCTION_STORAGE_EXCEPTION
389
390 /* External Input Interrupt */
391 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
392
393 /* Alignment Interrupt */
394 ALIGNMENT_EXCEPTION
395
396 /* Program Interrupt */
397 PROGRAM_EXCEPTION
398
399 /* Floating Point Unavailable Interrupt */
400 #ifdef CONFIG_PPC_FPU
401 FP_UNAVAILABLE_EXCEPTION
402 #else
403 #ifdef CONFIG_E200
404 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
405 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
406 program_check_exception, EXC_XFER_STD)
407 #else
408 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
409 unknown_exception, EXC_XFER_STD)
410 #endif
411 #endif
412
413 /* System Call Interrupt */
414 START_EXCEPTION(SystemCall)
415 SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1
416
417 /* Auxiliary Processor Unavailable Interrupt */
418 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
419 unknown_exception, EXC_XFER_STD)
420
421 /* Decrementer Interrupt */
422 DECREMENTER_EXCEPTION
423
424 /* Fixed Internal Timer Interrupt */
425 /* TODO: Add FIT support */
426 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
427 unknown_exception, EXC_XFER_STD)
428
429 /* Watchdog Timer Interrupt */
430 #ifdef CONFIG_BOOKE_WDT
431 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
432 #else
433 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
434 #endif
435
436 /* Data TLB Error Interrupt */
437 START_EXCEPTION(DataTLBError)
438 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
439 mfspr r10, SPRN_SPRG_THREAD
440 stw r11, THREAD_NORMSAVE(0)(r10)
441 #ifdef CONFIG_KVM_BOOKE_HV
442 BEGIN_FTR_SECTION
443 mfspr r11, SPRN_SRR1
444 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
445 #endif
446 stw r12, THREAD_NORMSAVE(1)(r10)
447 stw r13, THREAD_NORMSAVE(2)(r10)
448 mfcr r13
449 stw r13, THREAD_NORMSAVE(3)(r10)
450 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
451 START_BTB_FLUSH_SECTION
452 mfspr r11, SPRN_SRR1
453 andi. r10,r11,MSR_PR
454 beq 1f
455 BTB_FLUSH(r10)
456 1:
457 END_BTB_FLUSH_SECTION
458 mfspr r10, SPRN_DEAR /* Get faulting address */
459
460 /* If we are faulting a kernel address, we have to use the
461 * kernel page tables.
462 */
463 lis r11, PAGE_OFFSET@h
464 cmplw 5, r10, r11
465 blt 5, 3f
466 lis r11, swapper_pg_dir@h
467 ori r11, r11, swapper_pg_dir@l
468
469 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
470 rlwinm r12,r12,0,16,1
471 mtspr SPRN_MAS1,r12
472
473 b 4f
474
475 /* Get the PGD for the current thread */
476 3:
477 mfspr r11,SPRN_SPRG_THREAD
478 lwz r11,PGDIR(r11)
479
480 4:
481 /* Mask of required permission bits. Note that while we
482 * do copy ESR:ST to _PAGE_RW position as trying to write
483 * to an RO page is pretty common, we don't do it with
484 * _PAGE_DIRTY. We could do it, but it's a fairly rare
485 * event so I'd rather take the overhead when it happens
486 * rather than adding an instruction here. We should measure
487 * whether the whole thing is worth it in the first place
488 * as we could avoid loading SPRN_ESR completely in the first
489 * place...
490 *
491 * TODO: Is it worth doing that mfspr & rlwimi in the first
492 * place or can we save a couple of instructions here ?
493 */
494 mfspr r12,SPRN_ESR
495 #ifdef CONFIG_PTE_64BIT
496 li r13,_PAGE_PRESENT
497 oris r13,r13,_PAGE_ACCESSED@h
498 #else
499 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
500 #endif
501 rlwimi r13,r12,11,29,29
502
503 FIND_PTE
504 andc. r13,r13,r11 /* Check permission */
505
506 #ifdef CONFIG_PTE_64BIT
507 #ifdef CONFIG_SMP
508 subf r13,r11,r12 /* create false data dep */
509 lwzx r13,r11,r13 /* Get upper pte bits */
510 #else
511 lwz r13,0(r12) /* Get upper pte bits */
512 #endif
513 #endif
514
515 bne 2f /* Bail if permission/valid mismach */
516
517 /* Jump to common tlb load */
518 b finish_tlb_load
519 2:
520 /* The bailout. Restore registers to pre-exception conditions
521 * and call the heavyweights to help us out.
522 */
523 mfspr r10, SPRN_SPRG_THREAD
524 lwz r11, THREAD_NORMSAVE(3)(r10)
525 mtcr r11
526 lwz r13, THREAD_NORMSAVE(2)(r10)
527 lwz r12, THREAD_NORMSAVE(1)(r10)
528 lwz r11, THREAD_NORMSAVE(0)(r10)
529 mfspr r10, SPRN_SPRG_RSCRATCH0
530 b DataStorage
531
532 /* Instruction TLB Error Interrupt */
533 /*
534 * Nearly the same as above, except we get our
535 * information from different registers and bailout
536 * to a different point.
537 */
538 START_EXCEPTION(InstructionTLBError)
539 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
540 mfspr r10, SPRN_SPRG_THREAD
541 stw r11, THREAD_NORMSAVE(0)(r10)
542 #ifdef CONFIG_KVM_BOOKE_HV
543 BEGIN_FTR_SECTION
544 mfspr r11, SPRN_SRR1
545 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
546 #endif
547 stw r12, THREAD_NORMSAVE(1)(r10)
548 stw r13, THREAD_NORMSAVE(2)(r10)
549 mfcr r13
550 stw r13, THREAD_NORMSAVE(3)(r10)
551 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
552 START_BTB_FLUSH_SECTION
553 mfspr r11, SPRN_SRR1
554 andi. r10,r11,MSR_PR
555 beq 1f
556 BTB_FLUSH(r10)
557 1:
558 END_BTB_FLUSH_SECTION
559
560 mfspr r10, SPRN_SRR0 /* Get faulting address */
561
562 /* If we are faulting a kernel address, we have to use the
563 * kernel page tables.
564 */
565 lis r11, PAGE_OFFSET@h
566 cmplw 5, r10, r11
567 blt 5, 3f
568 lis r11, swapper_pg_dir@h
569 ori r11, r11, swapper_pg_dir@l
570
571 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
572 rlwinm r12,r12,0,16,1
573 mtspr SPRN_MAS1,r12
574
575 /* Make up the required permissions for kernel code */
576 #ifdef CONFIG_PTE_64BIT
577 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
578 oris r13,r13,_PAGE_ACCESSED@h
579 #else
580 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
581 #endif
582 b 4f
583
584 /* Get the PGD for the current thread */
585 3:
586 mfspr r11,SPRN_SPRG_THREAD
587 lwz r11,PGDIR(r11)
588
589 /* Make up the required permissions for user code */
590 #ifdef CONFIG_PTE_64BIT
591 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
592 oris r13,r13,_PAGE_ACCESSED@h
593 #else
594 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
595 #endif
596
597 4:
598 FIND_PTE
599 andc. r13,r13,r11 /* Check permission */
600
601 #ifdef CONFIG_PTE_64BIT
602 #ifdef CONFIG_SMP
603 subf r13,r11,r12 /* create false data dep */
604 lwzx r13,r11,r13 /* Get upper pte bits */
605 #else
606 lwz r13,0(r12) /* Get upper pte bits */
607 #endif
608 #endif
609
610 bne 2f /* Bail if permission mismach */
611
612 /* Jump to common TLB load point */
613 b finish_tlb_load
614
615 2:
616 /* The bailout. Restore registers to pre-exception conditions
617 * and call the heavyweights to help us out.
618 */
619 mfspr r10, SPRN_SPRG_THREAD
620 lwz r11, THREAD_NORMSAVE(3)(r10)
621 mtcr r11
622 lwz r13, THREAD_NORMSAVE(2)(r10)
623 lwz r12, THREAD_NORMSAVE(1)(r10)
624 lwz r11, THREAD_NORMSAVE(0)(r10)
625 mfspr r10, SPRN_SPRG_RSCRATCH0
626 b InstructionStorage
627
628 /* Define SPE handlers for e200 and e500v2 */
629 #ifdef CONFIG_SPE
630 /* SPE Unavailable */
631 START_EXCEPTION(SPEUnavailable)
632 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
633 beq 1f
634 bl load_up_spe
635 b fast_exception_return
636 1: addi r3,r1,STACK_FRAME_OVERHEAD
637 EXC_XFER_LITE(0x2010, KernelSPE)
638 #elif defined(CONFIG_SPE_POSSIBLE)
639 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
640 unknown_exception, EXC_XFER_STD)
641 #endif /* CONFIG_SPE_POSSIBLE */
642
643 /* SPE Floating Point Data */
644 #ifdef CONFIG_SPE
645 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
646 SPEFloatingPointException, EXC_XFER_STD)
647
648 /* SPE Floating Point Round */
649 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
650 SPEFloatingPointRoundException, EXC_XFER_STD)
651 #elif defined(CONFIG_SPE_POSSIBLE)
652 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
653 unknown_exception, EXC_XFER_STD)
654 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
655 unknown_exception, EXC_XFER_STD)
656 #endif /* CONFIG_SPE_POSSIBLE */
657
658
659 /* Performance Monitor */
660 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
661 performance_monitor_exception, EXC_XFER_STD)
662
663 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
664
665 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
666 CriticalDoorbell, unknown_exception)
667
668 /* Debug Interrupt */
669 DEBUG_DEBUG_EXCEPTION
670 DEBUG_CRIT_EXCEPTION
671
672 GUEST_DOORBELL_EXCEPTION
673
674 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
675 unknown_exception)
676
677 /* Hypercall */
678 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_STD)
679
680 /* Embedded Hypervisor Privilege */
681 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_STD)
682
683 interrupt_end:
684
685 /*
686 * Local functions
687 */
688
689 /*
690 * Both the instruction and data TLB miss get to this
691 * point to load the TLB.
692 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
693 * r11 - TLB (info from Linux PTE)
694 * r12 - available to use
695 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
696 * CR5 - results of addr >= PAGE_OFFSET
697 * MAS0, MAS1 - loaded with proper value when we get here
698 * MAS2, MAS3 - will need additional info from Linux PTE
699 * Upon exit, we reload everything and RFI.
700 */
701 finish_tlb_load:
702 #ifdef CONFIG_HUGETLB_PAGE
703 cmpwi 6, r10, 0 /* check for huge page */
704 beq 6, finish_tlb_load_cont /* !huge */
705
706 /* Alas, we need more scratch registers for hugepages */
707 mfspr r12, SPRN_SPRG_THREAD
708 stw r14, THREAD_NORMSAVE(4)(r12)
709 stw r15, THREAD_NORMSAVE(5)(r12)
710 stw r16, THREAD_NORMSAVE(6)(r12)
711 stw r17, THREAD_NORMSAVE(7)(r12)
712
713 /* Get the next_tlbcam_idx percpu var */
714 #ifdef CONFIG_SMP
715 lwz r15, TASK_CPU-THREAD(r12)
716 lis r14, __per_cpu_offset@h
717 ori r14, r14, __per_cpu_offset@l
718 rlwinm r15, r15, 2, 0, 29
719 lwzx r16, r14, r15
720 #else
721 li r16, 0
722 #endif
723 lis r17, next_tlbcam_idx@h
724 ori r17, r17, next_tlbcam_idx@l
725 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
726 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
727
728 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
729 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
730 mtspr SPRN_MAS0, r14
731
732 /* Extract TLB1CFG(NENTRY) */
733 mfspr r16, SPRN_TLB1CFG
734 andi. r16, r16, 0xfff
735
736 /* Update next_tlbcam_idx, wrapping when necessary */
737 addi r15, r15, 1
738 cmpw r15, r16
739 blt 100f
740 lis r14, tlbcam_index@h
741 ori r14, r14, tlbcam_index@l
742 lwz r15, 0(r14)
743 100: stw r15, 0(r17)
744
745 /*
746 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
747 * tlb_enc = (pshift - 10).
748 */
749 subi r15, r10, 10
750 mfspr r16, SPRN_MAS1
751 rlwimi r16, r15, 7, 20, 24
752 mtspr SPRN_MAS1, r16
753
754 /* copy the pshift for use later */
755 mr r14, r10
756
757 /* fall through */
758
759 #endif /* CONFIG_HUGETLB_PAGE */
760
761 /*
762 * We set execute, because we don't have the granularity to
763 * properly set this at the page level (Linux problem).
764 * Many of these bits are software only. Bits we don't set
765 * here we (properly should) assume have the appropriate value.
766 */
767 finish_tlb_load_cont:
768 #ifdef CONFIG_PTE_64BIT
769 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
770 andi. r10, r11, _PAGE_DIRTY
771 bne 1f
772 li r10, MAS3_SW | MAS3_UW
773 andc r12, r12, r10
774 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
775 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
776 2: mtspr SPRN_MAS3, r12
777 BEGIN_MMU_FTR_SECTION
778 srwi r10, r13, 12 /* grab RPN[12:31] */
779 mtspr SPRN_MAS7, r10
780 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
781 #else
782 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
783 mr r13, r11
784 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
785 and r12, r11, r10
786 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
787 slwi r10, r12, 1
788 or r10, r10, r12
789 iseleq r12, r12, r10
790 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
791 mtspr SPRN_MAS3, r13
792 #endif
793
794 mfspr r12, SPRN_MAS2
795 #ifdef CONFIG_PTE_64BIT
796 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
797 #else
798 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
799 #endif
800 #ifdef CONFIG_HUGETLB_PAGE
801 beq 6, 3f /* don't mask if page isn't huge */
802 li r13, 1
803 slw r13, r13, r14
804 subi r13, r13, 1
805 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
806 andc r12, r12, r13 /* mask off ea bits within the page */
807 #endif
808 3: mtspr SPRN_MAS2, r12
809
810 #ifdef CONFIG_E200
811 /* Round robin TLB1 entries assignment */
812 mfspr r12, SPRN_MAS0
813
814 /* Extract TLB1CFG(NENTRY) */
815 mfspr r11, SPRN_TLB1CFG
816 andi. r11, r11, 0xfff
817
818 /* Extract MAS0(NV) */
819 andi. r13, r12, 0xfff
820 addi r13, r13, 1
821 cmpw 0, r13, r11
822 addi r12, r12, 1
823
824 /* check if we need to wrap */
825 blt 7f
826
827 /* wrap back to first free tlbcam entry */
828 lis r13, tlbcam_index@ha
829 lwz r13, tlbcam_index@l(r13)
830 rlwimi r12, r13, 0, 20, 31
831 7:
832 mtspr SPRN_MAS0,r12
833 #endif /* CONFIG_E200 */
834
835 tlb_write_entry:
836 tlbwe
837
838 /* Done...restore registers and get out of here. */
839 mfspr r10, SPRN_SPRG_THREAD
840 #ifdef CONFIG_HUGETLB_PAGE
841 beq 6, 8f /* skip restore for 4k page faults */
842 lwz r14, THREAD_NORMSAVE(4)(r10)
843 lwz r15, THREAD_NORMSAVE(5)(r10)
844 lwz r16, THREAD_NORMSAVE(6)(r10)
845 lwz r17, THREAD_NORMSAVE(7)(r10)
846 #endif
847 8: lwz r11, THREAD_NORMSAVE(3)(r10)
848 mtcr r11
849 lwz r13, THREAD_NORMSAVE(2)(r10)
850 lwz r12, THREAD_NORMSAVE(1)(r10)
851 lwz r11, THREAD_NORMSAVE(0)(r10)
852 mfspr r10, SPRN_SPRG_RSCRATCH0
853 rfi /* Force context change */
854
855 #ifdef CONFIG_SPE
856 /* Note that the SPE support is closely modeled after the AltiVec
857 * support. Changes to one are likely to be applicable to the
858 * other! */
859 _GLOBAL(load_up_spe)
860 /*
861 * Disable SPE for the task which had SPE previously,
862 * and save its SPE registers in its thread_struct.
863 * Enables SPE for use in the kernel on return.
864 * On SMP we know the SPE units are free, since we give it up every
865 * switch. -- Kumar
866 */
867 mfmsr r5
868 oris r5,r5,MSR_SPE@h
869 mtmsr r5 /* enable use of SPE now */
870 isync
871 /* enable use of SPE after return */
872 oris r9,r9,MSR_SPE@h
873 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
874 li r4,1
875 li r10,THREAD_ACC
876 stw r4,THREAD_USED_SPE(r5)
877 evlddx evr4,r10,r5
878 evmra evr4,evr4
879 REST_32EVRS(0,r10,r5,THREAD_EVR0)
880 blr
881
882 /*
883 * SPE unavailable trap from kernel - print a message, but let
884 * the task use SPE in the kernel until it returns to user mode.
885 */
886 KernelSPE:
887 lwz r3,_MSR(r1)
888 oris r3,r3,MSR_SPE@h
889 stw r3,_MSR(r1) /* enable use of SPE after return */
890 #ifdef CONFIG_PRINTK
891 lis r3,87f@h
892 ori r3,r3,87f@l
893 mr r4,r2 /* current */
894 lwz r5,_NIP(r1)
895 bl printk
896 #endif
897 b ret_from_except
898 #ifdef CONFIG_PRINTK
899 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
900 #endif
901 .align 4,0
902
903 #endif /* CONFIG_SPE */
904
905 /*
906 * Translate the effec addr in r3 to phys addr. The phys addr will be put
907 * into r3(higher 32bit) and r4(lower 32bit)
908 */
909 get_phys_addr:
910 mfmsr r8
911 mfspr r9,SPRN_PID
912 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
913 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
914 mtspr SPRN_MAS6,r9
915
916 tlbsx 0,r3 /* must succeed */
917
918 mfspr r8,SPRN_MAS1
919 mfspr r12,SPRN_MAS3
920 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
921 li r10,1024
922 slw r10,r10,r9 /* r10 = page size */
923 addi r10,r10,-1
924 and r11,r3,r10 /* r11 = page offset */
925 andc r4,r12,r10 /* r4 = page base */
926 or r4,r4,r11 /* r4 = devtree phys addr */
927 #ifdef CONFIG_PHYS_64BIT
928 mfspr r3,SPRN_MAS7
929 #endif
930 blr
931
932 /*
933 * Global functions
934 */
935
936 #ifdef CONFIG_E200
937 /* Adjust or setup IVORs for e200 */
938 _GLOBAL(__setup_e200_ivors)
939 li r3,DebugDebug@l
940 mtspr SPRN_IVOR15,r3
941 li r3,SPEUnavailable@l
942 mtspr SPRN_IVOR32,r3
943 li r3,SPEFloatingPointData@l
944 mtspr SPRN_IVOR33,r3
945 li r3,SPEFloatingPointRound@l
946 mtspr SPRN_IVOR34,r3
947 sync
948 blr
949 #endif
950
951 #ifdef CONFIG_E500
952 #ifndef CONFIG_PPC_E500MC
953 /* Adjust or setup IVORs for e500v1/v2 */
954 _GLOBAL(__setup_e500_ivors)
955 li r3,DebugCrit@l
956 mtspr SPRN_IVOR15,r3
957 li r3,SPEUnavailable@l
958 mtspr SPRN_IVOR32,r3
959 li r3,SPEFloatingPointData@l
960 mtspr SPRN_IVOR33,r3
961 li r3,SPEFloatingPointRound@l
962 mtspr SPRN_IVOR34,r3
963 li r3,PerformanceMonitor@l
964 mtspr SPRN_IVOR35,r3
965 sync
966 blr
967 #else
968 /* Adjust or setup IVORs for e500mc */
969 _GLOBAL(__setup_e500mc_ivors)
970 li r3,DebugDebug@l
971 mtspr SPRN_IVOR15,r3
972 li r3,PerformanceMonitor@l
973 mtspr SPRN_IVOR35,r3
974 li r3,Doorbell@l
975 mtspr SPRN_IVOR36,r3
976 li r3,CriticalDoorbell@l
977 mtspr SPRN_IVOR37,r3
978 sync
979 blr
980
981 /* setup ehv ivors for */
982 _GLOBAL(__setup_ehv_ivors)
983 li r3,GuestDoorbell@l
984 mtspr SPRN_IVOR38,r3
985 li r3,CriticalGuestDoorbell@l
986 mtspr SPRN_IVOR39,r3
987 li r3,Hypercall@l
988 mtspr SPRN_IVOR40,r3
989 li r3,Ehvpriv@l
990 mtspr SPRN_IVOR41,r3
991 sync
992 blr
993 #endif /* CONFIG_PPC_E500MC */
994 #endif /* CONFIG_E500 */
995
996 #ifdef CONFIG_SPE
997 /*
998 * extern void __giveup_spe(struct task_struct *prev)
999 *
1000 */
1001 _GLOBAL(__giveup_spe)
1002 addi r3,r3,THREAD /* want THREAD of task */
1003 lwz r5,PT_REGS(r3)
1004 cmpi 0,r5,0
1005 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1006 evxor evr6, evr6, evr6 /* clear out evr6 */
1007 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
1008 li r4,THREAD_ACC
1009 evstddx evr6, r4, r3 /* save off accumulator */
1010 beq 1f
1011 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1012 lis r3,MSR_SPE@h
1013 andc r4,r4,r3 /* disable SPE for previous task */
1014 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1015 1:
1016 blr
1017 #endif /* CONFIG_SPE */
1018
1019 /*
1020 * extern void abort(void)
1021 *
1022 * At present, this routine just applies a system reset.
1023 */
1024 _GLOBAL(abort)
1025 li r13,0
1026 mtspr SPRN_DBCR0,r13 /* disable all debug events */
1027 isync
1028 mfmsr r13
1029 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1030 mtmsr r13
1031 isync
1032 mfspr r13,SPRN_DBCR0
1033 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1034 mtspr SPRN_DBCR0,r13
1035 isync
1036
1037 _GLOBAL(set_context)
1038
1039 #ifdef CONFIG_BDI_SWITCH
1040 /* Context switch the PTE pointer for the Abatron BDI2000.
1041 * The PGDIR is the second parameter.
1042 */
1043 lis r5, abatron_pteptrs@h
1044 ori r5, r5, abatron_pteptrs@l
1045 stw r4, 0x4(r5)
1046 #endif
1047 mtspr SPRN_PID,r3
1048 isync /* Force context change */
1049 blr
1050
1051 #ifdef CONFIG_SMP
1052 /* When we get here, r24 needs to hold the CPU # */
1053 .globl __secondary_start
1054 __secondary_start:
1055 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1056 lwz r3,0(r3)
1057 mtctr r3
1058 li r26,0 /* r26 safe? */
1059
1060 bl switch_to_as1
1061 mr r27,r3 /* tlb entry */
1062 /* Load each CAM entry */
1063 1: mr r3,r26
1064 bl loadcam_entry
1065 addi r26,r26,1
1066 bdnz 1b
1067 mr r3,r27 /* tlb entry */
1068 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1069 lwz r4,0(r4)
1070 mr r5,r25 /* phys kernel start */
1071 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1072 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1073 lis r7,KERNELBASE@h
1074 ori r7,r7,KERNELBASE@l
1075 cmpw r20,r7 /* if kernstart_virt_addr != KERNELBASE, randomized */
1076 beq 2f
1077 li r4,0
1078 2: li r5,0 /* no device tree */
1079 li r6,0 /* not boot cpu */
1080 bl restore_to_as0
1081
1082
1083 lis r3,__secondary_hold_acknowledge@h
1084 ori r3,r3,__secondary_hold_acknowledge@l
1085 stw r24,0(r3)
1086
1087 li r3,0
1088 mr r4,r24 /* Why? */
1089 bl call_setup_cpu
1090
1091 /* get current's stack and current */
1092 lis r2,secondary_current@ha
1093 lwz r2,secondary_current@l(r2)
1094 lwz r1,TASK_STACK(r2)
1095
1096 /* stack */
1097 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1098 li r0,0
1099 stw r0,0(r1)
1100
1101 /* ptr to current thread */
1102 addi r4,r2,THREAD /* address of our thread_struct */
1103 mtspr SPRN_SPRG_THREAD,r4
1104
1105 /* Setup the defaults for TLB entries */
1106 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1107 mtspr SPRN_MAS4,r4
1108
1109 /* Jump to start_secondary */
1110 lis r4,MSR_KERNEL@h
1111 ori r4,r4,MSR_KERNEL@l
1112 lis r3,start_secondary@h
1113 ori r3,r3,start_secondary@l
1114 mtspr SPRN_SRR0,r3
1115 mtspr SPRN_SRR1,r4
1116 sync
1117 rfi
1118 sync
1119
1120 .globl __secondary_hold_acknowledge
1121 __secondary_hold_acknowledge:
1122 .long -1
1123 #endif
1124
1125 /*
1126 * Create a 64M tlb by address and entry
1127 * r3 - entry
1128 * r4 - virtual address
1129 * r5/r6 - physical address
1130 */
1131 _GLOBAL(create_kaslr_tlb_entry)
1132 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
1133 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
1134 mtspr SPRN_MAS0,r7 /* Write MAS0 */
1135
1136 lis r3,(MAS1_VALID|MAS1_IPROT)@h
1137 ori r3,r3,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
1138 mtspr SPRN_MAS1,r3 /* Write MAS1 */
1139
1140 lis r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h
1141 ori r3,r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l
1142 and r3,r3,r4
1143 ori r3,r3,MAS2_M_IF_NEEDED@l
1144 mtspr SPRN_MAS2,r3 /* Write MAS2(EPN) */
1145
1146 #ifdef CONFIG_PHYS_64BIT
1147 ori r8,r6,(MAS3_SW|MAS3_SR|MAS3_SX)
1148 mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */
1149 mtspr SPRN_MAS7,r5
1150 #else
1151 ori r8,r5,(MAS3_SW|MAS3_SR|MAS3_SX)
1152 mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */
1153 #endif
1154
1155 tlbwe /* Write TLB */
1156 isync
1157 sync
1158 blr
1159
1160 /*
1161 * Return to the start of the relocated kernel and run again
1162 * r3 - virtual address of fdt
1163 * r4 - entry of the kernel
1164 */
1165 _GLOBAL(reloc_kernel_entry)
1166 mfmsr r7
1167 rlwinm r7, r7, 0, ~(MSR_IS | MSR_DS)
1168
1169 mtspr SPRN_SRR0,r4
1170 mtspr SPRN_SRR1,r7
1171 rfi
1172
1173 /*
1174 * Create a tlb entry with the same effective and physical address as
1175 * the tlb entry used by the current running code. But set the TS to 1.
1176 * Then switch to the address space 1. It will return with the r3 set to
1177 * the ESEL of the new created tlb.
1178 */
1179 _GLOBAL(switch_to_as1)
1180 mflr r5
1181
1182 /* Find a entry not used */
1183 mfspr r3,SPRN_TLB1CFG
1184 andi. r3,r3,0xfff
1185 mfspr r4,SPRN_PID
1186 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1187 mtspr SPRN_MAS6,r4
1188 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1189 addi r3,r3,-1
1190 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1191 mtspr SPRN_MAS0,r4
1192 tlbre
1193 mfspr r4,SPRN_MAS1
1194 andis. r4,r4,MAS1_VALID@h
1195 bne 1b
1196
1197 /* Get the tlb entry used by the current running code */
1198 bl 0f
1199 0: mflr r4
1200 tlbsx 0,r4
1201
1202 mfspr r4,SPRN_MAS1
1203 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1204 mtspr SPRN_MAS1,r4
1205
1206 mfspr r4,SPRN_MAS0
1207 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1208 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1209 mtspr SPRN_MAS0,r4
1210 tlbwe
1211 isync
1212 sync
1213
1214 mfmsr r4
1215 ori r4,r4,MSR_IS | MSR_DS
1216 mtspr SPRN_SRR0,r5
1217 mtspr SPRN_SRR1,r4
1218 sync
1219 rfi
1220
1221 /*
1222 * Restore to the address space 0 and also invalidate the tlb entry created
1223 * by switch_to_as1.
1224 * r3 - the tlb entry which should be invalidated
1225 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1226 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1227 * r6 - boot cpu
1228 */
1229 _GLOBAL(restore_to_as0)
1230 mflr r0
1231
1232 bl 0f
1233 0: mflr r9
1234 addi r9,r9,1f - 0b
1235
1236 /*
1237 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1238 * so we need calculate the right jump and device tree address based
1239 * on the offset passed by r4.
1240 */
1241 add r9,r9,r4
1242 add r5,r5,r4
1243 add r0,r0,r4
1244
1245 2: mfmsr r7
1246 li r8,(MSR_IS | MSR_DS)
1247 andc r7,r7,r8
1248
1249 mtspr SPRN_SRR0,r9
1250 mtspr SPRN_SRR1,r7
1251 sync
1252 rfi
1253
1254 /* Invalidate the temporary tlb entry for AS1 */
1255 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1256 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1257 mtspr SPRN_MAS0,r9
1258 tlbre
1259 mfspr r9,SPRN_MAS1
1260 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1261 mtspr SPRN_MAS1,r9
1262 tlbwe
1263 isync
1264
1265 cmpwi r4,0
1266 cmpwi cr1,r6,0
1267 cror eq,4*cr1+eq,eq
1268 bne 3f /* offset != 0 && is_boot_cpu */
1269 mtlr r0
1270 blr
1271
1272 /*
1273 * The PAGE_OFFSET will map to a different physical address,
1274 * jump to _start to do another relocation again.
1275 */
1276 3: mr r3,r5
1277 bl _start
1278
1279 /*
1280 * We put a few things here that have to be page-aligned. This stuff
1281 * goes at the beginning of the data segment, which is page-aligned.
1282 */
1283 .data
1284 .align 12
1285 .globl sdata
1286 sdata:
1287 .globl empty_zero_page
1288 empty_zero_page:
1289 .space 4096
1290 EXPORT_SYMBOL(empty_zero_page)
1291 .globl swapper_pg_dir
1292 swapper_pg_dir:
1293 .space PGD_TABLE_SIZE
1294
1295 /*
1296 * Room for two PTE pointers, usually the kernel and current user pointers
1297 * to their respective root page table.
1298 */
1299 abatron_pteptrs:
1300 .space 8
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