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1 /*
2 * Kernel execution entry point code.
3 *
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Rewritten for PReP
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
26 *
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
31 */
32
33 #include <linux/init.h>
34 #include <linux/threads.h>
35 #include <asm/processor.h>
36 #include <asm/page.h>
37 #include <asm/mmu.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/cache.h>
44 #include <asm/ptrace.h>
45 #include "head_booke.h"
46
47 /* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
50 *
51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 * r4 - Starting address of the init RAM disk
53 * r5 - Ending address of the init RAM disk
54 * r6 - Start of kernel command line string (e.g. "mem=128")
55 * r7 - End of kernel command line string
56 *
57 */
58 __HEAD
59 _ENTRY(_stext);
60 _ENTRY(_start);
61 /*
62 * Reserve a word at a fixed location to store the address
63 * of abatron_pteptrs
64 */
65 nop
66 /*
67 * Save parameters we are passed
68 */
69 mr r31,r3
70 mr r30,r4
71 mr r29,r5
72 mr r28,r6
73 mr r27,r7
74 li r25,0 /* phys kernel start (low) */
75 li r24,0 /* CPU number */
76 li r23,0 /* phys kernel start (high) */
77
78 /* We try to not make any assumptions about how the boot loader
79 * setup or used the TLBs. We invalidate all mappings from the
80 * boot loader and load a single entry in TLB1[0] to map the
81 * first 64M of kernel memory. Any boot info passed from the
82 * bootloader needs to live in this first 64M.
83 *
84 * Requirement on bootloader:
85 * - The page we're executing in needs to reside in TLB1 and
86 * have IPROT=1. If not an invalidate broadcast could
87 * evict the entry we're currently executing in.
88 *
89 * r3 = Index of TLB1 were executing in
90 * r4 = Current MSR[IS]
91 * r5 = Index of TLB1 temp mapping
92 *
93 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
94 * if needed
95 */
96
97 _ENTRY(__early_start)
98
99 #define ENTRY_MAPPING_BOOT_SETUP
100 #include "fsl_booke_entry_mapping.S"
101 #undef ENTRY_MAPPING_BOOT_SETUP
102
103 /* Establish the interrupt vector offsets */
104 SET_IVOR(0, CriticalInput);
105 SET_IVOR(1, MachineCheck);
106 SET_IVOR(2, DataStorage);
107 SET_IVOR(3, InstructionStorage);
108 SET_IVOR(4, ExternalInput);
109 SET_IVOR(5, Alignment);
110 SET_IVOR(6, Program);
111 SET_IVOR(7, FloatingPointUnavailable);
112 SET_IVOR(8, SystemCall);
113 SET_IVOR(9, AuxillaryProcessorUnavailable);
114 SET_IVOR(10, Decrementer);
115 SET_IVOR(11, FixedIntervalTimer);
116 SET_IVOR(12, WatchdogTimer);
117 SET_IVOR(13, DataTLBError);
118 SET_IVOR(14, InstructionTLBError);
119 SET_IVOR(15, DebugCrit);
120
121 /* Establish the interrupt vector base */
122 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
123 mtspr SPRN_IVPR,r4
124
125 /* Setup the defaults for TLB entries */
126 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
127 #ifdef CONFIG_E200
128 oris r2,r2,MAS4_TLBSELD(1)@h
129 #endif
130 mtspr SPRN_MAS4, r2
131
132 #if 0
133 /* Enable DOZE */
134 mfspr r2,SPRN_HID0
135 oris r2,r2,HID0_DOZE@h
136 mtspr SPRN_HID0, r2
137 #endif
138
139 #if !defined(CONFIG_BDI_SWITCH)
140 /*
141 * The Abatron BDI JTAG debugger does not tolerate others
142 * mucking with the debug registers.
143 */
144 lis r2,DBCR0_IDM@h
145 mtspr SPRN_DBCR0,r2
146 isync
147 /* clear any residual debug events */
148 li r2,-1
149 mtspr SPRN_DBSR,r2
150 #endif
151
152 #ifdef CONFIG_SMP
153 /* Check to see if we're the second processor, and jump
154 * to the secondary_start code if so
155 */
156 lis r24, boot_cpuid@h
157 ori r24, r24, boot_cpuid@l
158 lwz r24, 0(r24)
159 cmpwi r24, -1
160 mfspr r24,SPRN_PIR
161 bne __secondary_start
162 #endif
163
164 /*
165 * This is where the main kernel code starts.
166 */
167
168 /* ptr to current */
169 lis r2,init_task@h
170 ori r2,r2,init_task@l
171
172 /* ptr to current thread */
173 addi r4,r2,THREAD /* init task's THREAD */
174 mtspr SPRN_SPRG_THREAD,r4
175
176 /* stack */
177 lis r1,init_thread_union@h
178 ori r1,r1,init_thread_union@l
179 li r0,0
180 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
181
182 rlwinm r22,r1,0,0,31-THREAD_SHIFT /* current thread_info */
183 stw r24, TI_CPU(r22)
184
185 bl early_init
186
187 #ifdef CONFIG_RELOCATABLE
188 lis r3,kernstart_addr@ha
189 la r3,kernstart_addr@l(r3)
190 #ifdef CONFIG_PHYS_64BIT
191 stw r23,0(r3)
192 stw r25,4(r3)
193 #else
194 stw r25,0(r3)
195 #endif
196 #endif
197
198 /*
199 * Decide what sort of machine this is and initialize the MMU.
200 */
201 mr r3,r31
202 mr r4,r30
203 mr r5,r29
204 mr r6,r28
205 mr r7,r27
206 bl machine_init
207 bl MMU_init
208
209 /* Setup PTE pointers for the Abatron bdiGDB */
210 lis r6, swapper_pg_dir@h
211 ori r6, r6, swapper_pg_dir@l
212 lis r5, abatron_pteptrs@h
213 ori r5, r5, abatron_pteptrs@l
214 lis r4, KERNELBASE@h
215 ori r4, r4, KERNELBASE@l
216 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
217 stw r6, 0(r5)
218
219 /* Let's move on */
220 lis r4,start_kernel@h
221 ori r4,r4,start_kernel@l
222 lis r3,MSR_KERNEL@h
223 ori r3,r3,MSR_KERNEL@l
224 mtspr SPRN_SRR0,r4
225 mtspr SPRN_SRR1,r3
226 rfi /* change context and jump to start_kernel */
227
228 /* Macros to hide the PTE size differences
229 *
230 * FIND_PTE -- walks the page tables given EA & pgdir pointer
231 * r10 -- EA of fault
232 * r11 -- PGDIR pointer
233 * r12 -- free
234 * label 2: is the bailout case
235 *
236 * if we find the pte (fall through):
237 * r11 is low pte word
238 * r12 is pointer to the pte
239 * r10 is the pshift from the PGD, if we're a hugepage
240 */
241 #ifdef CONFIG_PTE_64BIT
242 #ifdef CONFIG_HUGETLB_PAGE
243 #define FIND_PTE \
244 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
245 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
246 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
247 blt 1000f; /* Normal non-huge page */ \
248 beq 2f; /* Bail if no table */ \
249 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
250 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
251 xor r12, r10, r11; /* drop size bits from pointer */ \
252 b 1001f; \
253 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
254 li r10, 0; /* clear r10 */ \
255 1001: lwz r11, 4(r12); /* Get pte entry */
256 #else
257 #define FIND_PTE \
258 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
259 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
260 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
261 beq 2f; /* Bail if no table */ \
262 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
263 lwz r11, 4(r12); /* Get pte entry */
264 #endif /* HUGEPAGE */
265 #else /* !PTE_64BIT */
266 #define FIND_PTE \
267 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
268 lwz r11, 0(r11); /* Get L1 entry */ \
269 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
270 beq 2f; /* Bail if no table */ \
271 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
272 lwz r11, 0(r12); /* Get Linux PTE */
273 #endif
274
275 /*
276 * Interrupt vector entry code
277 *
278 * The Book E MMUs are always on so we don't need to handle
279 * interrupts in real mode as with previous PPC processors. In
280 * this case we handle interrupts in the kernel virtual address
281 * space.
282 *
283 * Interrupt vectors are dynamically placed relative to the
284 * interrupt prefix as determined by the address of interrupt_base.
285 * The interrupt vectors offsets are programmed using the labels
286 * for each interrupt vector entry.
287 *
288 * Interrupt vectors must be aligned on a 16 byte boundary.
289 * We align on a 32 byte cache line boundary for good measure.
290 */
291
292 interrupt_base:
293 /* Critical Input Interrupt */
294 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
295
296 /* Machine Check Interrupt */
297 #ifdef CONFIG_E200
298 /* no RFMCI, MCSRRs on E200 */
299 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
300 #else
301 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
302 #endif
303
304 /* Data Storage Interrupt */
305 START_EXCEPTION(DataStorage)
306 NORMAL_EXCEPTION_PROLOG
307 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
308 stw r5,_ESR(r11)
309 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
310 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
311 bne 1f
312 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
313 1:
314 addi r3,r1,STACK_FRAME_OVERHEAD
315 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
316
317 /* Instruction Storage Interrupt */
318 INSTRUCTION_STORAGE_EXCEPTION
319
320 /* External Input Interrupt */
321 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
322
323 /* Alignment Interrupt */
324 ALIGNMENT_EXCEPTION
325
326 /* Program Interrupt */
327 PROGRAM_EXCEPTION
328
329 /* Floating Point Unavailable Interrupt */
330 #ifdef CONFIG_PPC_FPU
331 FP_UNAVAILABLE_EXCEPTION
332 #else
333 #ifdef CONFIG_E200
334 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
335 EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
336 #else
337 EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
338 #endif
339 #endif
340
341 /* System Call Interrupt */
342 START_EXCEPTION(SystemCall)
343 NORMAL_EXCEPTION_PROLOG
344 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
345
346 /* Auxiliary Processor Unavailable Interrupt */
347 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
348
349 /* Decrementer Interrupt */
350 DECREMENTER_EXCEPTION
351
352 /* Fixed Internal Timer Interrupt */
353 /* TODO: Add FIT support */
354 EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
355
356 /* Watchdog Timer Interrupt */
357 #ifdef CONFIG_BOOKE_WDT
358 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
359 #else
360 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
361 #endif
362
363 /* Data TLB Error Interrupt */
364 START_EXCEPTION(DataTLBError)
365 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
366 mfspr r10, SPRN_SPRG_THREAD
367 stw r11, THREAD_NORMSAVE(0)(r10)
368 stw r12, THREAD_NORMSAVE(1)(r10)
369 stw r13, THREAD_NORMSAVE(2)(r10)
370 mfcr r13
371 stw r13, THREAD_NORMSAVE(3)(r10)
372 mfspr r10, SPRN_DEAR /* Get faulting address */
373
374 /* If we are faulting a kernel address, we have to use the
375 * kernel page tables.
376 */
377 lis r11, PAGE_OFFSET@h
378 cmplw 5, r10, r11
379 blt 5, 3f
380 lis r11, swapper_pg_dir@h
381 ori r11, r11, swapper_pg_dir@l
382
383 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
384 rlwinm r12,r12,0,16,1
385 mtspr SPRN_MAS1,r12
386
387 b 4f
388
389 /* Get the PGD for the current thread */
390 3:
391 mfspr r11,SPRN_SPRG_THREAD
392 lwz r11,PGDIR(r11)
393
394 4:
395 /* Mask of required permission bits. Note that while we
396 * do copy ESR:ST to _PAGE_RW position as trying to write
397 * to an RO page is pretty common, we don't do it with
398 * _PAGE_DIRTY. We could do it, but it's a fairly rare
399 * event so I'd rather take the overhead when it happens
400 * rather than adding an instruction here. We should measure
401 * whether the whole thing is worth it in the first place
402 * as we could avoid loading SPRN_ESR completely in the first
403 * place...
404 *
405 * TODO: Is it worth doing that mfspr & rlwimi in the first
406 * place or can we save a couple of instructions here ?
407 */
408 mfspr r12,SPRN_ESR
409 #ifdef CONFIG_PTE_64BIT
410 li r13,_PAGE_PRESENT
411 oris r13,r13,_PAGE_ACCESSED@h
412 #else
413 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
414 #endif
415 rlwimi r13,r12,11,29,29
416
417 FIND_PTE
418 andc. r13,r13,r11 /* Check permission */
419
420 #ifdef CONFIG_PTE_64BIT
421 #ifdef CONFIG_SMP
422 subf r13,r11,r12 /* create false data dep */
423 lwzx r13,r11,r13 /* Get upper pte bits */
424 #else
425 lwz r13,0(r12) /* Get upper pte bits */
426 #endif
427 #endif
428
429 bne 2f /* Bail if permission/valid mismach */
430
431 /* Jump to common tlb load */
432 b finish_tlb_load
433 2:
434 /* The bailout. Restore registers to pre-exception conditions
435 * and call the heavyweights to help us out.
436 */
437 mfspr r10, SPRN_SPRG_THREAD
438 lwz r11, THREAD_NORMSAVE(3)(r10)
439 mtcr r11
440 lwz r13, THREAD_NORMSAVE(2)(r10)
441 lwz r12, THREAD_NORMSAVE(1)(r10)
442 lwz r11, THREAD_NORMSAVE(0)(r10)
443 mfspr r10, SPRN_SPRG_RSCRATCH0
444 b DataStorage
445
446 /* Instruction TLB Error Interrupt */
447 /*
448 * Nearly the same as above, except we get our
449 * information from different registers and bailout
450 * to a different point.
451 */
452 START_EXCEPTION(InstructionTLBError)
453 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
454 mfspr r10, SPRN_SPRG_THREAD
455 stw r11, THREAD_NORMSAVE(0)(r10)
456 stw r12, THREAD_NORMSAVE(1)(r10)
457 stw r13, THREAD_NORMSAVE(2)(r10)
458 mfcr r13
459 stw r13, THREAD_NORMSAVE(3)(r10)
460 mfspr r10, SPRN_SRR0 /* Get faulting address */
461
462 /* If we are faulting a kernel address, we have to use the
463 * kernel page tables.
464 */
465 lis r11, PAGE_OFFSET@h
466 cmplw 5, r10, r11
467 blt 5, 3f
468 lis r11, swapper_pg_dir@h
469 ori r11, r11, swapper_pg_dir@l
470
471 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
472 rlwinm r12,r12,0,16,1
473 mtspr SPRN_MAS1,r12
474
475 /* Make up the required permissions for kernel code */
476 #ifdef CONFIG_PTE_64BIT
477 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
478 oris r13,r13,_PAGE_ACCESSED@h
479 #else
480 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
481 #endif
482 b 4f
483
484 /* Get the PGD for the current thread */
485 3:
486 mfspr r11,SPRN_SPRG_THREAD
487 lwz r11,PGDIR(r11)
488
489 /* Make up the required permissions for user code */
490 #ifdef CONFIG_PTE_64BIT
491 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
492 oris r13,r13,_PAGE_ACCESSED@h
493 #else
494 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
495 #endif
496
497 4:
498 FIND_PTE
499 andc. r13,r13,r11 /* Check permission */
500
501 #ifdef CONFIG_PTE_64BIT
502 #ifdef CONFIG_SMP
503 subf r13,r11,r12 /* create false data dep */
504 lwzx r13,r11,r13 /* Get upper pte bits */
505 #else
506 lwz r13,0(r12) /* Get upper pte bits */
507 #endif
508 #endif
509
510 bne 2f /* Bail if permission mismach */
511
512 /* Jump to common TLB load point */
513 b finish_tlb_load
514
515 2:
516 /* The bailout. Restore registers to pre-exception conditions
517 * and call the heavyweights to help us out.
518 */
519 mfspr r10, SPRN_SPRG_THREAD
520 lwz r11, THREAD_NORMSAVE(3)(r10)
521 mtcr r11
522 lwz r13, THREAD_NORMSAVE(2)(r10)
523 lwz r12, THREAD_NORMSAVE(1)(r10)
524 lwz r11, THREAD_NORMSAVE(0)(r10)
525 mfspr r10, SPRN_SPRG_RSCRATCH0
526 b InstructionStorage
527
528 #ifdef CONFIG_SPE
529 /* SPE Unavailable */
530 START_EXCEPTION(SPEUnavailable)
531 NORMAL_EXCEPTION_PROLOG
532 bne load_up_spe
533 addi r3,r1,STACK_FRAME_OVERHEAD
534 EXC_XFER_EE_LITE(0x2010, KernelSPE)
535 #else
536 EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
537 #endif /* CONFIG_SPE */
538
539 /* SPE Floating Point Data */
540 #ifdef CONFIG_SPE
541 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
542
543 /* SPE Floating Point Round */
544 EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
545 #else
546 EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
547 EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
548 #endif /* CONFIG_SPE */
549
550 /* Performance Monitor */
551 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
552
553 EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD)
554
555 CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception)
556
557 /* Debug Interrupt */
558 DEBUG_DEBUG_EXCEPTION
559 DEBUG_CRIT_EXCEPTION
560
561 /*
562 * Local functions
563 */
564
565 /*
566 * Both the instruction and data TLB miss get to this
567 * point to load the TLB.
568 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
569 * r11 - TLB (info from Linux PTE)
570 * r12 - available to use
571 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
572 * CR5 - results of addr >= PAGE_OFFSET
573 * MAS0, MAS1 - loaded with proper value when we get here
574 * MAS2, MAS3 - will need additional info from Linux PTE
575 * Upon exit, we reload everything and RFI.
576 */
577 finish_tlb_load:
578 #ifdef CONFIG_HUGETLB_PAGE
579 cmpwi 6, r10, 0 /* check for huge page */
580 beq 6, finish_tlb_load_cont /* !huge */
581
582 /* Alas, we need more scratch registers for hugepages */
583 mfspr r12, SPRN_SPRG_THREAD
584 stw r14, THREAD_NORMSAVE(4)(r12)
585 stw r15, THREAD_NORMSAVE(5)(r12)
586 stw r16, THREAD_NORMSAVE(6)(r12)
587 stw r17, THREAD_NORMSAVE(7)(r12)
588
589 /* Get the next_tlbcam_idx percpu var */
590 #ifdef CONFIG_SMP
591 lwz r12, THREAD_INFO-THREAD(r12)
592 lwz r15, TI_CPU(r12)
593 lis r14, __per_cpu_offset@h
594 ori r14, r14, __per_cpu_offset@l
595 rlwinm r15, r15, 2, 0, 29
596 lwzx r16, r14, r15
597 #else
598 li r16, 0
599 #endif
600 lis r17, next_tlbcam_idx@h
601 ori r17, r17, next_tlbcam_idx@l
602 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
603 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
604
605 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
606 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
607 mtspr SPRN_MAS0, r14
608
609 /* Extract TLB1CFG(NENTRY) */
610 mfspr r16, SPRN_TLB1CFG
611 andi. r16, r16, 0xfff
612
613 /* Update next_tlbcam_idx, wrapping when necessary */
614 addi r15, r15, 1
615 cmpw r15, r16
616 blt 100f
617 lis r14, tlbcam_index@h
618 ori r14, r14, tlbcam_index@l
619 lwz r15, 0(r14)
620 100: stw r15, 0(r17)
621
622 /*
623 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
624 * tlb_enc = (pshift - 10).
625 */
626 subi r15, r10, 10
627 mfspr r16, SPRN_MAS1
628 rlwimi r16, r15, 7, 20, 24
629 mtspr SPRN_MAS1, r16
630
631 /* copy the pshift for use later */
632 mr r14, r10
633
634 /* fall through */
635
636 #endif /* CONFIG_HUGETLB_PAGE */
637
638 /*
639 * We set execute, because we don't have the granularity to
640 * properly set this at the page level (Linux problem).
641 * Many of these bits are software only. Bits we don't set
642 * here we (properly should) assume have the appropriate value.
643 */
644 finish_tlb_load_cont:
645 #ifdef CONFIG_PTE_64BIT
646 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
647 andi. r10, r11, _PAGE_DIRTY
648 bne 1f
649 li r10, MAS3_SW | MAS3_UW
650 andc r12, r12, r10
651 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
652 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
653 2: mtspr SPRN_MAS3, r12
654 BEGIN_MMU_FTR_SECTION
655 srwi r10, r13, 12 /* grab RPN[12:31] */
656 mtspr SPRN_MAS7, r10
657 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
658 #else
659 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
660 mr r13, r11
661 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
662 and r12, r11, r10
663 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
664 slwi r10, r12, 1
665 or r10, r10, r12
666 iseleq r12, r12, r10
667 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
668 mtspr SPRN_MAS3, r13
669 #endif
670
671 mfspr r12, SPRN_MAS2
672 #ifdef CONFIG_PTE_64BIT
673 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
674 #else
675 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
676 #endif
677 #ifdef CONFIG_HUGETLB_PAGE
678 beq 6, 3f /* don't mask if page isn't huge */
679 li r13, 1
680 slw r13, r13, r14
681 subi r13, r13, 1
682 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
683 andc r12, r12, r13 /* mask off ea bits within the page */
684 #endif
685 3: mtspr SPRN_MAS2, r12
686
687 #ifdef CONFIG_E200
688 /* Round robin TLB1 entries assignment */
689 mfspr r12, SPRN_MAS0
690
691 /* Extract TLB1CFG(NENTRY) */
692 mfspr r11, SPRN_TLB1CFG
693 andi. r11, r11, 0xfff
694
695 /* Extract MAS0(NV) */
696 andi. r13, r12, 0xfff
697 addi r13, r13, 1
698 cmpw 0, r13, r11
699 addi r12, r12, 1
700
701 /* check if we need to wrap */
702 blt 7f
703
704 /* wrap back to first free tlbcam entry */
705 lis r13, tlbcam_index@ha
706 lwz r13, tlbcam_index@l(r13)
707 rlwimi r12, r13, 0, 20, 31
708 7:
709 mtspr SPRN_MAS0,r12
710 #endif /* CONFIG_E200 */
711
712 tlb_write_entry:
713 tlbwe
714
715 /* Done...restore registers and get out of here. */
716 mfspr r10, SPRN_SPRG_THREAD
717 #ifdef CONFIG_HUGETLB_PAGE
718 beq 6, 8f /* skip restore for 4k page faults */
719 lwz r14, THREAD_NORMSAVE(4)(r10)
720 lwz r15, THREAD_NORMSAVE(5)(r10)
721 lwz r16, THREAD_NORMSAVE(6)(r10)
722 lwz r17, THREAD_NORMSAVE(7)(r10)
723 #endif
724 8: lwz r11, THREAD_NORMSAVE(3)(r10)
725 mtcr r11
726 lwz r13, THREAD_NORMSAVE(2)(r10)
727 lwz r12, THREAD_NORMSAVE(1)(r10)
728 lwz r11, THREAD_NORMSAVE(0)(r10)
729 mfspr r10, SPRN_SPRG_RSCRATCH0
730 rfi /* Force context change */
731
732 #ifdef CONFIG_SPE
733 /* Note that the SPE support is closely modeled after the AltiVec
734 * support. Changes to one are likely to be applicable to the
735 * other! */
736 load_up_spe:
737 /*
738 * Disable SPE for the task which had SPE previously,
739 * and save its SPE registers in its thread_struct.
740 * Enables SPE for use in the kernel on return.
741 * On SMP we know the SPE units are free, since we give it up every
742 * switch. -- Kumar
743 */
744 mfmsr r5
745 oris r5,r5,MSR_SPE@h
746 mtmsr r5 /* enable use of SPE now */
747 isync
748 /*
749 * For SMP, we don't do lazy SPE switching because it just gets too
750 * horrendously complex, especially when a task switches from one CPU
751 * to another. Instead we call giveup_spe in switch_to.
752 */
753 #ifndef CONFIG_SMP
754 lis r3,last_task_used_spe@ha
755 lwz r4,last_task_used_spe@l(r3)
756 cmpi 0,r4,0
757 beq 1f
758 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
759 SAVE_32EVRS(0,r10,r4,THREAD_EVR0)
760 evxor evr10, evr10, evr10 /* clear out evr10 */
761 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
762 li r5,THREAD_ACC
763 evstddx evr10, r4, r5 /* save off accumulator */
764 lwz r5,PT_REGS(r4)
765 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
766 lis r10,MSR_SPE@h
767 andc r4,r4,r10 /* disable SPE for previous task */
768 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
769 1:
770 #endif /* !CONFIG_SMP */
771 /* enable use of SPE after return */
772 oris r9,r9,MSR_SPE@h
773 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
774 li r4,1
775 li r10,THREAD_ACC
776 stw r4,THREAD_USED_SPE(r5)
777 evlddx evr4,r10,r5
778 evmra evr4,evr4
779 REST_32EVRS(0,r10,r5,THREAD_EVR0)
780 #ifndef CONFIG_SMP
781 subi r4,r5,THREAD
782 stw r4,last_task_used_spe@l(r3)
783 #endif /* !CONFIG_SMP */
784 /* restore registers and return */
785 2: REST_4GPRS(3, r11)
786 lwz r10,_CCR(r11)
787 REST_GPR(1, r11)
788 mtcr r10
789 lwz r10,_LINK(r11)
790 mtlr r10
791 REST_GPR(10, r11)
792 mtspr SPRN_SRR1,r9
793 mtspr SPRN_SRR0,r12
794 REST_GPR(9, r11)
795 REST_GPR(12, r11)
796 lwz r11,GPR11(r11)
797 rfi
798
799 /*
800 * SPE unavailable trap from kernel - print a message, but let
801 * the task use SPE in the kernel until it returns to user mode.
802 */
803 KernelSPE:
804 lwz r3,_MSR(r1)
805 oris r3,r3,MSR_SPE@h
806 stw r3,_MSR(r1) /* enable use of SPE after return */
807 #ifdef CONFIG_PRINTK
808 lis r3,87f@h
809 ori r3,r3,87f@l
810 mr r4,r2 /* current */
811 lwz r5,_NIP(r1)
812 bl printk
813 #endif
814 b ret_from_except
815 #ifdef CONFIG_PRINTK
816 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
817 #endif
818 .align 4,0
819
820 #endif /* CONFIG_SPE */
821
822 /*
823 * Global functions
824 */
825
826 /* Adjust or setup IVORs for e200 */
827 _GLOBAL(__setup_e200_ivors)
828 li r3,DebugDebug@l
829 mtspr SPRN_IVOR15,r3
830 li r3,SPEUnavailable@l
831 mtspr SPRN_IVOR32,r3
832 li r3,SPEFloatingPointData@l
833 mtspr SPRN_IVOR33,r3
834 li r3,SPEFloatingPointRound@l
835 mtspr SPRN_IVOR34,r3
836 sync
837 blr
838
839 /* Adjust or setup IVORs for e500v1/v2 */
840 _GLOBAL(__setup_e500_ivors)
841 li r3,DebugCrit@l
842 mtspr SPRN_IVOR15,r3
843 li r3,SPEUnavailable@l
844 mtspr SPRN_IVOR32,r3
845 li r3,SPEFloatingPointData@l
846 mtspr SPRN_IVOR33,r3
847 li r3,SPEFloatingPointRound@l
848 mtspr SPRN_IVOR34,r3
849 li r3,PerformanceMonitor@l
850 mtspr SPRN_IVOR35,r3
851 sync
852 blr
853
854 /* Adjust or setup IVORs for e500mc */
855 _GLOBAL(__setup_e500mc_ivors)
856 li r3,DebugDebug@l
857 mtspr SPRN_IVOR15,r3
858 li r3,PerformanceMonitor@l
859 mtspr SPRN_IVOR35,r3
860 li r3,Doorbell@l
861 mtspr SPRN_IVOR36,r3
862 li r3,CriticalDoorbell@l
863 mtspr SPRN_IVOR37,r3
864 sync
865 blr
866
867 /*
868 * extern void giveup_altivec(struct task_struct *prev)
869 *
870 * The e500 core does not have an AltiVec unit.
871 */
872 _GLOBAL(giveup_altivec)
873 blr
874
875 #ifdef CONFIG_SPE
876 /*
877 * extern void giveup_spe(struct task_struct *prev)
878 *
879 */
880 _GLOBAL(giveup_spe)
881 mfmsr r5
882 oris r5,r5,MSR_SPE@h
883 mtmsr r5 /* enable use of SPE now */
884 isync
885 cmpi 0,r3,0
886 beqlr- /* if no previous owner, done */
887 addi r3,r3,THREAD /* want THREAD of task */
888 lwz r5,PT_REGS(r3)
889 cmpi 0,r5,0
890 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
891 evxor evr6, evr6, evr6 /* clear out evr6 */
892 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
893 li r4,THREAD_ACC
894 evstddx evr6, r4, r3 /* save off accumulator */
895 beq 1f
896 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
897 lis r3,MSR_SPE@h
898 andc r4,r4,r3 /* disable SPE for previous task */
899 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
900 1:
901 #ifndef CONFIG_SMP
902 li r5,0
903 lis r4,last_task_used_spe@ha
904 stw r5,last_task_used_spe@l(r4)
905 #endif /* !CONFIG_SMP */
906 blr
907 #endif /* CONFIG_SPE */
908
909 /*
910 * extern void giveup_fpu(struct task_struct *prev)
911 *
912 * Not all FSL Book-E cores have an FPU
913 */
914 #ifndef CONFIG_PPC_FPU
915 _GLOBAL(giveup_fpu)
916 blr
917 #endif
918
919 /*
920 * extern void abort(void)
921 *
922 * At present, this routine just applies a system reset.
923 */
924 _GLOBAL(abort)
925 li r13,0
926 mtspr SPRN_DBCR0,r13 /* disable all debug events */
927 isync
928 mfmsr r13
929 ori r13,r13,MSR_DE@l /* Enable Debug Events */
930 mtmsr r13
931 isync
932 mfspr r13,SPRN_DBCR0
933 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
934 mtspr SPRN_DBCR0,r13
935 isync
936
937 _GLOBAL(set_context)
938
939 #ifdef CONFIG_BDI_SWITCH
940 /* Context switch the PTE pointer for the Abatron BDI2000.
941 * The PGDIR is the second parameter.
942 */
943 lis r5, abatron_pteptrs@h
944 ori r5, r5, abatron_pteptrs@l
945 stw r4, 0x4(r5)
946 #endif
947 mtspr SPRN_PID,r3
948 isync /* Force context change */
949 blr
950
951 _GLOBAL(flush_dcache_L1)
952 mfspr r3,SPRN_L1CFG0
953
954 rlwinm r5,r3,9,3 /* Extract cache block size */
955 twlgti r5,1 /* Only 32 and 64 byte cache blocks
956 * are currently defined.
957 */
958 li r4,32
959 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
960 * log2(number of ways)
961 */
962 slw r5,r4,r5 /* r5 = cache block size */
963
964 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
965 mulli r7,r7,13 /* An 8-way cache will require 13
966 * loads per set.
967 */
968 slw r7,r7,r6
969
970 /* save off HID0 and set DCFA */
971 mfspr r8,SPRN_HID0
972 ori r9,r8,HID0_DCFA@l
973 mtspr SPRN_HID0,r9
974 isync
975
976 lis r4,KERNELBASE@h
977 mtctr r7
978
979 1: lwz r3,0(r4) /* Load... */
980 add r4,r4,r5
981 bdnz 1b
982
983 msync
984 lis r4,KERNELBASE@h
985 mtctr r7
986
987 1: dcbf 0,r4 /* ...and flush. */
988 add r4,r4,r5
989 bdnz 1b
990
991 /* restore HID0 */
992 mtspr SPRN_HID0,r8
993 isync
994
995 blr
996
997 #ifdef CONFIG_SMP
998 /* When we get here, r24 needs to hold the CPU # */
999 .globl __secondary_start
1000 __secondary_start:
1001 lis r3,__secondary_hold_acknowledge@h
1002 ori r3,r3,__secondary_hold_acknowledge@l
1003 stw r24,0(r3)
1004
1005 li r3,0
1006 mr r4,r24 /* Why? */
1007 bl call_setup_cpu
1008
1009 lis r3,tlbcam_index@ha
1010 lwz r3,tlbcam_index@l(r3)
1011 mtctr r3
1012 li r26,0 /* r26 safe? */
1013
1014 /* Load each CAM entry */
1015 1: mr r3,r26
1016 bl loadcam_entry
1017 addi r26,r26,1
1018 bdnz 1b
1019
1020 /* get current_thread_info and current */
1021 lis r1,secondary_ti@ha
1022 lwz r1,secondary_ti@l(r1)
1023 lwz r2,TI_TASK(r1)
1024
1025 /* stack */
1026 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1027 li r0,0
1028 stw r0,0(r1)
1029
1030 /* ptr to current thread */
1031 addi r4,r2,THREAD /* address of our thread_struct */
1032 mtspr SPRN_SPRG_THREAD,r4
1033
1034 /* Setup the defaults for TLB entries */
1035 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1036 mtspr SPRN_MAS4,r4
1037
1038 /* Jump to start_secondary */
1039 lis r4,MSR_KERNEL@h
1040 ori r4,r4,MSR_KERNEL@l
1041 lis r3,start_secondary@h
1042 ori r3,r3,start_secondary@l
1043 mtspr SPRN_SRR0,r3
1044 mtspr SPRN_SRR1,r4
1045 sync
1046 rfi
1047 sync
1048
1049 .globl __secondary_hold_acknowledge
1050 __secondary_hold_acknowledge:
1051 .long -1
1052 #endif
1053
1054 /*
1055 * We put a few things here that have to be page-aligned. This stuff
1056 * goes at the beginning of the data segment, which is page-aligned.
1057 */
1058 .data
1059 .align 12
1060 .globl sdata
1061 sdata:
1062 .globl empty_zero_page
1063 empty_zero_page:
1064 .space 4096
1065 .globl swapper_pg_dir
1066 swapper_pg_dir:
1067 .space PGD_TABLE_SIZE
1068
1069 /*
1070 * Room for two PTE pointers, usually the kernel and current user pointers
1071 * to their respective root page table.
1072 */
1073 abatron_pteptrs:
1074 .space 8
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