arch/powerpc/kernel/head_fsl_booke.S

   1 /*
   2  * Kernel execution entry point code.
   3  *
   4  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   5  *      Initial PowerPC version.
   6  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *      Rewritten for PReP
   8  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   9  *      Low-level exception handers, MMU support, and rewrite.
  10  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  11  *      PowerPC 8xx modifications.
  12  *    Copyright (c) 1998-1999 TiVo, Inc.
  13  *      PowerPC 403GCX modifications.
  14  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  15  *      PowerPC 403GCX/405GP modifications.
  16  *    Copyright 2000 MontaVista Software Inc.
  17  *      PPC405 modifications
  18  *      PowerPC 403GCX/405GP modifications.
  19  *      Author: MontaVista Software, Inc.
  20  *              frank_rowand@mvista.com or source@mvista.com
  21  *              debbie_chu@mvista.com
  22  *    Copyright 2002-2004 MontaVista Software, Inc.
  23  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  24  *    Copyright 2004 Freescale Semiconductor, Inc
  25  *      PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
  26  *
  27  * This program is free software; you can redistribute  it and/or modify it
  28  * under  the terms of  the GNU General  Public License as published by the
  29  * Free Software Foundation;  either version 2 of the  License, or (at your
  30  * option) any later version.
  31  */
  32
  33 #include <linux/threads.h>
  34 #include <asm/processor.h>
  35 #include <asm/page.h>
  36 #include <asm/mmu.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/cputable.h>
  39 #include <asm/thread_info.h>
  40 #include <asm/ppc_asm.h>
  41 #include <asm/asm-offsets.h>
  42 #include "head_booke.h"
  43
  44 /* As with the other PowerPC ports, it is expected that when code
  45  * execution begins here, the following registers contain valid, yet
  46  * optional, information:
  47  *
  48  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  49  *   r4 - Starting address of the init RAM disk
  50  *   r5 - Ending address of the init RAM disk
  51  *   r6 - Start of kernel command line string (e.g. "mem=128")
  52  *   r7 - End of kernel command line string
  53  *
  54  */
  55         .section        .text.head, "ax"
  56 _ENTRY(_stext);
  57 _ENTRY(_start);
  58         /*
  59          * Reserve a word at a fixed location to store the address
  60          * of abatron_pteptrs
  61          */
  62         nop
  63 /*
  64  * Save parameters we are passed
  65  */
  66         mr      r31,r3
  67         mr      r30,r4
  68         mr      r29,r5
  69         mr      r28,r6
  70         mr      r27,r7
  71         li      r25,0           /* phys kernel start (low) */
  72         li      r24,0           /* CPU number */
  73         li      r23,0           /* phys kernel start (high) */
  74
  75 /* We try to not make any assumptions about how the boot loader
  76  * setup or used the TLBs.  We invalidate all mappings from the
  77  * boot loader and load a single entry in TLB1[0] to map the
  78  * first 64M of kernel memory.  Any boot info passed from the
  79  * bootloader needs to live in this first 64M.
  80  *
  81  * Requirement on bootloader:
  82  *  - The page we're executing in needs to reside in TLB1 and
  83  *    have IPROT=1.  If not an invalidate broadcast could
  84  *    evict the entry we're currently executing in.
  85  *
  86  *  r3 = Index of TLB1 were executing in
  87  *  r4 = Current MSR[IS]
  88  *  r5 = Index of TLB1 temp mapping
  89  *
  90  * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
  91  * if needed
  92  */
  93
  94 /* 1. Find the index of the entry we're executing in */
  95         bl      invstr                          /* Find our address */
  96 invstr: mflr    r6                              /* Make it accessible */
  97         mfmsr   r7
  98         rlwinm  r4,r7,27,31,31                  /* extract MSR[IS] */
  99         mfspr   r7, SPRN_PID0
 100         slwi    r7,r7,16
 101         or      r7,r7,r4
 102         mtspr   SPRN_MAS6,r7
 103         tlbsx   0,r6                            /* search MSR[IS], SPID=PID0 */
 104 #ifndef CONFIG_E200
 105         mfspr   r7,SPRN_MAS1
 106         andis.  r7,r7,MAS1_VALID@h
 107         bne     match_TLB
 108         mfspr   r7,SPRN_PID1
 109         slwi    r7,r7,16
 110         or      r7,r7,r4
 111         mtspr   SPRN_MAS6,r7
 112         tlbsx   0,r6                            /* search MSR[IS], SPID=PID1 */
 113         mfspr   r7,SPRN_MAS1
 114         andis.  r7,r7,MAS1_VALID@h
 115         bne     match_TLB
 116         mfspr   r7, SPRN_PID2
 117         slwi    r7,r7,16
 118         or      r7,r7,r4
 119         mtspr   SPRN_MAS6,r7
 120         tlbsx   0,r6                            /* Fall through, we had to match */
 121 #endif
 122 match_TLB:
 123         mfspr   r7,SPRN_MAS0
 124         rlwinm  r3,r7,16,20,31                  /* Extract MAS0(Entry) */
 125
 126         mfspr   r7,SPRN_MAS1                    /* Insure IPROT set */
 127         oris    r7,r7,MAS1_IPROT@h
 128         mtspr   SPRN_MAS1,r7
 129         tlbwe
 130
 131 /* 2. Invalidate all entries except the entry we're executing in */
 132         mfspr   r9,SPRN_TLB1CFG
 133         andi.   r9,r9,0xfff
 134         li      r6,0                            /* Set Entry counter to 0 */
 135 1:      lis     r7,0x1000                       /* Set MAS0(TLBSEL) = 1 */
 136         rlwimi  r7,r6,16,4,15                   /* Setup MAS0 = TLBSEL | ESEL(r6) */
 137         mtspr   SPRN_MAS0,r7
 138         tlbre
 139         mfspr   r7,SPRN_MAS1
 140         rlwinm  r7,r7,0,2,31                    /* Clear MAS1 Valid and IPROT */
 141         cmpw    r3,r6
 142         beq     skpinv                          /* Dont update the current execution TLB */
 143         mtspr   SPRN_MAS1,r7
 144         tlbwe
 145         isync
 146 skpinv: addi    r6,r6,1                         /* Increment */
 147         cmpw    r6,r9                           /* Are we done? */
 148         bne     1b                              /* If not, repeat */
 149
 150         /* Invalidate TLB0 */
 151         li      r6,0x04
 152         tlbivax 0,r6
 153 #ifdef CONFIG_SMP
 154         tlbsync
 155 #endif
 156         /* Invalidate TLB1 */
 157         li      r6,0x0c
 158         tlbivax 0,r6
 159 #ifdef CONFIG_SMP
 160         tlbsync
 161 #endif
 162         msync
 163
 164 /* 3. Setup a temp mapping and jump to it */
 165         andi.   r5, r3, 0x1     /* Find an entry not used and is non-zero */
 166         addi    r5, r5, 0x1
 167         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 168         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 169         mtspr   SPRN_MAS0,r7
 170         tlbre
 171
 172         /* grab and fixup the RPN */
 173         mfspr   r6,SPRN_MAS1    /* extract MAS1[SIZE] */
 174         rlwinm  r6,r6,25,27,30
 175         li      r8,-1
 176         addi    r6,r6,10
 177         slw     r6,r8,r6        /* convert to mask */
 178
 179         bl      1f              /* Find our address */
 180 1:      mflr    r7
 181
 182         mfspr   r8,SPRN_MAS3
 183 #ifdef CONFIG_PHYS_64BIT
 184         mfspr   r23,SPRN_MAS7
 185 #endif
 186         and     r8,r6,r8
 187         subfic  r9,r6,-4096
 188         and     r9,r9,r7
 189
 190         or      r25,r8,r9
 191         ori     r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
 192
 193         /* Just modify the entry ID and EPN for the temp mapping */
 194         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 195         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 196         mtspr   SPRN_MAS0,r7
 197         xori    r6,r4,1         /* Setup TMP mapping in the other Address space */
 198         slwi    r6,r6,12
 199         oris    r6,r6,(MAS1_VALID|MAS1_IPROT)@h
 200         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 201         mtspr   SPRN_MAS1,r6
 202         mfspr   r6,SPRN_MAS2
 203         li      r7,0            /* temp EPN = 0 */
 204         rlwimi  r7,r6,0,20,31
 205         mtspr   SPRN_MAS2,r7
 206         mtspr   SPRN_MAS3,r8
 207         tlbwe
 208
 209         xori    r6,r4,1
 210         slwi    r6,r6,5         /* setup new context with other address space */
 211         bl      1f              /* Find our address */
 212 1:      mflr    r9
 213         rlwimi  r7,r9,0,20,31
 214         addi    r7,r7,24
 215         mtspr   SPRN_SRR0,r7
 216         mtspr   SPRN_SRR1,r6
 217         rfi
 218
 219 /* 4. Clear out PIDs & Search info */
 220         li      r6,0
 221         mtspr   SPRN_PID0,r6
 222 #ifndef CONFIG_E200
 223         mtspr   SPRN_PID1,r6
 224         mtspr   SPRN_PID2,r6
 225 #endif
 226         mtspr   SPRN_MAS6,r6
 227
 228 /* 5. Invalidate mapping we started in */
 229         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 230         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 231         mtspr   SPRN_MAS0,r7
 232         tlbre
 233         mfspr   r6,SPRN_MAS1
 234         rlwinm  r6,r6,0,2,0     /* clear IPROT */
 235         mtspr   SPRN_MAS1,r6
 236         tlbwe
 237         /* Invalidate TLB1 */
 238         li      r9,0x0c
 239         tlbivax 0,r9
 240 #ifdef CONFIG_SMP
 241         tlbsync
 242 #endif
 243         msync
 244
 245 /* 6. Setup KERNELBASE mapping in TLB1[0] */
 246         lis     r6,0x1000               /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
 247         mtspr   SPRN_MAS0,r6
 248         lis     r6,(MAS1_VALID|MAS1_IPROT)@h
 249         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
 250         mtspr   SPRN_MAS1,r6
 251         li      r7,0
 252         lis     r6,PAGE_OFFSET@h
 253         ori     r6,r6,PAGE_OFFSET@l
 254         rlwimi  r6,r7,0,20,31
 255         mtspr   SPRN_MAS2,r6
 256         mtspr   SPRN_MAS3,r8
 257         tlbwe
 258
 259 /* 7. Jump to KERNELBASE mapping */
 260         lis     r6,KERNELBASE@h
 261         ori     r6,r6,KERNELBASE@l
 262         rlwimi  r6,r7,0,20,31
 263         lis     r7,MSR_KERNEL@h
 264         ori     r7,r7,MSR_KERNEL@l
 265         bl      1f                      /* Find our address */
 266 1:      mflr    r9
 267         rlwimi  r6,r9,0,20,31
 268         addi    r6,r6,24
 269         mtspr   SPRN_SRR0,r6
 270         mtspr   SPRN_SRR1,r7
 271         rfi                             /* start execution out of TLB1[0] entry */
 272
 273 /* 8. Clear out the temp mapping */
 274         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 275         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 276         mtspr   SPRN_MAS0,r7
 277         tlbre
 278         mfspr   r8,SPRN_MAS1
 279         rlwinm  r8,r8,0,2,0     /* clear IPROT */
 280         mtspr   SPRN_MAS1,r8
 281         tlbwe
 282         /* Invalidate TLB1 */
 283         li      r9,0x0c
 284         tlbivax 0,r9
 285 #ifdef CONFIG_SMP
 286         tlbsync
 287 #endif
 288         msync
 289
 290         /* Establish the interrupt vector offsets */
 291         SET_IVOR(0,  CriticalInput);
 292         SET_IVOR(1,  MachineCheck);
 293         SET_IVOR(2,  DataStorage);
 294         SET_IVOR(3,  InstructionStorage);
 295         SET_IVOR(4,  ExternalInput);
 296         SET_IVOR(5,  Alignment);
 297         SET_IVOR(6,  Program);
 298         SET_IVOR(7,  FloatingPointUnavailable);
 299         SET_IVOR(8,  SystemCall);
 300         SET_IVOR(9,  AuxillaryProcessorUnavailable);
 301         SET_IVOR(10, Decrementer);
 302         SET_IVOR(11, FixedIntervalTimer);
 303         SET_IVOR(12, WatchdogTimer);
 304         SET_IVOR(13, DataTLBError);
 305         SET_IVOR(14, InstructionTLBError);
 306         SET_IVOR(15, DebugDebug);
 307 #if defined(CONFIG_E500)
 308         SET_IVOR(15, DebugCrit);
 309 #endif
 310         SET_IVOR(32, SPEUnavailable);
 311         SET_IVOR(33, SPEFloatingPointData);
 312         SET_IVOR(34, SPEFloatingPointRound);
 313 #ifndef CONFIG_E200
 314         SET_IVOR(35, PerformanceMonitor);
 315 #endif
 316
 317         /* Establish the interrupt vector base */
 318         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
 319         mtspr   SPRN_IVPR,r4
 320
 321         /* Setup the defaults for TLB entries */
 322         li      r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
 323 #ifdef CONFIG_E200
 324         oris    r2,r2,MAS4_TLBSELD(1)@h
 325 #endif
 326         mtspr   SPRN_MAS4, r2
 327
 328 #if 0
 329         /* Enable DOZE */
 330         mfspr   r2,SPRN_HID0
 331         oris    r2,r2,HID0_DOZE@h
 332         mtspr   SPRN_HID0, r2
 333 #endif
 334 #ifdef CONFIG_E200
 335         /* enable dedicated debug exception handling resources (Debug APU) */
 336         mfspr   r2,SPRN_HID0
 337         ori     r2,r2,HID0_DAPUEN@l
 338         mtspr   SPRN_HID0,r2
 339 #endif
 340
 341 #if !defined(CONFIG_BDI_SWITCH)
 342         /*
 343          * The Abatron BDI JTAG debugger does not tolerate others
 344          * mucking with the debug registers.
 345          */
 346         lis     r2,DBCR0_IDM@h
 347         mtspr   SPRN_DBCR0,r2
 348         isync
 349         /* clear any residual debug events */
 350         li      r2,-1
 351         mtspr   SPRN_DBSR,r2
 352 #endif
 353
 354         /*
 355          * This is where the main kernel code starts.
 356          */
 357
 358         /* ptr to current */
 359         lis     r2,init_task@h
 360         ori     r2,r2,init_task@l
 361
 362         /* ptr to current thread */
 363         addi    r4,r2,THREAD    /* init task's THREAD */
 364         mtspr   SPRN_SPRG3,r4
 365
 366         /* stack */
 367         lis     r1,init_thread_union@h
 368         ori     r1,r1,init_thread_union@l
 369         li      r0,0
 370         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 371
 372         bl      early_init
 373
 374 #ifdef CONFIG_RELOCATABLE
 375         lis     r3,kernstart_addr@ha
 376         la      r3,kernstart_addr@l(r3)
 377 #ifdef CONFIG_PHYS_64BIT
 378         stw     r23,0(r3)
 379         stw     r25,4(r3)
 380 #else
 381         stw     r25,0(r3)
 382 #endif
 383 #endif
 384
 385         mfspr   r3,SPRN_TLB1CFG
 386         andi.   r3,r3,0xfff
 387         lis     r4,num_tlbcam_entries@ha
 388         stw     r3,num_tlbcam_entries@l(r4)
 389 /*
 390  * Decide what sort of machine this is and initialize the MMU.
 391  */
 392         mr      r3,r31
 393         mr      r4,r30
 394         mr      r5,r29
 395         mr      r6,r28
 396         mr      r7,r27
 397         bl      machine_init
 398         bl      MMU_init
 399
 400         /* Setup PTE pointers for the Abatron bdiGDB */
 401         lis     r6, swapper_pg_dir@h
 402         ori     r6, r6, swapper_pg_dir@l
 403         lis     r5, abatron_pteptrs@h
 404         ori     r5, r5, abatron_pteptrs@l
 405         lis     r4, KERNELBASE@h
 406         ori     r4, r4, KERNELBASE@l
 407         stw     r5, 0(r4)       /* Save abatron_pteptrs at a fixed location */
 408         stw     r6, 0(r5)
 409
 410         /* Let's move on */
 411         lis     r4,start_kernel@h
 412         ori     r4,r4,start_kernel@l
 413         lis     r3,MSR_KERNEL@h
 414         ori     r3,r3,MSR_KERNEL@l
 415         mtspr   SPRN_SRR0,r4
 416         mtspr   SPRN_SRR1,r3
 417         rfi                     /* change context and jump to start_kernel */
 418
 419 /* Macros to hide the PTE size differences
 420  *
 421  * FIND_PTE -- walks the page tables given EA & pgdir pointer
 422  *   r10 -- EA of fault
 423  *   r11 -- PGDIR pointer
 424  *   r12 -- free
 425  *   label 2: is the bailout case
 426  *
 427  * if we find the pte (fall through):
 428  *   r11 is low pte word
 429  *   r12 is pointer to the pte
 430  */
 431 #ifdef CONFIG_PTE_64BIT
 432 #define PTE_FLAGS_OFFSET        4
 433 #define FIND_PTE        \
 434         rlwinm  r12, r10, 13, 19, 29;   /* Compute pgdir/pmd offset */  \
 435         lwzx    r11, r12, r11;          /* Get pgd/pmd entry */         \
 436         rlwinm. r12, r11, 0, 0, 20;     /* Extract pt base address */   \
 437         beq     2f;                     /* Bail if no table */          \
 438         rlwimi  r12, r10, 23, 20, 28;   /* Compute pte address */       \
 439         lwz     r11, 4(r12);            /* Get pte entry */
 440 #else
 441 #define PTE_FLAGS_OFFSET        0
 442 #define FIND_PTE        \
 443         rlwimi  r11, r10, 12, 20, 29;   /* Create L1 (pgdir/pmd) address */     \
 444         lwz     r11, 0(r11);            /* Get L1 entry */                      \
 445         rlwinm. r12, r11, 0, 0, 19;     /* Extract L2 (pte) base address */     \
 446         beq     2f;                     /* Bail if no table */                  \
 447         rlwimi  r12, r10, 22, 20, 29;   /* Compute PTE address */               \
 448         lwz     r11, 0(r12);            /* Get Linux PTE */
 449 #endif
 450
 451 /*
 452  * Interrupt vector entry code
 453  *
 454  * The Book E MMUs are always on so we don't need to handle
 455  * interrupts in real mode as with previous PPC processors. In
 456  * this case we handle interrupts in the kernel virtual address
 457  * space.
 458  *
 459  * Interrupt vectors are dynamically placed relative to the
 460  * interrupt prefix as determined by the address of interrupt_base.
 461  * The interrupt vectors offsets are programmed using the labels
 462  * for each interrupt vector entry.
 463  *
 464  * Interrupt vectors must be aligned on a 16 byte boundary.
 465  * We align on a 32 byte cache line boundary for good measure.
 466  */
 467
 468 interrupt_base:
 469         /* Critical Input Interrupt */
 470         CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
 471
 472         /* Machine Check Interrupt */
 473 #ifdef CONFIG_E200
 474         /* no RFMCI, MCSRRs on E200 */
 475         CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 476 #else
 477         MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 478 #endif
 479
 480         /* Data Storage Interrupt */
 481         START_EXCEPTION(DataStorage)
 482         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 483         mtspr   SPRN_SPRG1, r11
 484         mtspr   SPRN_SPRG4W, r12
 485         mtspr   SPRN_SPRG5W, r13
 486         mfcr    r11
 487         mtspr   SPRN_SPRG7W, r11
 488
 489         /*
 490          * Check if it was a store fault, if not then bail
 491          * because a user tried to access a kernel or
 492          * read-protected page.  Otherwise, get the
 493          * offending address and handle it.
 494          */
 495         mfspr   r10, SPRN_ESR
 496         andis.  r10, r10, ESR_ST@h
 497         beq     2f
 498
 499         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 500
 501         /* If we are faulting a kernel address, we have to use the
 502          * kernel page tables.
 503          */
 504         lis     r11, PAGE_OFFSET@h
 505         cmplw   0, r10, r11
 506         bge     2f
 507
 508         /* Get the PGD for the current thread */
 509 3:
 510         mfspr   r11,SPRN_SPRG3
 511         lwz     r11,PGDIR(r11)
 512 4:
 513         FIND_PTE
 514
 515         /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
 516         andi.   r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
 517         cmpwi   0, r13, _PAGE_RW|_PAGE_USER
 518         bne     2f                      /* Bail if not */
 519
 520         /* Update 'changed'. */
 521         ori     r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 522         stw     r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
 523
 524         /* MAS2 not updated as the entry does exist in the tlb, this
 525            fault taken to detect state transition (eg: COW -> DIRTY)
 526          */
 527         andi.   r11, r11, _PAGE_HWEXEC
 528         rlwimi  r11, r11, 31, 27, 27    /* SX <- _PAGE_HWEXEC */
 529         ori     r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
 530
 531         /* update search PID in MAS6, AS = 0 */
 532         mfspr   r12, SPRN_PID0
 533         slwi    r12, r12, 16
 534         mtspr   SPRN_MAS6, r12
 535
 536         /* find the TLB index that caused the fault.  It has to be here. */
 537         tlbsx   0, r10
 538
 539         /* only update the perm bits, assume the RPN is fine */
 540         mfspr   r12, SPRN_MAS3
 541         rlwimi  r12, r11, 0, 20, 31
 542         mtspr   SPRN_MAS3,r12
 543         tlbwe
 544
 545         /* Done...restore registers and get out of here.  */
 546         mfspr   r11, SPRN_SPRG7R
 547         mtcr    r11
 548         mfspr   r13, SPRN_SPRG5R
 549         mfspr   r12, SPRN_SPRG4R
 550         mfspr   r11, SPRN_SPRG1
 551         mfspr   r10, SPRN_SPRG0
 552         rfi                     /* Force context change */
 553
 554 2:
 555         /*
 556          * The bailout.  Restore registers to pre-exception conditions
 557          * and call the heavyweights to help us out.
 558          */
 559         mfspr   r11, SPRN_SPRG7R
 560         mtcr    r11
 561         mfspr   r13, SPRN_SPRG5R
 562         mfspr   r12, SPRN_SPRG4R
 563         mfspr   r11, SPRN_SPRG1
 564         mfspr   r10, SPRN_SPRG0
 565         b       data_access
 566
 567         /* Instruction Storage Interrupt */
 568         INSTRUCTION_STORAGE_EXCEPTION
 569
 570         /* External Input Interrupt */
 571         EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
 572
 573         /* Alignment Interrupt */
 574         ALIGNMENT_EXCEPTION
 575
 576         /* Program Interrupt */
 577         PROGRAM_EXCEPTION
 578
 579         /* Floating Point Unavailable Interrupt */
 580 #ifdef CONFIG_PPC_FPU
 581         FP_UNAVAILABLE_EXCEPTION
 582 #else
 583 #ifdef CONFIG_E200
 584         /* E200 treats 'normal' floating point instructions as FP Unavail exception */
 585         EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
 586 #else
 587         EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
 588 #endif
 589 #endif
 590
 591         /* System Call Interrupt */
 592         START_EXCEPTION(SystemCall)
 593         NORMAL_EXCEPTION_PROLOG
 594         EXC_XFER_EE_LITE(0x0c00, DoSyscall)
 595
 596         /* Auxillary Processor Unavailable Interrupt */
 597         EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
 598
 599         /* Decrementer Interrupt */
 600         DECREMENTER_EXCEPTION
 601
 602         /* Fixed Internal Timer Interrupt */
 603         /* TODO: Add FIT support */
 604         EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
 605
 606         /* Watchdog Timer Interrupt */
 607 #ifdef CONFIG_BOOKE_WDT
 608         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
 609 #else
 610         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
 611 #endif
 612
 613         /* Data TLB Error Interrupt */
 614         START_EXCEPTION(DataTLBError)
 615         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 616         mtspr   SPRN_SPRG1, r11
 617         mtspr   SPRN_SPRG4W, r12
 618         mtspr   SPRN_SPRG5W, r13
 619         mfcr    r11
 620         mtspr   SPRN_SPRG7W, r11
 621         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 622
 623         /* If we are faulting a kernel address, we have to use the
 624          * kernel page tables.
 625          */
 626         lis     r11, PAGE_OFFSET@h
 627         cmplw   5, r10, r11
 628         blt     5, 3f
 629         lis     r11, swapper_pg_dir@h
 630         ori     r11, r11, swapper_pg_dir@l
 631
 632         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 633         rlwinm  r12,r12,0,16,1
 634         mtspr   SPRN_MAS1,r12
 635
 636         b       4f
 637
 638         /* Get the PGD for the current thread */
 639 3:
 640         mfspr   r11,SPRN_SPRG3
 641         lwz     r11,PGDIR(r11)
 642
 643 4:
 644         FIND_PTE
 645         andi.   r13, r11, _PAGE_PRESENT /* Is the page present? */
 646         beq     2f                      /* Bail if not present */
 647
 648 #ifdef CONFIG_PTE_64BIT
 649         lwz     r13, 0(r12)
 650 #endif
 651         ori     r11, r11, _PAGE_ACCESSED
 652         stw     r11, PTE_FLAGS_OFFSET(r12)
 653
 654          /* Jump to common tlb load */
 655         b       finish_tlb_load
 656 2:
 657         /* The bailout.  Restore registers to pre-exception conditions
 658          * and call the heavyweights to help us out.
 659          */
 660         mfspr   r11, SPRN_SPRG7R
 661         mtcr    r11
 662         mfspr   r13, SPRN_SPRG5R
 663         mfspr   r12, SPRN_SPRG4R
 664         mfspr   r11, SPRN_SPRG1
 665         mfspr   r10, SPRN_SPRG0
 666         b       data_access
 667
 668         /* Instruction TLB Error Interrupt */
 669         /*
 670          * Nearly the same as above, except we get our
 671          * information from different registers and bailout
 672          * to a different point.
 673          */
 674         START_EXCEPTION(InstructionTLBError)
 675         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 676         mtspr   SPRN_SPRG1, r11
 677         mtspr   SPRN_SPRG4W, r12
 678         mtspr   SPRN_SPRG5W, r13
 679         mfcr    r11
 680         mtspr   SPRN_SPRG7W, r11
 681         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 682
 683         /* If we are faulting a kernel address, we have to use the
 684          * kernel page tables.
 685          */
 686         lis     r11, PAGE_OFFSET@h
 687         cmplw   5, r10, r11
 688         blt     5, 3f
 689         lis     r11, swapper_pg_dir@h
 690         ori     r11, r11, swapper_pg_dir@l
 691
 692         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 693         rlwinm  r12,r12,0,16,1
 694         mtspr   SPRN_MAS1,r12
 695
 696         b       4f
 697
 698         /* Get the PGD for the current thread */
 699 3:
 700         mfspr   r11,SPRN_SPRG3
 701         lwz     r11,PGDIR(r11)
 702
 703 4:
 704         FIND_PTE
 705         andi.   r13, r11, _PAGE_PRESENT /* Is the page present? */
 706         beq     2f                      /* Bail if not present */
 707
 708 #ifdef CONFIG_PTE_64BIT
 709         lwz     r13, 0(r12)
 710 #endif
 711         ori     r11, r11, _PAGE_ACCESSED
 712         stw     r11, PTE_FLAGS_OFFSET(r12)
 713
 714         /* Jump to common TLB load point */
 715         b       finish_tlb_load
 716
 717 2:
 718         /* The bailout.  Restore registers to pre-exception conditions
 719          * and call the heavyweights to help us out.
 720          */
 721         mfspr   r11, SPRN_SPRG7R
 722         mtcr    r11
 723         mfspr   r13, SPRN_SPRG5R
 724         mfspr   r12, SPRN_SPRG4R
 725         mfspr   r11, SPRN_SPRG1
 726         mfspr   r10, SPRN_SPRG0
 727         b       InstructionStorage
 728
 729 #ifdef CONFIG_SPE
 730         /* SPE Unavailable */
 731         START_EXCEPTION(SPEUnavailable)
 732         NORMAL_EXCEPTION_PROLOG
 733         bne     load_up_spe
 734         addi    r3,r1,STACK_FRAME_OVERHEAD
 735         EXC_XFER_EE_LITE(0x2010, KernelSPE)
 736 #else
 737         EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
 738 #endif /* CONFIG_SPE */
 739
 740         /* SPE Floating Point Data */
 741 #ifdef CONFIG_SPE
 742         EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
 743 #else
 744         EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
 745 #endif /* CONFIG_SPE */
 746
 747         /* SPE Floating Point Round */
 748         EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
 749
 750         /* Performance Monitor */
 751         EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
 752
 753
 754         /* Debug Interrupt */
 755         DEBUG_DEBUG_EXCEPTION
 756 #if defined(CONFIG_E500)
 757         DEBUG_CRIT_EXCEPTION
 758 #endif
 759
 760 /*
 761  * Local functions
 762  */
 763
 764         /*
 765          * Data TLB exceptions will bail out to this point
 766          * if they can't resolve the lightweight TLB fault.
 767          */
 768 data_access:
 769         NORMAL_EXCEPTION_PROLOG
 770         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 771         stw     r5,_ESR(r11)
 772         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 773         andis.  r10,r5,(ESR_ILK|ESR_DLK)@h
 774         bne     1f
 775         EXC_XFER_EE_LITE(0x0300, handle_page_fault)
 776 1:
 777         addi    r3,r1,STACK_FRAME_OVERHEAD
 778         EXC_XFER_EE_LITE(0x0300, CacheLockingException)
 779
 780 /*
 781
 782  * Both the instruction and data TLB miss get to this
 783  * point to load the TLB.
 784  *      r10 - EA of fault
 785  *      r11 - TLB (info from Linux PTE)
 786  *      r12, r13 - available to use
 787  *      CR5 - results of addr >= PAGE_OFFSET
 788  *      MAS0, MAS1 - loaded with proper value when we get here
 789  *      MAS2, MAS3 - will need additional info from Linux PTE
 790  *      Upon exit, we reload everything and RFI.
 791  */
 792 finish_tlb_load:
 793         /*
 794          * We set execute, because we don't have the granularity to
 795          * properly set this at the page level (Linux problem).
 796          * Many of these bits are software only.  Bits we don't set
 797          * here we (properly should) assume have the appropriate value.
 798          */
 799
 800         mfspr   r12, SPRN_MAS2
 801 #ifdef CONFIG_PTE_64BIT
 802         rlwimi  r12, r11, 26, 24, 31    /* extract ...WIMGE from pte */
 803 #else
 804         rlwimi  r12, r11, 26, 27, 31    /* extract WIMGE from pte */
 805 #endif
 806         mtspr   SPRN_MAS2, r12
 807
 808         bge     5, 1f
 809
 810         /* is user addr */
 811         andi.   r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
 812         andi.   r10, r11, _PAGE_USER    /* Test for _PAGE_USER */
 813         srwi    r10, r12, 1
 814         or      r12, r12, r10   /* Copy user perms into supervisor */
 815         iseleq  r12, 0, r12
 816         b       2f
 817
 818         /* is kernel addr */
 819 1:      rlwinm  r12, r11, 31, 29, 29    /* Extract _PAGE_HWWRITE into SW */
 820         ori     r12, r12, (MAS3_SX | MAS3_SR)
 821
 822 #ifdef CONFIG_PTE_64BIT
 823 2:      rlwimi  r12, r13, 24, 0, 7      /* grab RPN[32:39] */
 824         rlwimi  r12, r11, 24, 8, 19     /* grab RPN[40:51] */
 825         mtspr   SPRN_MAS3, r12
 826 BEGIN_FTR_SECTION
 827         srwi    r10, r13, 8             /* grab RPN[8:31] */
 828         mtspr   SPRN_MAS7, r10
 829 END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
 830 #else
 831 2:      rlwimi  r11, r12, 0, 20, 31     /* Extract RPN from PTE and merge with perms */
 832         mtspr   SPRN_MAS3, r11
 833 #endif
 834 #ifdef CONFIG_E200
 835         /* Round robin TLB1 entries assignment */
 836         mfspr   r12, SPRN_MAS0
 837
 838         /* Extract TLB1CFG(NENTRY) */
 839         mfspr   r11, SPRN_TLB1CFG
 840         andi.   r11, r11, 0xfff
 841
 842         /* Extract MAS0(NV) */
 843         andi.   r13, r12, 0xfff
 844         addi    r13, r13, 1
 845         cmpw    0, r13, r11
 846         addi    r12, r12, 1
 847
 848         /* check if we need to wrap */
 849         blt     7f
 850
 851         /* wrap back to first free tlbcam entry */
 852         lis     r13, tlbcam_index@ha
 853         lwz     r13, tlbcam_index@l(r13)
 854         rlwimi  r12, r13, 0, 20, 31
 855 7:
 856         mtspr   SPRN_MAS0,r12
 857 #endif /* CONFIG_E200 */
 858
 859         tlbwe
 860
 861         /* Done...restore registers and get out of here.  */
 862         mfspr   r11, SPRN_SPRG7R
 863         mtcr    r11
 864         mfspr   r13, SPRN_SPRG5R
 865         mfspr   r12, SPRN_SPRG4R
 866         mfspr   r11, SPRN_SPRG1
 867         mfspr   r10, SPRN_SPRG0
 868         rfi                                     /* Force context change */
 869
 870 #ifdef CONFIG_SPE
 871 /* Note that the SPE support is closely modeled after the AltiVec
 872  * support.  Changes to one are likely to be applicable to the
 873  * other!  */
 874 load_up_spe:
 875 /*
 876  * Disable SPE for the task which had SPE previously,
 877  * and save its SPE registers in its thread_struct.
 878  * Enables SPE for use in the kernel on return.
 879  * On SMP we know the SPE units are free, since we give it up every
 880  * switch.  -- Kumar
 881  */
 882         mfmsr   r5
 883         oris    r5,r5,MSR_SPE@h
 884         mtmsr   r5                      /* enable use of SPE now */
 885         isync
 886 /*
 887  * For SMP, we don't do lazy SPE switching because it just gets too
 888  * horrendously complex, especially when a task switches from one CPU
 889  * to another.  Instead we call giveup_spe in switch_to.
 890  */
 891 #ifndef CONFIG_SMP
 892         lis     r3,last_task_used_spe@ha
 893         lwz     r4,last_task_used_spe@l(r3)
 894         cmpi    0,r4,0
 895         beq     1f
 896         addi    r4,r4,THREAD    /* want THREAD of last_task_used_spe */
 897         SAVE_32EVRS(0,r10,r4)
 898         evxor   evr10, evr10, evr10     /* clear out evr10 */
 899         evmwumiaa evr10, evr10, evr10   /* evr10 <- ACC = 0 * 0 + ACC */
 900         li      r5,THREAD_ACC
 901         evstddx evr10, r4, r5           /* save off accumulator */
 902         lwz     r5,PT_REGS(r4)
 903         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 904         lis     r10,MSR_SPE@h
 905         andc    r4,r4,r10       /* disable SPE for previous task */
 906         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 907 1:
 908 #endif /* !CONFIG_SMP */
 909         /* enable use of SPE after return */
 910         oris    r9,r9,MSR_SPE@h
 911         mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
 912         li      r4,1
 913         li      r10,THREAD_ACC
 914         stw     r4,THREAD_USED_SPE(r5)
 915         evlddx  evr4,r10,r5
 916         evmra   evr4,evr4
 917         REST_32EVRS(0,r10,r5)
 918 #ifndef CONFIG_SMP
 919         subi    r4,r5,THREAD
 920         stw     r4,last_task_used_spe@l(r3)
 921 #endif /* !CONFIG_SMP */
 922         /* restore registers and return */
 923 2:      REST_4GPRS(3, r11)
 924         lwz     r10,_CCR(r11)
 925         REST_GPR(1, r11)
 926         mtcr    r10
 927         lwz     r10,_LINK(r11)
 928         mtlr    r10
 929         REST_GPR(10, r11)
 930         mtspr   SPRN_SRR1,r9
 931         mtspr   SPRN_SRR0,r12
 932         REST_GPR(9, r11)
 933         REST_GPR(12, r11)
 934         lwz     r11,GPR11(r11)
 935         rfi
 936
 937 /*
 938  * SPE unavailable trap from kernel - print a message, but let
 939  * the task use SPE in the kernel until it returns to user mode.
 940  */
 941 KernelSPE:
 942         lwz     r3,_MSR(r1)
 943         oris    r3,r3,MSR_SPE@h
 944         stw     r3,_MSR(r1)     /* enable use of SPE after return */
 945         lis     r3,87f@h
 946         ori     r3,r3,87f@l
 947         mr      r4,r2           /* current */
 948         lwz     r5,_NIP(r1)
 949         bl      printk
 950         b       ret_from_except
 951 87:     .string "SPE used in kernel  (task=%p, pc=%x)  \n"
 952         .align  4,0
 953
 954 #endif /* CONFIG_SPE */
 955
 956 /*
 957  * Global functions
 958  */
 959
 960 /*
 961  * extern void loadcam_entry(unsigned int index)
 962  *
 963  * Load TLBCAM[index] entry in to the L2 CAM MMU
 964  */
 965 _GLOBAL(loadcam_entry)
 966         lis     r4,TLBCAM@ha
 967         addi    r4,r4,TLBCAM@l
 968         mulli   r5,r3,20
 969         add     r3,r5,r4
 970         lwz     r4,0(r3)
 971         mtspr   SPRN_MAS0,r4
 972         lwz     r4,4(r3)
 973         mtspr   SPRN_MAS1,r4
 974         lwz     r4,8(r3)
 975         mtspr   SPRN_MAS2,r4
 976         lwz     r4,12(r3)
 977         mtspr   SPRN_MAS3,r4
 978         tlbwe
 979         isync
 980         blr
 981
 982 /*
 983  * extern void giveup_altivec(struct task_struct *prev)
 984  *
 985  * The e500 core does not have an AltiVec unit.
 986  */
 987 _GLOBAL(giveup_altivec)
 988         blr
 989
 990 #ifdef CONFIG_SPE
 991 /*
 992  * extern void giveup_spe(struct task_struct *prev)
 993  *
 994  */
 995 _GLOBAL(giveup_spe)
 996         mfmsr   r5
 997         oris    r5,r5,MSR_SPE@h
 998         mtmsr   r5                      /* enable use of SPE now */
 999         isync
1000         cmpi    0,r3,0
1001         beqlr-                          /* if no previous owner, done */
1002         addi    r3,r3,THREAD            /* want THREAD of task */
1003         lwz     r5,PT_REGS(r3)
1004         cmpi    0,r5,0
1005         SAVE_32EVRS(0, r4, r3)
1006         evxor   evr6, evr6, evr6        /* clear out evr6 */
1007         evmwumiaa evr6, evr6, evr6      /* evr6 <- ACC = 0 * 0 + ACC */
1008         li      r4,THREAD_ACC
1009         evstddx evr6, r4, r3            /* save off accumulator */
1010         mfspr   r6,SPRN_SPEFSCR
1011         stw     r6,THREAD_SPEFSCR(r3)   /* save spefscr register value */
1012         beq     1f
1013         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1014         lis     r3,MSR_SPE@h
1015         andc    r4,r4,r3                /* disable SPE for previous task */
1016         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1017 1:
1018 #ifndef CONFIG_SMP
1019         li      r5,0
1020         lis     r4,last_task_used_spe@ha
1021         stw     r5,last_task_used_spe@l(r4)
1022 #endif /* !CONFIG_SMP */
1023         blr
1024 #endif /* CONFIG_SPE */
1025
1026 /*
1027  * extern void giveup_fpu(struct task_struct *prev)
1028  *
1029  * Not all FSL Book-E cores have an FPU
1030  */
1031 #ifndef CONFIG_PPC_FPU
1032 _GLOBAL(giveup_fpu)
1033         blr
1034 #endif
1035
1036 /*
1037  * extern void abort(void)
1038  *
1039  * At present, this routine just applies a system reset.
1040  */
1041 _GLOBAL(abort)
1042         li      r13,0
1043         mtspr   SPRN_DBCR0,r13          /* disable all debug events */
1044         isync
1045         mfmsr   r13
1046         ori     r13,r13,MSR_DE@l        /* Enable Debug Events */
1047         mtmsr   r13
1048         isync
1049         mfspr   r13,SPRN_DBCR0
1050         lis     r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1051         mtspr   SPRN_DBCR0,r13
1052         isync
1053
1054 _GLOBAL(set_context)
1055
1056 #ifdef CONFIG_BDI_SWITCH
1057         /* Context switch the PTE pointer for the Abatron BDI2000.
1058          * The PGDIR is the second parameter.
1059          */
1060         lis     r5, abatron_pteptrs@h
1061         ori     r5, r5, abatron_pteptrs@l
1062         stw     r4, 0x4(r5)
1063 #endif
1064         mtspr   SPRN_PID,r3
1065         isync                   /* Force context change */
1066         blr
1067
1068 /*
1069  * We put a few things here that have to be page-aligned. This stuff
1070  * goes at the beginning of the data segment, which is page-aligned.
1071  */
1072         .data
1073         .align  12
1074         .globl  sdata
1075 sdata:
1076         .globl  empty_zero_page
1077 empty_zero_page:
1078         .space  4096
1079         .globl  swapper_pg_dir
1080 swapper_pg_dir:
1081         .space  PGD_TABLE_SIZE
1082
1083 /* Reserved 4k for the critical exception stack & 4k for the machine
1084  * check stack per CPU for kernel mode exceptions */
1085         .section .bss
1086         .align 12
1087 exception_stack_bottom:
1088         .space  BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS
1089         .globl  exception_stack_top
1090 exception_stack_top:
1091
1092 /*
1093  * Room for two PTE pointers, usually the kernel and current user pointers
1094  * to their respective root page table.
1095  */
1096 abatron_pteptrs:
1097         .space  8