2 * Kernel execution entry point code.
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
33 #include <linux/threads.h>
34 #include <asm/processor.h>
37 #include <asm/pgtable.h>
38 #include <asm/cputable.h>
39 #include <asm/thread_info.h>
40 #include <asm/ppc_asm.h>
41 #include <asm/asm-offsets.h>
42 #include <asm/cache.h>
43 #include "head_booke.h"
45 /* As with the other PowerPC ports, it is expected that when code
46 * execution begins here, the following registers contain valid, yet
47 * optional, information:
49 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
50 * r4 - Starting address of the init RAM disk
51 * r5 - Ending address of the init RAM disk
52 * r6 - Start of kernel command line string (e.g. "mem=128")
53 * r7 - End of kernel command line string
56 .section .text.head, "ax"
60 * Reserve a word at a fixed location to store the address
65 * Save parameters we are passed
72 li r25,0 /* phys kernel start (low) */
73 li r24,0 /* CPU number */
74 li r23,0 /* phys kernel start (high) */
76 /* We try to not make any assumptions about how the boot loader
77 * setup or used the TLBs. We invalidate all mappings from the
78 * boot loader and load a single entry in TLB1[0] to map the
79 * first 64M of kernel memory. Any boot info passed from the
80 * bootloader needs to live in this first 64M.
82 * Requirement on bootloader:
83 * - The page we're executing in needs to reside in TLB1 and
84 * have IPROT=1. If not an invalidate broadcast could
85 * evict the entry we're currently executing in.
87 * r3 = Index of TLB1 were executing in
88 * r4 = Current MSR[IS]
89 * r5 = Index of TLB1 temp mapping
91 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
95 /* 1. Find the index of the entry we're executing in */
96 bl invstr /* Find our address */
97 invstr: mflr r6 /* Make it accessible */
99 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
104 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
107 andis. r7,r7,MAS1_VALID@h
113 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
115 andis. r7,r7,MAS1_VALID@h
121 tlbsx 0,r6 /* Fall through, we had to match */
125 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
127 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
128 oris r7,r7,MAS1_IPROT@h
132 /* 2. Invalidate all entries except the entry we're executing in */
133 mfspr r9,SPRN_TLB1CFG
135 li r6,0 /* Set Entry counter to 0 */
136 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
137 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
141 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
143 beq skpinv /* Dont update the current execution TLB */
147 skpinv: addi r6,r6,1 /* Increment */
148 cmpw r6,r9 /* Are we done? */
149 bne 1b /* If not, repeat */
151 /* Invalidate TLB0 */
155 /* Invalidate TLB1 */
160 /* 3. Setup a temp mapping and jump to it */
161 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
163 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
164 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
168 /* grab and fixup the RPN */
169 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
170 rlwinm r6,r6,25,27,30
173 slw r6,r8,r6 /* convert to mask */
175 bl 1f /* Find our address */
179 #ifdef CONFIG_PHYS_64BIT
187 ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
189 /* Just modify the entry ID and EPN for the temp mapping */
190 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
191 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
193 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
195 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
196 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
199 li r7,0 /* temp EPN = 0 */
206 slwi r6,r6,5 /* setup new context with other address space */
207 bl 1f /* Find our address */
215 /* 4. Clear out PIDs & Search info */
224 /* 5. Invalidate mapping we started in */
225 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
226 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
230 rlwinm r6,r6,0,2,0 /* clear IPROT */
233 /* Invalidate TLB1 */
238 /* The mapping only needs to be cache-coherent on SMP */
240 #define M_IF_SMP MAS2_M
245 /* 6. Setup KERNELBASE mapping in TLB1[0] */
246 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
248 lis r6,(MAS1_VALID|MAS1_IPROT)@h
249 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
251 lis r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@h
252 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@l
257 /* 7. Jump to KERNELBASE mapping */
258 lis r6,(KERNELBASE & ~0xfff)@h
259 ori r6,r6,(KERNELBASE & ~0xfff)@l
261 ori r7,r7,MSR_KERNEL@l
262 bl 1f /* Find our address */
268 rfi /* start execution out of TLB1[0] entry */
270 /* 8. Clear out the temp mapping */
271 2: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
272 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
276 rlwinm r8,r8,0,2,0 /* clear IPROT */
279 /* Invalidate TLB1 */
284 /* Establish the interrupt vector offsets */
285 SET_IVOR(0, CriticalInput);
286 SET_IVOR(1, MachineCheck);
287 SET_IVOR(2, DataStorage);
288 SET_IVOR(3, InstructionStorage);
289 SET_IVOR(4, ExternalInput);
290 SET_IVOR(5, Alignment);
291 SET_IVOR(6, Program);
292 SET_IVOR(7, FloatingPointUnavailable);
293 SET_IVOR(8, SystemCall);
294 SET_IVOR(9, AuxillaryProcessorUnavailable);
295 SET_IVOR(10, Decrementer);
296 SET_IVOR(11, FixedIntervalTimer);
297 SET_IVOR(12, WatchdogTimer);
298 SET_IVOR(13, DataTLBError);
299 SET_IVOR(14, InstructionTLBError);
300 SET_IVOR(15, DebugDebug);
301 #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
302 SET_IVOR(15, DebugCrit);
304 SET_IVOR(32, SPEUnavailable);
305 SET_IVOR(33, SPEFloatingPointData);
306 SET_IVOR(34, SPEFloatingPointRound);
308 SET_IVOR(35, PerformanceMonitor);
310 #ifdef CONFIG_PPC_E500MC
311 SET_IVOR(36, Doorbell);
314 /* Establish the interrupt vector base */
315 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
318 /* Setup the defaults for TLB entries */
319 li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
321 oris r2,r2,MAS4_TLBSELD(1)@h
328 oris r2,r2,HID0_DOZE@h
332 /* enable dedicated debug exception handling resources (Debug APU) */
334 ori r2,r2,HID0_DAPUEN@l
338 #if !defined(CONFIG_BDI_SWITCH)
340 * The Abatron BDI JTAG debugger does not tolerate others
341 * mucking with the debug registers.
346 /* clear any residual debug events */
352 * This is where the main kernel code starts.
357 ori r2,r2,init_task@l
359 /* ptr to current thread */
360 addi r4,r2,THREAD /* init task's THREAD */
364 lis r1,init_thread_union@h
365 ori r1,r1,init_thread_union@l
367 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
371 #ifdef CONFIG_RELOCATABLE
372 lis r3,kernstart_addr@ha
373 la r3,kernstart_addr@l(r3)
374 #ifdef CONFIG_PHYS_64BIT
382 mfspr r3,SPRN_TLB1CFG
384 lis r4,num_tlbcam_entries@ha
385 stw r3,num_tlbcam_entries@l(r4)
387 * Decide what sort of machine this is and initialize the MMU.
397 /* Setup PTE pointers for the Abatron bdiGDB */
398 lis r6, swapper_pg_dir@h
399 ori r6, r6, swapper_pg_dir@l
400 lis r5, abatron_pteptrs@h
401 ori r5, r5, abatron_pteptrs@l
403 ori r4, r4, KERNELBASE@l
404 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
408 lis r4,start_kernel@h
409 ori r4,r4,start_kernel@l
411 ori r3,r3,MSR_KERNEL@l
414 rfi /* change context and jump to start_kernel */
416 /* Macros to hide the PTE size differences
418 * FIND_PTE -- walks the page tables given EA & pgdir pointer
420 * r11 -- PGDIR pointer
422 * label 2: is the bailout case
424 * if we find the pte (fall through):
425 * r11 is low pte word
426 * r12 is pointer to the pte
428 #ifdef CONFIG_PTE_64BIT
430 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
431 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
432 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
433 beq 2f; /* Bail if no table */ \
434 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
435 lwz r11, 4(r12); /* Get pte entry */
438 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
439 lwz r11, 0(r11); /* Get L1 entry */ \
440 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
441 beq 2f; /* Bail if no table */ \
442 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
443 lwz r11, 0(r12); /* Get Linux PTE */
447 * Interrupt vector entry code
449 * The Book E MMUs are always on so we don't need to handle
450 * interrupts in real mode as with previous PPC processors. In
451 * this case we handle interrupts in the kernel virtual address
454 * Interrupt vectors are dynamically placed relative to the
455 * interrupt prefix as determined by the address of interrupt_base.
456 * The interrupt vectors offsets are programmed using the labels
457 * for each interrupt vector entry.
459 * Interrupt vectors must be aligned on a 16 byte boundary.
460 * We align on a 32 byte cache line boundary for good measure.
464 /* Critical Input Interrupt */
465 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
467 /* Machine Check Interrupt */
469 /* no RFMCI, MCSRRs on E200 */
470 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
472 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
475 /* Data Storage Interrupt */
476 START_EXCEPTION(DataStorage)
477 NORMAL_EXCEPTION_PROLOG
478 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
480 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
481 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
483 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
485 addi r3,r1,STACK_FRAME_OVERHEAD
486 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
488 /* Instruction Storage Interrupt */
489 INSTRUCTION_STORAGE_EXCEPTION
491 /* External Input Interrupt */
492 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
494 /* Alignment Interrupt */
497 /* Program Interrupt */
500 /* Floating Point Unavailable Interrupt */
501 #ifdef CONFIG_PPC_FPU
502 FP_UNAVAILABLE_EXCEPTION
505 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
506 EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
508 EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
512 /* System Call Interrupt */
513 START_EXCEPTION(SystemCall)
514 NORMAL_EXCEPTION_PROLOG
515 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
517 /* Auxillary Processor Unavailable Interrupt */
518 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
520 /* Decrementer Interrupt */
521 DECREMENTER_EXCEPTION
523 /* Fixed Internal Timer Interrupt */
524 /* TODO: Add FIT support */
525 EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
527 /* Watchdog Timer Interrupt */
528 #ifdef CONFIG_BOOKE_WDT
529 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
531 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
534 /* Data TLB Error Interrupt */
535 START_EXCEPTION(DataTLBError)
536 mtspr SPRN_SPRG0, r10 /* Save some working registers */
537 mtspr SPRN_SPRG1, r11
538 mtspr SPRN_SPRG4W, r12
539 mtspr SPRN_SPRG5W, r13
541 mtspr SPRN_SPRG7W, r11
542 mfspr r10, SPRN_DEAR /* Get faulting address */
544 /* If we are faulting a kernel address, we have to use the
545 * kernel page tables.
547 lis r11, PAGE_OFFSET@h
550 lis r11, swapper_pg_dir@h
551 ori r11, r11, swapper_pg_dir@l
553 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
554 rlwinm r12,r12,0,16,1
559 /* Get the PGD for the current thread */
565 /* Mask of required permission bits. Note that while we
566 * do copy ESR:ST to _PAGE_RW position as trying to write
567 * to an RO page is pretty common, we don't do it with
568 * _PAGE_DIRTY. We could do it, but it's a fairly rare
569 * event so I'd rather take the overhead when it happens
570 * rather than adding an instruction here. We should measure
571 * whether the whole thing is worth it in the first place
572 * as we could avoid loading SPRN_ESR completely in the first
575 * TODO: Is it worth doing that mfspr & rlwimi in the first
576 * place or can we save a couple of instructions here ?
579 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
580 rlwimi r13,r12,11,29,29
583 andc. r13,r13,r11 /* Check permission */
585 #ifdef CONFIG_PTE_64BIT
587 subf r10,r11,r12 /* create false data dep */
588 lwzx r13,r11,r10 /* Get upper pte bits */
590 lwz r13,0(r12) /* Get upper pte bits */
594 bne 2f /* Bail if permission/valid mismach */
596 /* Jump to common tlb load */
599 /* The bailout. Restore registers to pre-exception conditions
600 * and call the heavyweights to help us out.
602 mfspr r11, SPRN_SPRG7R
604 mfspr r13, SPRN_SPRG5R
605 mfspr r12, SPRN_SPRG4R
606 mfspr r11, SPRN_SPRG1
607 mfspr r10, SPRN_SPRG0
610 /* Instruction TLB Error Interrupt */
612 * Nearly the same as above, except we get our
613 * information from different registers and bailout
614 * to a different point.
616 START_EXCEPTION(InstructionTLBError)
617 mtspr SPRN_SPRG0, r10 /* Save some working registers */
618 mtspr SPRN_SPRG1, r11
619 mtspr SPRN_SPRG4W, r12
620 mtspr SPRN_SPRG5W, r13
622 mtspr SPRN_SPRG7W, r11
623 mfspr r10, SPRN_SRR0 /* Get faulting address */
625 /* If we are faulting a kernel address, we have to use the
626 * kernel page tables.
628 lis r11, PAGE_OFFSET@h
631 lis r11, swapper_pg_dir@h
632 ori r11, r11, swapper_pg_dir@l
634 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
635 rlwinm r12,r12,0,16,1
640 /* Get the PGD for the current thread */
646 /* Make up the required permissions */
647 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
650 andc. r13,r13,r11 /* Check permission */
652 #ifdef CONFIG_PTE_64BIT
654 subf r10,r11,r12 /* create false data dep */
655 lwzx r13,r11,r10 /* Get upper pte bits */
657 lwz r13,0(r12) /* Get upper pte bits */
661 bne 2f /* Bail if permission mismach */
663 /* Jump to common TLB load point */
667 /* The bailout. Restore registers to pre-exception conditions
668 * and call the heavyweights to help us out.
670 mfspr r11, SPRN_SPRG7R
672 mfspr r13, SPRN_SPRG5R
673 mfspr r12, SPRN_SPRG4R
674 mfspr r11, SPRN_SPRG1
675 mfspr r10, SPRN_SPRG0
679 /* SPE Unavailable */
680 START_EXCEPTION(SPEUnavailable)
681 NORMAL_EXCEPTION_PROLOG
683 addi r3,r1,STACK_FRAME_OVERHEAD
684 EXC_XFER_EE_LITE(0x2010, KernelSPE)
686 EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
687 #endif /* CONFIG_SPE */
689 /* SPE Floating Point Data */
691 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
693 /* SPE Floating Point Round */
694 EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
696 EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
697 EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
698 #endif /* CONFIG_SPE */
700 /* Performance Monitor */
701 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
703 #ifdef CONFIG_PPC_E500MC
704 EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_EE)
707 /* Debug Interrupt */
708 DEBUG_DEBUG_EXCEPTION
709 #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
718 * Both the instruction and data TLB miss get to this
719 * point to load the TLB.
720 * r10 - available to use
721 * r11 - TLB (info from Linux PTE)
722 * r12 - available to use
723 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
724 * CR5 - results of addr >= PAGE_OFFSET
725 * MAS0, MAS1 - loaded with proper value when we get here
726 * MAS2, MAS3 - will need additional info from Linux PTE
727 * Upon exit, we reload everything and RFI.
731 * We set execute, because we don't have the granularity to
732 * properly set this at the page level (Linux problem).
733 * Many of these bits are software only. Bits we don't set
734 * here we (properly should) assume have the appropriate value.
738 #ifdef CONFIG_PTE_64BIT
739 rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */
741 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
745 li r10, (_PAGE_HWEXEC | _PAGE_PRESENT)
746 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
748 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
753 #ifdef CONFIG_PTE_64BIT
754 rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */
755 rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */
758 srwi r10, r13, 8 /* grab RPN[8:31] */
760 END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
762 rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
766 /* Round robin TLB1 entries assignment */
769 /* Extract TLB1CFG(NENTRY) */
770 mfspr r11, SPRN_TLB1CFG
771 andi. r11, r11, 0xfff
773 /* Extract MAS0(NV) */
774 andi. r13, r12, 0xfff
779 /* check if we need to wrap */
782 /* wrap back to first free tlbcam entry */
783 lis r13, tlbcam_index@ha
784 lwz r13, tlbcam_index@l(r13)
785 rlwimi r12, r13, 0, 20, 31
788 #endif /* CONFIG_E200 */
792 /* Done...restore registers and get out of here. */
793 mfspr r11, SPRN_SPRG7R
795 mfspr r13, SPRN_SPRG5R
796 mfspr r12, SPRN_SPRG4R
797 mfspr r11, SPRN_SPRG1
798 mfspr r10, SPRN_SPRG0
799 rfi /* Force context change */
802 /* Note that the SPE support is closely modeled after the AltiVec
803 * support. Changes to one are likely to be applicable to the
807 * Disable SPE for the task which had SPE previously,
808 * and save its SPE registers in its thread_struct.
809 * Enables SPE for use in the kernel on return.
810 * On SMP we know the SPE units are free, since we give it up every
815 mtmsr r5 /* enable use of SPE now */
818 * For SMP, we don't do lazy SPE switching because it just gets too
819 * horrendously complex, especially when a task switches from one CPU
820 * to another. Instead we call giveup_spe in switch_to.
823 lis r3,last_task_used_spe@ha
824 lwz r4,last_task_used_spe@l(r3)
827 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
828 SAVE_32EVRS(0,r10,r4)
829 evxor evr10, evr10, evr10 /* clear out evr10 */
830 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
832 evstddx evr10, r4, r5 /* save off accumulator */
834 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
836 andc r4,r4,r10 /* disable SPE for previous task */
837 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
839 #endif /* !CONFIG_SMP */
840 /* enable use of SPE after return */
842 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
845 stw r4,THREAD_USED_SPE(r5)
848 REST_32EVRS(0,r10,r5)
851 stw r4,last_task_used_spe@l(r3)
852 #endif /* !CONFIG_SMP */
853 /* restore registers and return */
854 2: REST_4GPRS(3, r11)
869 * SPE unavailable trap from kernel - print a message, but let
870 * the task use SPE in the kernel until it returns to user mode.
875 stw r3,_MSR(r1) /* enable use of SPE after return */
878 mr r4,r2 /* current */
882 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
885 #endif /* CONFIG_SPE */
892 * extern void loadcam_entry(unsigned int index)
894 * Load TLBCAM[index] entry in to the L2 CAM MMU
896 _GLOBAL(loadcam_entry)
914 * extern void giveup_altivec(struct task_struct *prev)
916 * The e500 core does not have an AltiVec unit.
918 _GLOBAL(giveup_altivec)
923 * extern void giveup_spe(struct task_struct *prev)
929 mtmsr r5 /* enable use of SPE now */
932 beqlr- /* if no previous owner, done */
933 addi r3,r3,THREAD /* want THREAD of task */
936 SAVE_32EVRS(0, r4, r3)
937 evxor evr6, evr6, evr6 /* clear out evr6 */
938 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
940 evstddx evr6, r4, r3 /* save off accumulator */
941 mfspr r6,SPRN_SPEFSCR
942 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
944 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
946 andc r4,r4,r3 /* disable SPE for previous task */
947 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
951 lis r4,last_task_used_spe@ha
952 stw r5,last_task_used_spe@l(r4)
953 #endif /* !CONFIG_SMP */
955 #endif /* CONFIG_SPE */
958 * extern void giveup_fpu(struct task_struct *prev)
960 * Not all FSL Book-E cores have an FPU
962 #ifndef CONFIG_PPC_FPU
968 * extern void abort(void)
970 * At present, this routine just applies a system reset.
974 mtspr SPRN_DBCR0,r13 /* disable all debug events */
977 ori r13,r13,MSR_DE@l /* Enable Debug Events */
981 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
987 #ifdef CONFIG_BDI_SWITCH
988 /* Context switch the PTE pointer for the Abatron BDI2000.
989 * The PGDIR is the second parameter.
991 lis r5, abatron_pteptrs@h
992 ori r5, r5, abatron_pteptrs@l
996 isync /* Force context change */
999 _GLOBAL(flush_dcache_L1)
1000 mfspr r3,SPRN_L1CFG0
1002 rlwinm r5,r3,9,3 /* Extract cache block size */
1003 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1004 * are currently defined.
1007 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1008 * log2(number of ways)
1010 slw r5,r4,r5 /* r5 = cache block size */
1012 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1013 mulli r7,r7,13 /* An 8-way cache will require 13
1018 /* save off HID0 and set DCFA */
1020 ori r9,r8,HID0_DCFA@l
1027 1: lwz r3,0(r4) /* Load... */
1035 1: dcbf 0,r4 /* ...and flush. */
1046 * We put a few things here that have to be page-aligned. This stuff
1047 * goes at the beginning of the data segment, which is page-aligned.
1053 .globl empty_zero_page
1056 .globl swapper_pg_dir
1058 .space PGD_TABLE_SIZE
1061 * Room for two PTE pointers, usually the kernel and current user pointers
1062 * to their respective root page table.