2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/exception-64s.h>
24 #include <asm/book3s/64/mmu-hash.h>
30 * Use unused space in the interrupt stack to save and restore
31 * registers for winkle support.
46 #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
51 * Used by threads before entering deep idle states. Saves SPRs
52 * in interrupt stack frame
56 * Note all register i.e per-core, per-subcore or per-thread is saved
57 * here since any thread in the core might wake up first
61 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
71 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
89 * On POWER9, there are idle states such as stop4, invoked via cpuidle,
90 * that lose hypervisor resources. In such cases, we need to save
91 * additional SPRs before entering those idle states so that they can
92 * be restored to their older values on wakeup from the idle state.
94 * On POWER8, the only such deep idle state is winkle which is used
95 * only in the context of CPU-Hotplug, where these additional SPRs are
96 * reinitiazed to a sane value. Hence there is no need to save/restore
101 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
103 power9_save_additional_sprs:
106 std r3, STOP_PID(r13)
107 std r4, STOP_LDBAR(r13)
111 std r3, STOP_FSCR(r13)
112 std r4, STOP_HFSCR(r13)
116 std r3, STOP_MMCRA(r13)
121 std r3, STOP_MMCR1(r13)
122 std r4, STOP_MMCR2(r13)
125 power9_restore_additional_sprs:
131 ld r3, STOP_LDBAR(r13)
132 ld r4, STOP_FSCR(r13)
136 ld r3, STOP_HFSCR(r13)
137 ld r4, STOP_MMCRA(r13)
142 ld r4, STOP_MMCR1(r13)
146 ld r3, STOP_MMCR2(r13)
151 * Used by threads when the lock bit of core_idle_state is set.
152 * Threads will spin in HMT_LOW until the lock bit is cleared.
153 * r14 - pointer to core_idle_state
154 * r15 - used to load contents of core_idle_state
155 * r9 - used as a temporary variable
161 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
165 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
166 bne- core_idle_lock_held
170 * Pass requested state in r3:
171 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
172 * - Requested PSSCR value in POWER9
174 * Address of idle handler to branch to in realmode in r4
176 pnv_powersave_common:
177 /* Use r3 to pass state nap/sleep/winkle */
178 /* NAP is a state loss, we create a regs frame on the
179 * stack, fill it up with the state we care about and
180 * stick a pointer to it in PACAR1. We really only
181 * need to save PC, some CR bits and the NV GPRs,
182 * but for now an interrupt frame will do.
188 stdu r1,-INT_FRAME_SIZE(r1)
192 /* We haven't lost state ... yet */
194 stb r0,PACA_NAPSTATELOST(r13)
196 /* Continue saving state */
205 * POWER9 does not require real mode to stop, and presently does not
206 * set hwthread_state for KVM (threads don't share MMU context), so
207 * we can remain in virtual mode for this.
210 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
213 * Go to real mode to do the nap, as required by the architecture.
214 * Also, we need to be in real mode before setting hwthread_state,
215 * because as soon as we do that, another thread can switch
216 * the MMU context to the guest.
218 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
223 * This is the sequence required to execute idle instructions, as
224 * specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0.
226 #define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \
227 /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
231 236: cmpd cr0,r0,r0; \
236 .globl pnv_enter_arch207_idle_mode
237 pnv_enter_arch207_idle_mode:
238 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
239 /* Tell KVM we're entering idle */
240 li r4,KVM_HWTHREAD_IN_IDLE
241 /******************************************************/
242 /* N O T E W E L L ! ! ! N O T E W E L L */
243 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
244 /* MUST occur in real mode, i.e. with the MMU off, */
245 /* and the MMU must stay off until we clear this flag */
246 /* and test HSTATE_HWTHREAD_REQ(r13) in */
247 /* pnv_powersave_wakeup in this file. */
248 /* The reason is that another thread can switch the */
249 /* MMU to a guest context whenever this flag is set */
250 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
251 /* that would potentially cause this thread to start */
252 /* executing instructions from guest memory in */
253 /* hypervisor mode, leading to a host crash or data */
254 /* corruption, or worse. */
255 /******************************************************/
256 stb r4,HSTATE_HWTHREAD_STATE(r13)
258 stb r3,PACA_THREAD_IDLE_STATE(r13)
259 cmpwi cr3,r3,PNV_THREAD_SLEEP
261 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
264 /* Sleep or winkle */
265 lbz r7,PACA_THREAD_MASK(r13)
266 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
269 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h
274 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
275 bnel- core_idle_lock_held
277 add r15,r15,r5 /* Add if winkle */
278 andc r15,r15,r7 /* Clear thread bit */
280 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
283 * If cr0 = 0, then current thread is the last thread of the core entering
284 * sleep. Last thread needs to execute the hardware bug workaround code if
285 * required by the platform.
286 * Make the workaround call unconditionally here. The below branch call is
287 * patched out when the idle states are discovered if the platform does not
290 .global pnv_fastsleep_workaround_at_entry
291 pnv_fastsleep_workaround_at_entry:
292 beq fastsleep_workaround_at_entry
298 common_enter: /* common code for all the threads entering sleep or winkle */
300 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
302 fastsleep_workaround_at_entry:
303 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
308 /* Fast sleep workaround */
311 bl opal_config_cpu_idle_state
314 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
320 bl save_sprs_to_stack
322 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
325 * r3 - PSSCR value corresponding to the requested stop state.
328 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
329 /* Tell KVM we're entering idle */
330 li r4,KVM_HWTHREAD_IN_IDLE
331 /* DO THIS IN REAL MODE! See comment above. */
332 stb r4,HSTATE_HWTHREAD_STATE(r13)
335 * Check if we are executing the lite variant with ESL=EC=0
337 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
338 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
339 bne .Lhandle_esl_ec_set
341 li r3,0 /* Since we didn't lose state, return 0 */
342 std r3, PACA_REQ_PSSCR(r13)
345 * pnv_wakeup_noloss() expects r12 to contain the SRR1 value so
346 * it can determine if the wakeup reason is an HMI in
347 * CHECK_HMI_INTERRUPT.
349 * However, when we wakeup with ESL=0, SRR1 will not contain the wakeup
350 * reason, so there is no point setting r12 to SRR1.
352 * Further, we clear r12 here, so that we don't accidentally enter the
353 * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI.
361 * POWER9 DD2.0 or earlier can incorrectly set PMAO when waking up after
362 * a state-loss idle. Saving and restoring MMCR0 over idle is a
367 END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1)
370 * Check if the requested state is a deep idle state.
372 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
373 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
375 bge .Lhandle_deep_stop
376 PPC_STOP /* Does not return (system reset interrupt) */
380 * Entering deep idle state.
381 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
382 * stack and enter stop
384 lbz r7,PACA_THREAD_MASK(r13)
385 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
389 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
390 bnel- core_idle_lock_held
391 andc r15,r15,r7 /* Clear thread bit */
397 bl save_sprs_to_stack
399 PPC_STOP /* Does not return (system reset interrupt) */
402 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
403 * r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE).
405 _GLOBAL(power7_idle_insn)
406 /* Now check if user or arch enabled NAP mode */
407 LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode)
408 b pnv_powersave_common
410 #define CHECK_HMI_INTERRUPT \
411 BEGIN_FTR_SECTION_NESTED(66); \
412 rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \
413 FTR_SECTION_ELSE_NESTED(66); \
414 rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \
415 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
416 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
418 /* Invoke opal call to handle hmi */ \
419 ld r2,PACATOC(r13); \
421 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
422 li r3,0; /* NULL argument */ \
423 bl hmi_exception_realmode; \
425 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
429 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
430 * r3 contains desired PSSCR register value.
432 _GLOBAL(power9_idle_stop)
434 lwz r5, PACA_DONT_STOP(r13)
437 std r3, PACA_REQ_PSSCR(r13)
439 lwz r5, PACA_DONT_STOP(r13)
442 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
444 LOAD_REG_ADDR(r4,power_enter_stop)
445 b pnv_powersave_common
449 * We get here when TM / thread reconfiguration bug workaround
450 * code wants to get the CPU into SMT4 mode, and therefore
451 * we are being asked not to stop.
454 std r3, PACA_REQ_PSSCR(r13)
455 blr /* return 0 for wakeup cause / SRR1 value */
458 * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
459 * HSPRG0 will be set to the HSPRG0 value of one of the
460 * threads in this core. Thus the value we have in r13
461 * may not be this thread's paca pointer.
463 * Fortunately, the TIR remains invariant. Since this thread's
464 * paca pointer is recorded in all its sibling's paca, we can
465 * correctly recover this thread's paca pointer if we
466 * know the index of this thread in the core.
468 * This index can be obtained from the TIR.
470 * i.e, thread's position in the core = TIR.
471 * If this value is i, then this thread's paca is
472 * paca->thread_sibling_pacas[i].
474 power9_dd1_recover_paca:
477 * Since each entry in thread_sibling_pacas is 8 bytes
478 * we need to left-shift by 3 bits. Thus r4 = i * 8
481 /* Get &paca->thread_sibling_pacas[0] in r5 */
482 ld r5, PACA_SIBLING_PACA_PTRS(r13)
483 /* Load paca->thread_sibling_pacas[i] into r13 */
487 * Indicate that we have lost NVGPR state
488 * which needs to be restored from the stack.
491 stb r3,PACA_NAPSTATELOST(r13)
495 * Called from machine check handler for powersave wakeups.
496 * Low level machine check processing has already been done. Now just
497 * go through the wake up path to get everything in order.
499 * r3 - The original SRR1 value.
500 * Original SRR[01] have been clobbered.
503 .global pnv_powersave_wakeup_mce
504 pnv_powersave_wakeup_mce:
505 /* Set cr3 for pnv_powersave_wakeup */
506 rlwinm r11,r3,47-31,30,31
510 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
511 * reason into r12, which allows reuse of the system reset wakeup
512 * code without being mistaken for another type of wakeup.
514 oris r12,r3,SRR1_WAKEMCE_RESVD@h
516 b pnv_powersave_wakeup
519 * Called from reset vector for powersave wakeups.
520 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
523 .global pnv_powersave_wakeup
524 pnv_powersave_wakeup:
528 BEGIN_FTR_SECTION_NESTED(70)
529 bl power9_dd1_recover_paca
530 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70)
531 bl pnv_restore_hyp_resource_arch300
533 bl pnv_restore_hyp_resource_arch207
534 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
536 li r0,PNV_THREAD_RUNNING
537 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
541 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
542 li r0,KVM_HWTHREAD_IN_KERNEL
543 stb r0,HSTATE_HWTHREAD_STATE(r13)
544 /* Order setting hwthread_state vs. testing hwthread_req */
546 lbz r0,HSTATE_HWTHREAD_REQ(r13)
553 /* Return SRR1 from power7_nap() */
554 blt cr3,pnv_wakeup_noloss
558 * Check whether we have woken up with hypervisor state loss.
559 * If yes, restore hypervisor state and return back to link.
561 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
563 pnv_restore_hyp_resource_arch300:
565 * Workaround for POWER9, if we lost resources, the ERAT
566 * might have been mixed up and needs flushing. We also need
567 * to reload MMCR0 (see comment above). We also need to set
568 * then clear bit 60 in MMCRA to ensure the PMU starts running.
576 END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1)
578 ori r4,r4,(1 << (63-60))
580 xori r4,r4,(1 << (63-60))
584 * POWER ISA 3. Use PSSCR to determine if we
585 * are waking up from deep idle state
587 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
588 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
590 BEGIN_FTR_SECTION_NESTED(71)
592 * Assume that we are waking up from the state
593 * same as the Requested Level (RL) in the PSSCR
594 * which are Bits 60-63
596 ld r5,PACA_REQ_PSSCR(r13)
598 FTR_SECTION_ELSE_NESTED(71)
600 * 0-3 bits correspond to Power-Saving Level Status
601 * which indicates the idle state we are waking up from
605 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 71)
606 li r0, 0 /* clear requested_psscr to say we're awake */
607 std r0, PACA_REQ_PSSCR(r13)
609 bge cr4,pnv_wakeup_tb_loss /* returns to caller */
611 blr /* Waking up without hypervisor state loss. */
613 /* Same calling convention as arch300 */
614 pnv_restore_hyp_resource_arch207:
616 * POWER ISA 2.07 or less.
617 * Check if we slept with sleep or winkle.
619 lbz r4,PACA_THREAD_IDLE_STATE(r13)
620 cmpwi cr2,r4,PNV_THREAD_NAP
621 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
624 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
625 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
626 * indicates we are waking with hypervisor state loss from nap.
630 blr /* Waking up without hypervisor state loss */
633 * Called if waking up from idle state which can cause either partial or
634 * complete hyp state loss.
635 * In POWER8, called if waking up from fastsleep or winkle
636 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
639 * cr3 - gt if waking up with partial/complete hypervisor state loss
642 * cr4 - gt or eq if waking up from complete hypervisor state loss.
645 * r4 - PACA_THREAD_IDLE_STATE
650 * Before entering any idle state, the NVGPRs are saved in the stack.
651 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
652 * NVGPRs are restored. If we are here, it is likely that state is lost,
653 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
654 * here are the same as the test to restore NVGPRS:
655 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
656 * and SRR1 test for restoring NVGPRs.
658 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
659 * guarantee they will always be restored. This might be tightened
660 * with careful reading of specs (particularly for ISA300) but this
661 * is already a slow wakeup path and it's simpler to be safe.
664 stb r0,PACA_NAPSTATELOST(r13)
668 * Save SRR1 and LR in NVGPRs as they might be clobbered in
669 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
670 * to determine the wakeup reason if we branch to kvm_start_guest. LR
671 * is required to return back to reset vector after hypervisor state
672 * restore is complete.
679 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
681 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
682 lbz r7,PACA_THREAD_MASK(r13)
685 * Take the core lock to synchronize against other threads.
687 * Lock bit is set in one of the 2 cases-
688 * a. In the sleep/winkle enter path, the last thread is executing
689 * fastsleep workaround code.
690 * b. In the wake up path, another thread is executing fastsleep
691 * workaround undo code or resyncing timebase or restoring context
692 * In either case loop until the lock bit is cleared.
696 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
697 bnel- core_idle_lock_held
698 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
703 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
708 * cr2 - eq if first thread to wakeup in core
709 * cr3- gt if waking up with partial/complete hypervisor state loss
711 * cr4 - gt or eq if waking up from complete hypervisor state loss.
717 * If yes, check if all threads were in winkle, decrement our
718 * winkle count, set all thread winkle bits if all were in winkle.
719 * Check if our thread has a winkle bit set, and set cr4 accordingly
720 * (to match ISA300, above). Pseudo-code for core idle state
721 * transitions for ISA207 is as follows (everything happens atomically
722 * due to store conditional and/or lock bit):
729 * core_idle_state &= ~thread_in_core
734 * bool first_in_core, first_in_subcore;
736 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
737 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
739 * core_idle_state |= thread_in_core;
744 * core_idle_state &= ~thread_in_core;
745 * core_idle_state += 1 << WINKLE_COUNT_SHIFT;
750 * bool first_in_core, first_in_subcore, winkle_state_lost;
752 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
753 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
755 * core_idle_state |= thread_in_core;
757 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
758 * core_idle_state |= THREAD_WINKLE_BITS;
759 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
761 * winkle_state_lost = core_idle_state &
762 * (thread_in_core << WINKLE_THREAD_SHIFT);
763 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
767 cmpwi r18,PNV_THREAD_WINKLE
769 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
770 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
772 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
774 /* Shift thread bit to winkle mask, then test if this thread is set,
775 * and remove it from the winkle bits */
779 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */
781 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
783 cmpwi r4,0 /* Check if first in subcore */
785 or r15,r15,r7 /* Set thread bit */
786 beq first_thread_in_subcore
787 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
789 or r15,r15,r7 /* Set thread bit */
790 beq cr2,first_thread_in_core
792 /* Not first thread in core or subcore to wake up */
795 first_thread_in_subcore:
797 * If waking up from sleep, subcore state is not lost. Hence
798 * skip subcore state restore
800 blt cr4,subcore_state_restored
802 /* Restore per-subcore state */
811 subcore_state_restored:
813 * Check if the thread is also the first thread in the core. If not,
814 * skip to clear_lock.
818 first_thread_in_core:
821 * First thread in the core waking up from any state which can cause
822 * partial or complete hypervisor state loss. It needs to
823 * call the fastsleep workaround code if the platform requires it.
824 * Call it unconditionally here. The below branch instruction will
825 * be patched out if the platform does not have fastsleep or does not
826 * require the workaround. Patching will be performed during the
827 * discovery of idle-states.
829 .global pnv_fastsleep_workaround_at_exit
830 pnv_fastsleep_workaround_at_exit:
831 b fastsleep_workaround_at_exit
835 * Use cr3 which indicates that we are waking up with atleast partial
836 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
838 ble cr3,.Ltb_resynced
839 /* Time base re-sync */
840 bl opal_resync_timebase;
842 * If waking up from sleep (POWER8), per core state
843 * is not lost, skip to clear_lock.
849 * First thread in the core to wake up and its waking up with
850 * complete hypervisor state loss. Restore per core hypervisor
858 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
866 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
872 * Common to all threads.
874 * If waking up from sleep, hypervisor state is not lost. Hence
875 * skip hypervisor state restore.
877 blt cr4,hypervisor_state_restored
879 /* Waking up from winkle */
881 BEGIN_MMU_FTR_SECTION
883 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
884 /* Restore SLB from PACA */
885 ld r8,PACA_SLBSHADOWPTR(r13)
888 li r3, SLBSHADOW_SAVEAREA
892 andis. r7,r5,SLB_ESID_V@h
899 /* Restore per thread state */
910 /* Call cur_cpu_spec->cpu_restore() */
911 LOAD_REG_ADDR(r4, cur_cpu_spec)
913 ld r12,CPU_SPEC_RESTORE(r4)
914 #ifdef PPC64_ELF_ABI_v1
921 * On POWER9, we can come here on wakeup from a cpuidle stop state.
922 * Hence restore the additional SPRs to the saved value.
924 * On POWER8, we come here only on winkle. Since winkle is used
925 * only in the case of CPU-Hotplug, we don't need to restore
926 * the additional SPRs.
929 bl power9_restore_additional_sprs
930 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
931 hypervisor_state_restored:
935 blr /* return to pnv_powersave_wakeup */
937 fastsleep_workaround_at_exit:
940 bl opal_config_cpu_idle_state
944 * R3 here contains the value that will be returned to the caller
946 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
948 .global pnv_wakeup_loss
953 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
959 addi r1,r1,INT_FRAME_SIZE
966 * R3 here contains the value that will be returned to the caller
968 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
971 lbz r0,PACA_NAPSTATELOST(r13)
977 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
981 addi r1,r1,INT_FRAME_SIZE