2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/book3s/64/mmu-hash.h>
29 * Use unused space in the interrupt stack to save and restore
30 * registers for winkle support.
43 #define PSSCR_HV_TEMPLATE PSSCR_ESL | PSSCR_EC | \
44 PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
50 * Used by threads before entering deep idle states. Saves SPRs
51 * in interrupt stack frame
55 * Note all register i.e per-core, per-subcore or per-thread is saved
56 * here since any thread in the core might wake up first
62 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
68 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
89 * Used by threads when the lock bit of core_idle_state is set.
90 * Threads will spin in HMT_LOW until the lock bit is cleared.
91 * r14 - pointer to core_idle_state
92 * r15 - used to load contents of core_idle_state
93 * r9 - used as a temporary variable
99 andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT
103 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
104 bne core_idle_lock_held
108 * Pass requested state in r3:
109 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
110 * - Requested STOP state in POWER9
112 * To check IRQ_HAPPENED in r4
116 * Address to 'rfid' to in r5
118 _GLOBAL(pnv_powersave_common)
119 /* Use r3 to pass state nap/sleep/winkle */
120 /* NAP is a state loss, we create a regs frame on the
121 * stack, fill it up with the state we care about and
122 * stick a pointer to it in PACAR1. We really only
123 * need to save PC, some CR bits and the NV GPRs,
124 * but for now an interrupt frame will do.
128 stdu r1,-INT_FRAME_SIZE(r1)
132 /* Hard disable interrupts */
136 mtmsrd r9,1 /* hard-disable interrupts */
138 /* Check if something happened while soft-disabled */
139 lbz r0,PACAIRQHAPPENED(r13)
140 andi. r0,r0,~PACA_IRQ_HARD_DIS@l
144 addi r1,r1,INT_FRAME_SIZE
146 li r3,0 /* Return 0 (no nap) */
150 1: /* We mark irqs hard disabled as this is the state we'll
151 * be in when returning and we need to tell arch_local_irq_restore()
154 li r0,PACA_IRQ_HARD_DIS
155 stb r0,PACAIRQHAPPENED(r13)
157 /* We haven't lost state ... yet */
159 stb r0,PACA_NAPSTATELOST(r13)
161 /* Continue saving state */
170 * Go to real mode to do the nap, as required by the architecture.
171 * Also, we need to be in real mode before setting hwthread_state,
172 * because as soon as we do that, another thread can switch
173 * the MMU context to the guest.
175 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
178 mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
183 .globl pnv_enter_arch207_idle_mode
184 pnv_enter_arch207_idle_mode:
185 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
186 /* Tell KVM we're entering idle */
187 li r4,KVM_HWTHREAD_IN_IDLE
188 /******************************************************/
189 /* N O T E W E L L ! ! ! N O T E W E L L */
190 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
191 /* MUST occur in real mode, i.e. with the MMU off, */
192 /* and the MMU must stay off until we clear this flag */
193 /* and test HSTATE_HWTHREAD_REQ(r13) in the system */
194 /* reset interrupt vector in exceptions-64s.S. */
195 /* The reason is that another thread can switch the */
196 /* MMU to a guest context whenever this flag is set */
197 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
198 /* that would potentially cause this thread to start */
199 /* executing instructions from guest memory in */
200 /* hypervisor mode, leading to a host crash or data */
201 /* corruption, or worse. */
202 /******************************************************/
203 stb r4,HSTATE_HWTHREAD_STATE(r13)
205 stb r3,PACA_THREAD_IDLE_STATE(r13)
206 cmpwi cr3,r3,PNV_THREAD_SLEEP
208 IDLE_STATE_ENTER_SEQ(PPC_NAP)
211 /* Sleep or winkle */
212 lbz r7,PACA_THREAD_MASK(r13)
213 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
217 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
218 bnel core_idle_lock_held
220 andc r15,r15,r7 /* Clear thread bit */
222 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
225 * If cr0 = 0, then current thread is the last thread of the core entering
226 * sleep. Last thread needs to execute the hardware bug workaround code if
227 * required by the platform.
228 * Make the workaround call unconditionally here. The below branch call is
229 * patched out when the idle states are discovered if the platform does not
232 .global pnv_fastsleep_workaround_at_entry
233 pnv_fastsleep_workaround_at_entry:
234 beq fastsleep_workaround_at_entry
240 common_enter: /* common code for all the threads entering sleep or winkle */
242 IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
244 fastsleep_workaround_at_entry:
245 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
250 /* Fast sleep workaround */
253 bl opal_rm_config_cpu_idle_state
262 bl save_sprs_to_stack
264 IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
267 * r3 - requested stop state
270 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
271 /* Tell KVM we're entering idle */
272 li r4,KVM_HWTHREAD_IN_IDLE
273 /* DO THIS IN REAL MODE! See comment above. */
274 stb r4,HSTATE_HWTHREAD_STATE(r13)
277 * Check if the requested state is a deep idle state.
279 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
280 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
283 IDLE_STATE_ENTER_SEQ(PPC_STOP)
286 * Entering deep idle state.
287 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
288 * stack and enter stop
290 lbz r7,PACA_THREAD_MASK(r13)
291 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
295 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
296 bnel core_idle_lock_held
297 andc r15,r15,r7 /* Clear thread bit */
303 bl save_sprs_to_stack
305 IDLE_STATE_ENTER_SEQ(PPC_STOP)
308 /* Now check if user or arch enabled NAP mode */
309 LOAD_REG_ADDRBASE(r3,powersave_nap)
310 lwz r4,ADDROFF(powersave_nap)(r3)
319 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
320 b pnv_powersave_common
323 _GLOBAL(power7_sleep)
324 li r3,PNV_THREAD_SLEEP
326 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
327 b pnv_powersave_common
330 _GLOBAL(power7_winkle)
331 li r3,PNV_THREAD_WINKLE
333 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
334 b pnv_powersave_common
337 #define CHECK_HMI_INTERRUPT \
338 mfspr r0,SPRN_SRR1; \
339 BEGIN_FTR_SECTION_NESTED(66); \
340 rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
341 FTR_SECTION_ELSE_NESTED(66); \
342 rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
343 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
344 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
346 /* Invoke opal call to handle hmi */ \
347 ld r2,PACATOC(r13); \
349 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
350 li r3,0; /* NULL argument */ \
351 bl hmi_exception_realmode; \
353 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
358 * r3 - requested stop state
360 _GLOBAL(power9_idle_stop)
361 LOAD_REG_IMMEDIATE(r4, PSSCR_HV_TEMPLATE)
365 LOAD_REG_ADDR(r5,power_enter_stop)
366 b pnv_powersave_common
369 * Called from reset vector. Check whether we have woken up with
370 * hypervisor state loss. If yes, restore hypervisor state and return
371 * back to reset vector.
373 * r13 - Contents of HSPRG0
374 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
376 _GLOBAL(pnv_restore_hyp_resource)
380 * POWER ISA 3. Use PSSCR to determine if we
381 * are waking up from deep idle state
383 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
384 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
388 * 0-3 bits correspond to Power-Saving Level Status
389 * which indicates the idle state we are waking up from
393 bge cr4,pnv_wakeup_tb_loss
395 * Waking up without hypervisor state loss. Return to
400 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
403 * POWER ISA 2.07 or less.
404 * Check if last bit of HSPGR0 is set. This indicates whether we are
405 * waking up from winkle.
410 /* Now that we are sure r13 is corrected, load TOC */
413 mtspr SPRN_HSPRG0,r13
415 lbz r0,PACA_THREAD_IDLE_STATE(r13)
416 cmpwi cr2,r0,PNV_THREAD_NAP
417 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
420 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
421 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
422 * indicates we are waking with hypervisor state loss from nap.
426 blr /* Return back to System Reset vector from where
427 pnv_restore_hyp_resource was invoked */
430 * Called if waking up from idle state which can cause either partial or
431 * complete hyp state loss.
432 * In POWER8, called if waking up from fastsleep or winkle
433 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
436 * cr3 - gt if waking up with partial/complete hypervisor state loss
437 * cr4 - gt or eq if waking up from complete hypervisor state loss.
439 _GLOBAL(pnv_wakeup_tb_loss)
442 * Before entering any idle state, the NVGPRs are saved in the stack
443 * and they are restored before switching to the process context. Hence
444 * until they are restored, they are free to be used.
446 * Save SRR1 and LR in NVGPRs as they might be clobbered in
447 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
448 * to determine the wakeup reason if we branch to kvm_start_guest. LR
449 * is required to return back to reset vector after hypervisor state
450 * restore is complete.
456 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
458 lbz r7,PACA_THREAD_MASK(r13)
459 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
462 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
464 * Lock bit is set in one of the 2 cases-
465 * a. In the sleep/winkle enter path, the last thread is executing
466 * fastsleep workaround code.
467 * b. In the wake up path, another thread is executing fastsleep
468 * workaround undo code or resyncing timebase or restoring context
469 * In either case loop until the lock bit is cleared.
471 bnel core_idle_lock_held
477 * cr2 - eq if first thread to wakeup in core
478 * cr3- gt if waking up with partial/complete hypervisor state loss
479 * cr4 - gt or eq if waking up from complete hypervisor state loss.
482 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
488 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
490 cmpwi r4,0 /* Check if first in subcore */
492 or r15,r15,r7 /* Set thread bit */
493 beq first_thread_in_subcore
494 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
496 or r15,r15,r7 /* Set thread bit */
497 beq cr2,first_thread_in_core
499 /* Not first thread in core or subcore to wake up */
502 first_thread_in_subcore:
504 * If waking up from sleep, subcore state is not lost. Hence
505 * skip subcore state restore
507 blt cr4,subcore_state_restored
509 /* Restore per-subcore state */
518 subcore_state_restored:
520 * Check if the thread is also the first thread in the core. If not,
521 * skip to clear_lock.
525 first_thread_in_core:
528 * First thread in the core waking up from any state which can cause
529 * partial or complete hypervisor state loss. It needs to
530 * call the fastsleep workaround code if the platform requires it.
531 * Call it unconditionally here. The below branch instruction will
532 * be patched out if the platform does not have fastsleep or does not
533 * require the workaround. Patching will be performed during the
534 * discovery of idle-states.
536 .global pnv_fastsleep_workaround_at_exit
537 pnv_fastsleep_workaround_at_exit:
538 b fastsleep_workaround_at_exit
542 * Use cr3 which indicates that we are waking up with atleast partial
543 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
546 /* Time base re-sync */
547 bl opal_rm_resync_timebase;
549 * If waking up from sleep, per core state is not lost, skip to
555 * First thread in the core to wake up and its waking up with
556 * complete hypervisor state loss. Restore per core hypervisor
564 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
572 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
578 * Common to all threads.
580 * If waking up from sleep, hypervisor state is not lost. Hence
581 * skip hypervisor state restore.
583 blt cr4,hypervisor_state_restored
585 /* Waking up from winkle */
587 BEGIN_MMU_FTR_SECTION
589 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
590 /* Restore SLB from PACA */
591 ld r8,PACA_SLBSHADOWPTR(r13)
594 li r3, SLBSHADOW_SAVEAREA
598 andis. r7,r5,SLB_ESID_V@h
605 /* Restore per thread state */
616 /* Call cur_cpu_spec->cpu_restore() */
617 LOAD_REG_ADDR(r4, cur_cpu_spec)
619 ld r12,CPU_SPEC_RESTORE(r4)
620 #ifdef PPC64_ELF_ABI_v1
626 hypervisor_state_restored:
630 blr /* Return back to System Reset vector from where
631 pnv_restore_hyp_resource was invoked */
633 fastsleep_workaround_at_exit:
636 bl opal_rm_config_cpu_idle_state
640 * R3 here contains the value that will be returned to the caller
643 _GLOBAL(pnv_wakeup_loss)
647 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
653 addi r1,r1,INT_FRAME_SIZE
660 * R3 here contains the value that will be returned to the caller
663 _GLOBAL(pnv_wakeup_noloss)
664 lbz r0,PACA_NAPSTATELOST(r13)
669 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
674 addi r1,r1,INT_FRAME_SIZE