2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
19 #include <linux/sys.h>
20 #include <asm/unistd.h>
21 #include <asm/errno.h>
24 #include <asm/cache.h>
25 #include <asm/cputable.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/processor.h>
31 #include <asm/kexec.h>
35 #ifdef CONFIG_IRQSTACKS
36 _GLOBAL(call_do_softirq)
39 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
47 _GLOBAL(call_handle_irq)
51 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
58 #endif /* CONFIG_IRQSTACKS */
61 * This returns the high 64 bits of the product of two 64-bit numbers.
73 1: beqlr cr1 /* all done if high part of A is 0 */
88 * sub_reloc_offset(x) returns x - reloc_offset().
90 _GLOBAL(sub_reloc_offset)
102 * reloc_got2 runs through the .got2 section adding an offset
107 lis r7,__got2_start@ha
108 addi r7,r7,__got2_start@l
110 addi r8,r8,__got2_end@l
130 * call_setup_cpu - call the setup_cpu function for this cpu
131 * r3 = data offset, r24 = cpu number
133 * Setup function is called with:
135 * r4 = ptr to CPU spec (relocated)
137 _GLOBAL(call_setup_cpu)
138 addis r4,r3,cur_cpu_spec@ha
139 addi r4,r4,cur_cpu_spec@l
142 lwz r5,CPU_SPEC_SETUP(r4)
149 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
151 /* This gets called by via-pmu.c to switch the PLL selection
152 * on 750fx CPU. This function should really be moved to some
153 * other place (as most of the cpufreq code in via-pmu
155 _GLOBAL(low_choose_750fx_pll)
161 /* If switching to PLL1, disable HID0:BTIC */
172 /* Calc new HID1 value */
173 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
174 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
175 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
179 /* Store new HID1 image */
180 rlwinm r6,r1,0,0,(31-THREAD_SHIFT)
183 addis r6,r6,nap_save_hid1@ha
184 stw r4,nap_save_hid1@l(r6)
186 /* If switching to PLL0, enable HID0:BTIC */
201 _GLOBAL(low_choose_7447a_dfs)
207 /* Calc new HID1 value */
209 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
219 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
222 * complement mask on the msr then "or" some values on.
223 * _nmask_and_or_msr(nmask, value_to_or)
225 _GLOBAL(_nmask_and_or_msr)
226 mfmsr r0 /* Get current msr */
227 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
228 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
229 SYNC /* Some chip revs have problems here... */
230 mtmsr r0 /* Update machine state */
237 * Do an IO access in real mode
255 * Do an IO access in real mode
272 #endif /* CONFIG_40x */
277 #ifndef CONFIG_FSL_BOOKE
282 #if defined(CONFIG_40x)
283 sync /* Flush to memory before changing mapping */
285 isync /* Flush shadow TLB */
286 #elif defined(CONFIG_44x)
290 /* Load high watermark */
291 lis r4,tlb_44x_hwater@ha
292 lwz r5,tlb_44x_hwater@l(r4)
294 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
300 #elif defined(CONFIG_FSL_BOOKE)
301 /* Invalidate all entries in TLB0 */
304 /* Invalidate all entries in TLB1 */
310 #endif /* CONFIG_SMP */
311 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
312 #if defined(CONFIG_SMP)
313 rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
318 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
319 rlwinm r0,r0,0,28,26 /* clear DR */
323 lis r9,mmu_hash_lock@h
324 ori r9,r9,mmu_hash_lock@l
336 stw r0,0(r9) /* clear mmu_hash_lock */
340 #else /* CONFIG_SMP */
344 #endif /* CONFIG_SMP */
345 #endif /* ! defined(CONFIG_40x) */
349 * Flush MMU TLB for a particular address
351 #ifndef CONFIG_FSL_BOOKE
355 #if defined(CONFIG_40x)
356 /* We run the search with interrupts disabled because we have to change
357 * the PID and I don't want to preempt when that happens.
368 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
369 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
371 tlbwe r3, r3, TLB_TAG
375 #elif defined(CONFIG_44x)
377 rlwimi r5,r4,0,24,31 /* Set TID */
379 /* We have to run the search with interrupts disabled, even critical
380 * and debug interrupts (in fact the only critical exceptions we have
381 * are debug and machine check). Otherwise an interrupt which causes
382 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
384 lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
385 addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
393 /* There are only 64 TLB entries, so r3 < 64,
394 * which means bit 22, is clear. Since 22 is
395 * the V bit in the TLB_PAGEID, loading this
396 * value will invalidate the TLB entry.
398 tlbwe r3, r3, PPC44x_TLB_PAGEID
401 #elif defined(CONFIG_FSL_BOOKE)
402 rlwinm r4, r3, 0, 0, 19
403 ori r5, r4, 0x08 /* TLBSEL = 1 */
407 #if defined(CONFIG_SMP)
409 #endif /* CONFIG_SMP */
410 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
411 #if defined(CONFIG_SMP)
412 rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
417 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
418 rlwinm r0,r0,0,28,26 /* clear DR */
422 lis r9,mmu_hash_lock@h
423 ori r9,r9,mmu_hash_lock@l
435 stw r0,0(r9) /* clear mmu_hash_lock */
439 #else /* CONFIG_SMP */
442 #endif /* CONFIG_SMP */
443 #endif /* ! CONFIG_40x */
446 #if defined(CONFIG_FSL_BOOKE)
448 * Flush MMU TLB, but only on the local processor (no broadcast)
451 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
452 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
453 li r3,(MMUCSR0_TLBFI)@l
454 mtspr SPRN_MMUCSR0, r3
456 mfspr r3,SPRN_MMUCSR0
457 andi. r3,r3,MMUCSR0_TLBFI@l
462 * Flush MMU TLB for a particular process id, but only on the local processor
466 /* we currently do an invalidate all since we don't have per pid invalidate */
467 li r3,(MMUCSR0_TLBFI)@l
468 mtspr SPRN_MMUCSR0, r3
470 mfspr r3,SPRN_MMUCSR0
471 andi. r3,r3,MMUCSR0_TLBFI@l
478 * Flush MMU TLB for a particular address, but only on the local processor
483 mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
485 mfspr r4,SPRN_MAS1 /* check valid */
486 andis. r3,r4,MAS1_VALID@h
494 #endif /* CONFIG_FSL_BOOKE */
498 * Flush instruction cache.
499 * This is a no-op on the 601.
501 _GLOBAL(flush_instruction_cache)
502 #if defined(CONFIG_8xx)
505 mtspr SPRN_IC_CST, r5
506 #elif defined(CONFIG_4xx)
518 #elif CONFIG_FSL_BOOKE
521 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
522 /* msync; isync recommended here */
526 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
528 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
532 rlwinm r3,r3,16,16,31
534 beqlr /* for 601, do nothing */
535 /* 603/604 processor - use invalidate-all bit in HID0 */
539 #endif /* CONFIG_8xx/4xx */
544 * Write any modified data cache blocks out to memory
545 * and invalidate the corresponding instruction cache blocks.
546 * This is a no-op on the 601.
548 * flush_icache_range(unsigned long start, unsigned long stop)
550 _KPROBE(__flush_icache_range)
552 blr /* for 601, do nothing */
553 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
554 li r5,L1_CACHE_BYTES-1
558 srwi. r4,r4,L1_CACHE_SHIFT
563 addi r3,r3,L1_CACHE_BYTES
565 sync /* wait for dcbst's to get to ram */
568 addi r6,r6,L1_CACHE_BYTES
570 sync /* additional sync needed on g4 */
574 * Write any modified data cache blocks out to memory.
575 * Does not invalidate the corresponding cache lines (especially for
576 * any corresponding instruction cache).
578 * clean_dcache_range(unsigned long start, unsigned long stop)
580 _GLOBAL(clean_dcache_range)
581 li r5,L1_CACHE_BYTES-1
585 srwi. r4,r4,L1_CACHE_SHIFT
590 addi r3,r3,L1_CACHE_BYTES
592 sync /* wait for dcbst's to get to ram */
596 * Write any modified data cache blocks out to memory and invalidate them.
597 * Does not invalidate the corresponding instruction cache blocks.
599 * flush_dcache_range(unsigned long start, unsigned long stop)
601 _GLOBAL(flush_dcache_range)
602 li r5,L1_CACHE_BYTES-1
606 srwi. r4,r4,L1_CACHE_SHIFT
611 addi r3,r3,L1_CACHE_BYTES
613 sync /* wait for dcbst's to get to ram */
617 * Like above, but invalidate the D-cache. This is used by the 8xx
618 * to invalidate the cache so the PPC core doesn't get stale data
619 * from the CPM (no cache snooping here :-).
621 * invalidate_dcache_range(unsigned long start, unsigned long stop)
623 _GLOBAL(invalidate_dcache_range)
624 li r5,L1_CACHE_BYTES-1
628 srwi. r4,r4,L1_CACHE_SHIFT
633 addi r3,r3,L1_CACHE_BYTES
635 sync /* wait for dcbi's to get to ram */
639 * Flush a particular page from the data cache to RAM.
640 * Note: this is necessary because the instruction cache does *not*
641 * snoop from the data cache.
642 * This is a no-op on the 601 which has a unified cache.
644 * void __flush_dcache_icache(void *page)
646 _GLOBAL(__flush_dcache_icache)
649 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
650 rlwinm r3,r3,0,0,19 /* Get page base address */
651 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
654 0: dcbst 0,r3 /* Write line to ram */
655 addi r3,r3,L1_CACHE_BYTES
659 /* We don't flush the icache on 44x. Those have a virtual icache
660 * and we don't have access to the virtual address here (it's
661 * not the page vaddr but where it's mapped in user space). The
662 * flushing of the icache on these is handled elsewhere, when
663 * a change in the address space occurs, before returning to
668 addi r6,r6,L1_CACHE_BYTES
672 #endif /* CONFIG_44x */
676 * Flush a particular page from the data cache to RAM, identified
677 * by its physical address. We turn off the MMU so we can just use
678 * the physical address (this may be a highmem page without a kernel
681 * void __flush_dcache_icache_phys(unsigned long physaddr)
683 _GLOBAL(__flush_dcache_icache_phys)
685 blr /* for 601, do nothing */
686 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
688 rlwinm r0,r10,0,28,26 /* clear DR */
691 rlwinm r3,r3,0,0,19 /* Get page base address */
692 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
695 0: dcbst 0,r3 /* Write line to ram */
696 addi r3,r3,L1_CACHE_BYTES
701 addi r6,r6,L1_CACHE_BYTES
704 mtmsr r10 /* restore DR */
709 * Clear pages using the dcbz instruction, which doesn't cause any
710 * memory traffic (except to write out any cache lines which get
711 * displaced). This only works on cacheable memory.
713 * void clear_pages(void *page, int order) ;
716 li r0,4096/L1_CACHE_BYTES
728 addi r3,r3,L1_CACHE_BYTES
733 * Copy a whole page. We use the dcbz instruction on the destination
734 * to reduce memory traffic (it eliminates the unnecessary reads of
735 * the destination into cache). This requires that the destination
738 #define COPY_16_BYTES \
753 /* don't use prefetch on 8xx */
754 li r0,4096/L1_CACHE_BYTES
760 #else /* not 8xx, we can prefetch */
763 #if MAX_COPY_PREFETCH > 1
764 li r0,MAX_COPY_PREFETCH
768 addi r11,r11,L1_CACHE_BYTES
770 #else /* MAX_COPY_PREFETCH == 1 */
772 li r11,L1_CACHE_BYTES+4
773 #endif /* MAX_COPY_PREFETCH */
774 li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
782 #if L1_CACHE_BYTES >= 32
784 #if L1_CACHE_BYTES >= 64
787 #if L1_CACHE_BYTES >= 128
797 crnot 4*cr0+eq,4*cr0+eq
798 li r0,MAX_COPY_PREFETCH
801 #endif /* CONFIG_8xx */
804 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
805 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
807 _GLOBAL(atomic_clear_mask)
814 _GLOBAL(atomic_set_mask)
823 * Extended precision shifts.
825 * Updated to be valid for shift counts from 0 to 63 inclusive.
828 * R3/R4 has 64 bit value
832 * ashrdi3: arithmetic right shift (sign propagation)
833 * lshrdi3: logical right shift
834 * ashldi3: left shift
838 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
839 addi r7,r5,32 # could be xori, or addi with -32
840 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
841 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
842 sraw r7,r3,r7 # t2 = MSW >> (count-32)
843 or r4,r4,r6 # LSW |= t1
844 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
845 sraw r3,r3,r5 # MSW = MSW >> count
846 or r4,r4,r7 # LSW |= t2
851 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
852 addi r7,r5,32 # could be xori, or addi with -32
853 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
854 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
855 or r3,r3,r6 # MSW |= t1
856 slw r4,r4,r5 # LSW = LSW << count
857 or r3,r3,r7 # MSW |= t2
862 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
863 addi r7,r5,32 # could be xori, or addi with -32
864 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
865 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
866 or r4,r4,r6 # LSW |= t1
867 srw r3,r3,r5 # MSW = MSW >> count
868 or r4,r4,r7 # LSW |= t2
872 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
873 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
893 * Create a kernel thread
894 * kernel_thread(fn, arg, flags)
896 _GLOBAL(kernel_thread)
900 mr r30,r3 /* function */
901 mr r31,r4 /* argument */
902 ori r3,r5,CLONE_VM /* flags */
903 oris r3,r3,CLONE_UNTRACED>>16
904 li r4,0 /* new sp (unused) */
907 bns+ 1f /* did system call indicate error? */
908 neg r3,r3 /* if so, make return code negative */
909 1: cmpwi 0,r3,0 /* parent or child? */
910 bne 2f /* return if parent */
911 li r0,0 /* make top-level stack frame */
913 mtlr r30 /* fn addr in lr */
914 mr r3,r31 /* load arg and call fn */
917 li r0,__NR_exit /* exit if function returns */
926 * This routine is just here to keep GCC happy - sigh...
933 * Must be relocatable PIC code callable as a C function.
935 .globl relocate_new_kernel
938 /* r4 = reboot_code_buffer */
939 /* r5 = start_address */
944 * Set Machine Status Register to a known status,
945 * switch the MMU off and jump to 1: in a single step.
949 ori r8, r8, MSR_RI|MSR_ME
951 addi r8, r4, 1f - relocate_new_kernel
957 /* from this point address translation is turned off */
958 /* and interrupts are disabled */
960 /* set a new stack at the bottom of our page... */
961 /* (not really needed now) */
962 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
966 li r6, 0 /* checksum */
970 0: /* top, read another word for the indirection page */
974 /* is it a destination page? (r8) */
975 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
978 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
981 2: /* is it an indirection page? (r3) */
982 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
985 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
989 2: /* are we done? */
990 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
994 2: /* is it a source page? (r9) */
995 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
998 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1000 li r7, PAGE_SIZE / 4
1005 lwzu r0, 4(r9) /* do the copy */
1019 /* To be certain of avoiding problems with self-modifying code
1020 * execute a serializing instruction here.
1025 /* jump to the entry point, usually the setup routine */
1031 relocate_new_kernel_end:
1033 .globl relocate_new_kernel_size
1034 relocate_new_kernel_size:
1035 .long relocate_new_kernel_end - relocate_new_kernel
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