2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
34 #include <asm/processor.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/byteorder.h>
39 #include <asm/machdep.h>
40 #include <asm/ppc-pci.h>
43 static DEFINE_SPINLOCK(hose_spinlock
);
46 /* XXX kill that some day ... */
47 static int global_phb_number
; /* Global phb counter */
49 /* ISA Memory physical address */
50 resource_size_t isa_mem_base
;
53 static struct dma_map_ops
*pci_dma_ops
= &dma_direct_ops
;
55 void set_pci_dma_ops(struct dma_map_ops
*dma_ops
)
57 pci_dma_ops
= dma_ops
;
60 struct dma_map_ops
*get_pci_dma_ops(void)
64 EXPORT_SYMBOL(get_pci_dma_ops
);
66 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
68 struct pci_controller
*phb
;
70 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
73 spin_lock(&hose_spinlock
);
74 phb
->global_number
= global_phb_number
++;
75 list_add_tail(&phb
->list_node
, &hose_list
);
76 spin_unlock(&hose_spinlock
);
78 phb
->is_dynamic
= mem_init_done
;
81 int nid
= of_node_to_nid(dev
);
83 if (nid
< 0 || !node_online(nid
))
86 PHB_SET_NODE(phb
, nid
);
92 void pcibios_free_controller(struct pci_controller
*phb
)
94 spin_lock(&hose_spinlock
);
95 list_del(&phb
->list_node
);
96 spin_unlock(&hose_spinlock
);
102 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
105 return hose
->pci_io_size
;
107 return resource_size(&hose
->io_resource
);
111 int pcibios_vaddr_is_ioport(void __iomem
*address
)
114 struct pci_controller
*hose
;
115 resource_size_t size
;
117 spin_lock(&hose_spinlock
);
118 list_for_each_entry(hose
, &hose_list
, list_node
) {
119 size
= pcibios_io_size(hose
);
120 if (address
>= hose
->io_base_virt
&&
121 address
< (hose
->io_base_virt
+ size
)) {
126 spin_unlock(&hose_spinlock
);
130 unsigned long pci_address_to_pio(phys_addr_t address
)
132 struct pci_controller
*hose
;
133 resource_size_t size
;
134 unsigned long ret
= ~0;
136 spin_lock(&hose_spinlock
);
137 list_for_each_entry(hose
, &hose_list
, list_node
) {
138 size
= pcibios_io_size(hose
);
139 if (address
>= hose
->io_base_phys
&&
140 address
< (hose
->io_base_phys
+ size
)) {
142 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
143 ret
= base
+ (address
- hose
->io_base_phys
);
147 spin_unlock(&hose_spinlock
);
151 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
154 * Return the domain number for this bus.
156 int pci_domain_nr(struct pci_bus
*bus
)
158 struct pci_controller
*hose
= pci_bus_to_host(bus
);
160 return hose
->global_number
;
162 EXPORT_SYMBOL(pci_domain_nr
);
164 /* This routine is meant to be used early during boot, when the
165 * PCI bus numbers have not yet been assigned, and you need to
166 * issue PCI config cycles to an OF device.
167 * It could also be used to "fix" RTAS config cycles if you want
168 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
171 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
174 struct pci_controller
*hose
, *tmp
;
175 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
176 if (hose
->dn
== node
)
183 static ssize_t
pci_show_devspec(struct device
*dev
,
184 struct device_attribute
*attr
, char *buf
)
186 struct pci_dev
*pdev
;
187 struct device_node
*np
;
189 pdev
= to_pci_dev (dev
);
190 np
= pci_device_to_OF_node(pdev
);
191 if (np
== NULL
|| np
->full_name
== NULL
)
193 return sprintf(buf
, "%s", np
->full_name
);
195 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
197 /* Add sysfs properties */
198 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
200 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
203 char __devinit
*pcibios_setup(char *str
)
209 * Reads the interrupt pin to determine if interrupt is use by card.
210 * If the interrupt is used, then gets the interrupt line from the
211 * openfirmware and sets it in the pci_dev and pci_config line.
213 static int pci_read_irq_line(struct pci_dev
*pci_dev
)
218 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
221 memset(&oirq
, 0xff, sizeof(oirq
));
223 /* Try to get a mapping from the device-tree */
224 if (of_irq_map_pci(pci_dev
, &oirq
)) {
227 /* If that fails, lets fallback to what is in the config
228 * space and map that through the default controller. We
229 * also set the type to level low since that's what PCI
230 * interrupts are. If your platform does differently, then
231 * either provide a proper interrupt tree or don't use this
234 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
238 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
239 line
== 0xff || line
== 0) {
242 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
245 virq
= irq_create_mapping(NULL
, line
);
247 irq_set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
249 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
250 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
251 oirq
.controller
? oirq
.controller
->full_name
:
254 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
258 pr_debug(" Failed to map !\n");
262 pr_debug(" Mapped to linux irq %d\n", virq
);
270 * Platform support for /proc/bus/pci/X/Y mmap()s,
271 * modelled on the sparc64 implementation by Dave Miller.
276 * Adjust vm_pgoff of VMA such that it is the physical page offset
277 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
279 * Basically, the user finds the base address for his device which he wishes
280 * to mmap. They read the 32-bit value from the config space base register,
281 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
282 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
284 * Returns negative error code on failure, zero on success.
286 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
287 resource_size_t
*offset
,
288 enum pci_mmap_state mmap_state
)
290 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
291 unsigned long io_offset
= 0;
295 return NULL
; /* should never happen */
297 /* If memory, add on the PCI bridge address offset */
298 if (mmap_state
== pci_mmap_mem
) {
299 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
300 *offset
+= hose
->pci_mem_offset
;
302 res_bit
= IORESOURCE_MEM
;
304 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
305 *offset
+= io_offset
;
306 res_bit
= IORESOURCE_IO
;
310 * Check that the offset requested corresponds to one of the
311 * resources of the device.
313 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
314 struct resource
*rp
= &dev
->resource
[i
];
315 int flags
= rp
->flags
;
317 /* treat ROM as memory (should be already) */
318 if (i
== PCI_ROM_RESOURCE
)
319 flags
|= IORESOURCE_MEM
;
321 /* Active and same type? */
322 if ((flags
& res_bit
) == 0)
325 /* In the range of this resource? */
326 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
329 /* found it! construct the final physical address */
330 if (mmap_state
== pci_mmap_io
)
331 *offset
+= hose
->io_base_phys
- io_offset
;
339 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
342 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
344 enum pci_mmap_state mmap_state
,
347 unsigned long prot
= pgprot_val(protection
);
349 /* Write combine is always 0 on non-memory space mappings. On
350 * memory space, if the user didn't pass 1, we check for a
351 * "prefetchable" resource. This is a bit hackish, but we use
352 * this to workaround the inability of /sysfs to provide a write
355 if (mmap_state
!= pci_mmap_mem
)
357 else if (write_combine
== 0) {
358 if (rp
->flags
& IORESOURCE_PREFETCH
)
362 /* XXX would be nice to have a way to ask for write-through */
364 return pgprot_noncached_wc(prot
);
366 return pgprot_noncached(prot
);
370 * This one is used by /dev/mem and fbdev who have no clue about the
371 * PCI device, it tries to find the PCI device first and calls the
374 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
379 struct pci_dev
*pdev
= NULL
;
380 struct resource
*found
= NULL
;
381 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
384 if (page_is_ram(pfn
))
387 prot
= pgprot_noncached(prot
);
388 for_each_pci_dev(pdev
) {
389 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
390 struct resource
*rp
= &pdev
->resource
[i
];
391 int flags
= rp
->flags
;
393 /* Active and same type? */
394 if ((flags
& IORESOURCE_MEM
) == 0)
396 /* In the range of this resource? */
397 if (offset
< (rp
->start
& PAGE_MASK
) ||
407 if (found
->flags
& IORESOURCE_PREFETCH
)
408 prot
= pgprot_noncached_wc(prot
);
412 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
413 (unsigned long long)offset
, pgprot_val(prot
));
420 * Perform the actual remap of the pages for a PCI device mapping, as
421 * appropriate for this architecture. The region in the process to map
422 * is described by vm_start and vm_end members of VMA, the base physical
423 * address is found in vm_pgoff.
424 * The pci device structure is provided so that architectures may make mapping
425 * decisions on a per-device or per-bus basis.
427 * Returns a negative error code on failure, zero on success.
429 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
430 enum pci_mmap_state mmap_state
, int write_combine
)
432 resource_size_t offset
=
433 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
437 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
441 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
442 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
444 mmap_state
, write_combine
);
446 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
447 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
452 /* This provides legacy IO read access on a bus */
453 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
455 unsigned long offset
;
456 struct pci_controller
*hose
= pci_bus_to_host(bus
);
457 struct resource
*rp
= &hose
->io_resource
;
460 /* Check if port can be supported by that bus. We only check
461 * the ranges of the PHB though, not the bus itself as the rules
462 * for forwarding legacy cycles down bridges are not our problem
463 * here. So if the host bridge supports it, we do it.
465 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
468 if (!(rp
->flags
& IORESOURCE_IO
))
470 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
472 addr
= hose
->io_base_virt
+ port
;
476 *((u8
*)val
) = in_8(addr
);
481 *((u16
*)val
) = in_le16(addr
);
486 *((u32
*)val
) = in_le32(addr
);
492 /* This provides legacy IO write access on a bus */
493 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
495 unsigned long offset
;
496 struct pci_controller
*hose
= pci_bus_to_host(bus
);
497 struct resource
*rp
= &hose
->io_resource
;
500 /* Check if port can be supported by that bus. We only check
501 * the ranges of the PHB though, not the bus itself as the rules
502 * for forwarding legacy cycles down bridges are not our problem
503 * here. So if the host bridge supports it, we do it.
505 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
508 if (!(rp
->flags
& IORESOURCE_IO
))
510 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
512 addr
= hose
->io_base_virt
+ port
;
514 /* WARNING: The generic code is idiotic. It gets passed a pointer
515 * to what can be a 1, 2 or 4 byte quantity and always reads that
516 * as a u32, which means that we have to correct the location of
517 * the data read within those 32 bits for size 1 and 2
521 out_8(addr
, val
>> 24);
526 out_le16(addr
, val
>> 16);
537 /* This provides legacy IO or memory mmap access on a bus */
538 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
539 struct vm_area_struct
*vma
,
540 enum pci_mmap_state mmap_state
)
542 struct pci_controller
*hose
= pci_bus_to_host(bus
);
543 resource_size_t offset
=
544 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
545 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
548 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
549 pci_domain_nr(bus
), bus
->number
,
550 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
551 (unsigned long long)offset
,
552 (unsigned long long)(offset
+ size
- 1));
554 if (mmap_state
== pci_mmap_mem
) {
557 * Because X is lame and can fail starting if it gets an error trying
558 * to mmap legacy_mem (instead of just moving on without legacy memory
559 * access) we fake it here by giving it anonymous memory, effectively
560 * behaving just like /dev/zero
562 if ((offset
+ size
) > hose
->isa_mem_size
) {
564 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
565 current
->comm
, current
->pid
, pci_domain_nr(bus
), bus
->number
);
566 if (vma
->vm_flags
& VM_SHARED
)
567 return shmem_zero_setup(vma
);
570 offset
+= hose
->isa_mem_phys
;
572 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
573 unsigned long roffset
= offset
+ io_offset
;
574 rp
= &hose
->io_resource
;
575 if (!(rp
->flags
& IORESOURCE_IO
))
577 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
579 offset
+= hose
->io_base_phys
;
581 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
583 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
584 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
585 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
586 vma
->vm_end
- vma
->vm_start
,
590 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
591 const struct resource
*rsrc
,
592 resource_size_t
*start
, resource_size_t
*end
)
594 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
595 resource_size_t offset
= 0;
600 if (rsrc
->flags
& IORESOURCE_IO
)
601 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
603 /* We pass a fully fixed up address to userland for MMIO instead of
604 * a BAR value because X is lame and expects to be able to use that
605 * to pass to /dev/mem !
607 * That means that we'll have potentially 64 bits values where some
608 * userland apps only expect 32 (like X itself since it thinks only
609 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
612 * Hopefully, the sysfs insterface is immune to that gunk. Once X
613 * has been fixed (and the fix spread enough), we can re-enable the
614 * 2 lines below and pass down a BAR value to userland. In that case
615 * we'll also have to re-enable the matching code in
616 * __pci_mmap_make_offset().
621 else if (rsrc
->flags
& IORESOURCE_MEM
)
622 offset
= hose
->pci_mem_offset
;
625 *start
= rsrc
->start
- offset
;
626 *end
= rsrc
->end
- offset
;
630 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
631 * @hose: newly allocated pci_controller to be setup
632 * @dev: device node of the host bridge
633 * @primary: set if primary bus (32 bits only, soon to be deprecated)
635 * This function will parse the "ranges" property of a PCI host bridge device
636 * node and setup the resource mapping of a pci controller based on its
639 * Life would be boring if it wasn't for a few issues that we have to deal
642 * - We can only cope with one IO space range and up to 3 Memory space
643 * ranges. However, some machines (thanks Apple !) tend to split their
644 * space into lots of small contiguous ranges. So we have to coalesce.
646 * - We can only cope with all memory ranges having the same offset
647 * between CPU addresses and PCI addresses. Unfortunately, some bridges
648 * are setup for a large 1:1 mapping along with a small "window" which
649 * maps PCI address 0 to some arbitrary high address of the CPU space in
650 * order to give access to the ISA memory hole.
651 * The way out of here that I've chosen for now is to always set the
652 * offset based on the first resource found, then override it if we
653 * have a different offset and the previous was set by an ISA hole.
655 * - Some busses have IO space not starting at 0, which causes trouble with
656 * the way we do our IO resource renumbering. The code somewhat deals with
657 * it for 64 bits but I would expect problems on 32 bits.
659 * - Some 32 bits platforms such as 4xx can have physical space larger than
660 * 32 bits so we need to use 64 bits values for the parsing
662 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
663 struct device_node
*dev
,
668 int pna
= of_n_addr_cells(dev
);
670 int memno
= 0, isa_hole
= -1;
672 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
673 unsigned long long isa_mb
= 0;
674 struct resource
*res
;
676 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
677 dev
->full_name
, primary
? "(primary)" : "");
679 /* Get ranges property */
680 ranges
= of_get_property(dev
, "ranges", &rlen
);
685 while ((rlen
-= np
* 4) >= 0) {
686 /* Read next ranges element */
687 pci_space
= ranges
[0];
688 pci_addr
= of_read_number(ranges
+ 1, 2);
689 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
690 size
= of_read_number(ranges
+ pna
+ 3, 2);
693 /* If we failed translation or got a zero-sized region
694 * (some FW try to feed us with non sensical zero sized regions
695 * such as power3 which look like some kind of attempt at exposing
696 * the VGA memory hole)
698 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
701 /* Now consume following elements while they are contiguous */
702 for (; rlen
>= np
* sizeof(u32
);
703 ranges
+= np
, rlen
-= np
* 4) {
704 if (ranges
[0] != pci_space
)
706 pci_next
= of_read_number(ranges
+ 1, 2);
707 cpu_next
= of_translate_address(dev
, ranges
+ 3);
708 if (pci_next
!= pci_addr
+ size
||
709 cpu_next
!= cpu_addr
+ size
)
711 size
+= of_read_number(ranges
+ pna
+ 3, 2);
714 /* Act based on address space type */
716 switch ((pci_space
>> 24) & 0x3) {
717 case 1: /* PCI IO space */
719 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
720 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
722 /* We support only one IO range */
723 if (hose
->pci_io_size
) {
725 " \\--> Skipped (too many) !\n");
729 /* On 32 bits, limit I/O space to 16MB */
730 if (size
> 0x01000000)
733 /* 32 bits needs to map IOs here */
734 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
736 /* Expect trouble if pci_addr is not 0 */
739 (unsigned long)hose
->io_base_virt
;
740 #endif /* CONFIG_PPC32 */
741 /* pci_io_size and io_base_phys always represent IO
742 * space starting at 0 so we factor in pci_addr
744 hose
->pci_io_size
= pci_addr
+ size
;
745 hose
->io_base_phys
= cpu_addr
- pci_addr
;
748 res
= &hose
->io_resource
;
749 res
->flags
= IORESOURCE_IO
;
750 res
->start
= pci_addr
;
752 case 2: /* PCI Memory space */
753 case 3: /* PCI 64 bits Memory space */
755 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
756 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
757 (pci_space
& 0x40000000) ? "Prefetch" : "");
759 /* We support only 3 memory ranges */
762 " \\--> Skipped (too many) !\n");
765 /* Handles ISA memory hole space here */
769 if (primary
|| isa_mem_base
== 0)
770 isa_mem_base
= cpu_addr
;
771 hose
->isa_mem_phys
= cpu_addr
;
772 hose
->isa_mem_size
= size
;
775 /* We get the PCI/Mem offset from the first range or
776 * the, current one if the offset came from an ISA
777 * hole. If they don't match, bugger.
780 (isa_hole
>= 0 && pci_addr
!= 0 &&
781 hose
->pci_mem_offset
== isa_mb
))
782 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
783 else if (pci_addr
!= 0 &&
784 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
786 " \\--> Skipped (offset mismatch) !\n");
791 res
= &hose
->mem_resources
[memno
++];
792 res
->flags
= IORESOURCE_MEM
;
793 if (pci_space
& 0x40000000)
794 res
->flags
|= IORESOURCE_PREFETCH
;
795 res
->start
= cpu_addr
;
799 res
->name
= dev
->full_name
;
800 res
->end
= res
->start
+ size
- 1;
807 /* If there's an ISA hole and the pci_mem_offset is -not- matching
808 * the ISA hole offset, then we need to remove the ISA hole from
809 * the resource list for that brige
811 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
812 unsigned int next
= isa_hole
+ 1;
813 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
815 memmove(&hose
->mem_resources
[isa_hole
],
816 &hose
->mem_resources
[next
],
817 sizeof(struct resource
) * (memno
- next
));
818 hose
->mem_resources
[--memno
].flags
= 0;
822 /* Decide whether to display the domain number in /proc */
823 int pci_proc_domain(struct pci_bus
*bus
)
825 struct pci_controller
*hose
= pci_bus_to_host(bus
);
827 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS
))
829 if (pci_has_flag(PCI_COMPAT_DOMAIN_0
))
830 return hose
->global_number
!= 0;
834 /* This header fixup will do the resource fixup for all devices as they are
835 * probed, but not for bridge ranges
837 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
839 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
843 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
847 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
848 struct resource
*res
= dev
->resource
+ i
;
852 /* If we're going to re-assign everything, we mark all resources
853 * as unset (and 0-base them). In addition, we mark BARs starting
854 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
855 * since in that case, we don't want to re-assign anything
857 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC
) ||
858 (res
->start
== 0 && !pci_has_flag(PCI_PROBE_ONLY
))) {
859 /* Only print message if not re-assigning */
860 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC
))
861 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
864 (unsigned long long)res
->start
,
865 (unsigned long long)res
->end
,
866 (unsigned int)res
->flags
);
867 res
->end
-= res
->start
;
869 res
->flags
|= IORESOURCE_UNSET
;
873 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
875 (unsigned long long)res
->start
,\
876 (unsigned long long)res
->end
,
877 (unsigned int)res
->flags
);
880 /* Call machine specific resource fixup */
881 if (ppc_md
.pcibios_fixup_resources
)
882 ppc_md
.pcibios_fixup_resources(dev
);
884 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
886 /* This function tries to figure out if a bridge resource has been initialized
887 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
888 * things go more smoothly when it gets it right. It should covers cases such
889 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
891 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
892 struct resource
*res
)
894 struct pci_controller
*hose
= pci_bus_to_host(bus
);
895 struct pci_dev
*dev
= bus
->self
;
896 resource_size_t offset
;
900 /* We don't do anything if PCI_PROBE_ONLY is set */
901 if (pci_has_flag(PCI_PROBE_ONLY
))
904 /* Job is a bit different between memory and IO */
905 if (res
->flags
& IORESOURCE_MEM
) {
906 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
907 * initialized by somebody
909 if (res
->start
!= hose
->pci_mem_offset
)
912 /* The BAR is 0, let's check if memory decoding is enabled on
913 * the bridge. If not, we consider it unassigned
915 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
916 if ((command
& PCI_COMMAND_MEMORY
) == 0)
919 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
920 * resources covers that starting address (0 then it's good enough for
923 for (i
= 0; i
< 3; i
++) {
924 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
925 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
929 /* Well, it starts at 0 and we know it will collide so we may as
930 * well consider it as unassigned. That covers the Apple case.
934 /* If the BAR is non-0, then we consider it assigned */
935 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
936 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
939 /* Here, we are a bit different than memory as typically IO space
940 * starting at low addresses -is- valid. What we do instead if that
941 * we consider as unassigned anything that doesn't have IO enabled
942 * in the PCI command register, and that's it.
944 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
945 if (command
& PCI_COMMAND_IO
)
948 /* It's starting at 0 and IO is disabled in the bridge, consider
955 /* Fixup resources of a PCI<->PCI bridge */
956 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
958 struct resource
*res
;
961 struct pci_dev
*dev
= bus
->self
;
963 pci_bus_for_each_resource(bus
, res
, i
) {
964 if (!res
|| !res
->flags
)
966 if (i
>= 3 && bus
->self
->transparent
)
969 /* If we are going to re-assign everything, mark the resource
970 * as unset and move it down to 0
972 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC
)) {
973 res
->flags
|= IORESOURCE_UNSET
;
974 res
->end
-= res
->start
;
979 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
981 (unsigned long long)res
->start
,\
982 (unsigned long long)res
->end
,
983 (unsigned int)res
->flags
);
985 /* Try to detect uninitialized P2P bridge resources,
986 * and clear them out so they get re-assigned later
988 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
990 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
995 void __devinit
pcibios_setup_bus_self(struct pci_bus
*bus
)
997 /* Fix up the bus resources for P2P bridges */
998 if (bus
->self
!= NULL
)
999 pcibios_fixup_bridge(bus
);
1001 /* Platform specific bus fixups. This is currently only used
1002 * by fsl_pci and I'm hoping to get rid of it at some point
1004 if (ppc_md
.pcibios_fixup_bus
)
1005 ppc_md
.pcibios_fixup_bus(bus
);
1007 /* Setup bus DMA mappings */
1008 if (ppc_md
.pci_dma_bus_setup
)
1009 ppc_md
.pci_dma_bus_setup(bus
);
1012 void __devinit
pcibios_setup_bus_devices(struct pci_bus
*bus
)
1014 struct pci_dev
*dev
;
1016 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1017 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
1019 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1020 /* Cardbus can call us to add new devices to a bus, so ignore
1021 * those who are already fully discovered
1026 /* Fixup NUMA node as it may not be setup yet by the generic
1027 * code and is needed by the DMA init
1029 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
1031 /* Hook up default DMA ops */
1032 set_dma_ops(&dev
->dev
, pci_dma_ops
);
1033 set_dma_offset(&dev
->dev
, PCI_DRAM_OFFSET
);
1035 /* Additional platform DMA/iommu setup */
1036 if (ppc_md
.pci_dma_dev_setup
)
1037 ppc_md
.pci_dma_dev_setup(dev
);
1039 /* Read default IRQs and fixup if necessary */
1040 pci_read_irq_line(dev
);
1041 if (ppc_md
.pci_irq_fixup
)
1042 ppc_md
.pci_irq_fixup(dev
);
1046 void pcibios_set_master(struct pci_dev
*dev
)
1048 /* No special bus mastering setup handling */
1051 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1053 /* When called from the generic PCI probe, read PCI<->PCI bridge
1054 * bases. This is -not- called when generating the PCI tree from
1055 * the OF device-tree.
1057 if (bus
->self
!= NULL
)
1058 pci_read_bridge_bases(bus
);
1060 /* Now fixup the bus bus */
1061 pcibios_setup_bus_self(bus
);
1063 /* Now fixup devices on that bus */
1064 pcibios_setup_bus_devices(bus
);
1066 EXPORT_SYMBOL(pcibios_fixup_bus
);
1068 void __devinit
pci_fixup_cardbus(struct pci_bus
*bus
)
1070 /* Now fixup devices on that bus */
1071 pcibios_setup_bus_devices(bus
);
1075 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1077 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN
) &&
1078 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1084 * We need to avoid collisions with `mirrored' VGA ports
1085 * and other strange ISA hardware, so we always want the
1086 * addresses to be allocated in the 0x000-0x0ff region
1089 * Why? Because some silly external IO cards only decode
1090 * the low 10 bits of the IO address. The 0x00-0xff region
1091 * is reserved for motherboard devices that decode all 16
1092 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1093 * but we want to try to avoid allocating at 0x2900-0x2bff
1094 * which might have be mirrored at 0x0100-0x03ff..
1096 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
1097 resource_size_t size
, resource_size_t align
)
1099 struct pci_dev
*dev
= data
;
1100 resource_size_t start
= res
->start
;
1102 if (res
->flags
& IORESOURCE_IO
) {
1103 if (skip_isa_ioresource_align(dev
))
1106 start
= (start
+ 0x3ff) & ~0x3ff;
1111 EXPORT_SYMBOL(pcibios_align_resource
);
1114 * Reparent resource children of pr that conflict with res
1115 * under res, and make res replace those children.
1117 static int reparent_resources(struct resource
*parent
,
1118 struct resource
*res
)
1120 struct resource
*p
, **pp
;
1121 struct resource
**firstpp
= NULL
;
1123 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1124 if (p
->end
< res
->start
)
1126 if (res
->end
< p
->start
)
1128 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1129 return -1; /* not completely contained */
1130 if (firstpp
== NULL
)
1133 if (firstpp
== NULL
)
1134 return -1; /* didn't find any conflicting entries? */
1135 res
->parent
= parent
;
1136 res
->child
= *firstpp
;
1140 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1142 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1144 (unsigned long long)p
->start
,
1145 (unsigned long long)p
->end
, res
->name
);
1151 * Handle resources of PCI devices. If the world were perfect, we could
1152 * just allocate all the resource regions and do nothing more. It isn't.
1153 * On the other hand, we cannot just re-allocate all devices, as it would
1154 * require us to know lots of host bridge internals. So we attempt to
1155 * keep as much of the original configuration as possible, but tweak it
1156 * when it's found to be wrong.
1158 * Known BIOS problems we have to work around:
1159 * - I/O or memory regions not configured
1160 * - regions configured, but not enabled in the command register
1161 * - bogus I/O addresses above 64K used
1162 * - expansion ROMs left enabled (this may sound harmless, but given
1163 * the fact the PCI specs explicitly allow address decoders to be
1164 * shared between expansion ROMs and other resource regions, it's
1165 * at least dangerous)
1168 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1169 * This gives us fixed barriers on where we can allocate.
1170 * (2) Allocate resources for all enabled devices. If there is
1171 * a collision, just mark the resource as unallocated. Also
1172 * disable expansion ROMs during this step.
1173 * (3) Try to allocate resources for disabled devices. If the
1174 * resources were assigned correctly, everything goes well,
1175 * if they weren't, they won't disturb allocation of other
1177 * (4) Assign new addresses to resources which were either
1178 * not configured at all or misconfigured. If explicitly
1179 * requested by the user, configure expansion ROM address
1183 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1187 struct resource
*res
, *pr
;
1189 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1190 pci_domain_nr(bus
), bus
->number
);
1192 pci_bus_for_each_resource(bus
, res
, i
) {
1193 if (!res
|| !res
->flags
|| res
->start
> res
->end
|| res
->parent
)
1196 /* If the resource was left unset at this point, we clear it */
1197 if (res
->flags
& IORESOURCE_UNSET
)
1198 goto clear_resource
;
1200 if (bus
->parent
== NULL
)
1201 pr
= (res
->flags
& IORESOURCE_IO
) ?
1202 &ioport_resource
: &iomem_resource
;
1204 pr
= pci_find_parent_resource(bus
->self
, res
);
1206 /* this happens when the generic PCI
1207 * code (wrongly) decides that this
1208 * bridge is transparent -- paulus
1214 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1215 "[0x%x], parent %p (%s)\n",
1216 bus
->self
? pci_name(bus
->self
) : "PHB",
1218 (unsigned long long)res
->start
,
1219 (unsigned long long)res
->end
,
1220 (unsigned int)res
->flags
,
1221 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1223 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1224 if (request_resource(pr
, res
) == 0)
1227 * Must be a conflict with an existing entry.
1228 * Move that entry (or entries) under the
1229 * bridge resource and try again.
1231 if (reparent_resources(pr
, res
) == 0)
1234 pr_warning("PCI: Cannot allocate resource region "
1235 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1237 res
->start
= res
->end
= 0;
1241 list_for_each_entry(b
, &bus
->children
, node
)
1242 pcibios_allocate_bus_resources(b
);
1245 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1247 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1249 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1251 (unsigned long long)r
->start
,
1252 (unsigned long long)r
->end
,
1253 (unsigned int)r
->flags
);
1255 pr
= pci_find_parent_resource(dev
, r
);
1256 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1257 request_resource(pr
, r
) < 0) {
1258 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1259 " of device %s, will remap\n", idx
, pci_name(dev
));
1261 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1263 (unsigned long long)pr
->start
,
1264 (unsigned long long)pr
->end
,
1265 (unsigned int)pr
->flags
);
1266 /* We'll assign a new address later */
1267 r
->flags
|= IORESOURCE_UNSET
;
1273 static void __init
pcibios_allocate_resources(int pass
)
1275 struct pci_dev
*dev
= NULL
;
1280 for_each_pci_dev(dev
) {
1281 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1282 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1283 r
= &dev
->resource
[idx
];
1284 if (r
->parent
) /* Already allocated */
1286 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1287 continue; /* Not assigned at all */
1288 /* We only allocate ROMs on pass 1 just in case they
1289 * have been screwed up by firmware
1291 if (idx
== PCI_ROM_RESOURCE
)
1293 if (r
->flags
& IORESOURCE_IO
)
1294 disabled
= !(command
& PCI_COMMAND_IO
);
1296 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1297 if (pass
== disabled
)
1298 alloc_resource(dev
, idx
);
1302 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1304 /* Turn the ROM off, leave the resource region,
1305 * but keep it unregistered.
1308 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1309 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1310 pr_debug("PCI: Switching off ROM of %s\n",
1312 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1313 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1314 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1320 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1322 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1323 resource_size_t offset
;
1324 struct resource
*res
, *pres
;
1327 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus
));
1330 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1332 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1333 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1334 BUG_ON(res
== NULL
);
1335 res
->name
= "Legacy IO";
1336 res
->flags
= IORESOURCE_IO
;
1337 res
->start
= offset
;
1338 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1339 pr_debug("Candidate legacy IO: %pR\n", res
);
1340 if (request_resource(&hose
->io_resource
, res
)) {
1342 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1343 pci_domain_nr(bus
), bus
->number
, res
);
1348 /* Check for memory */
1349 offset
= hose
->pci_mem_offset
;
1350 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1351 for (i
= 0; i
< 3; i
++) {
1352 pres
= &hose
->mem_resources
[i
];
1353 if (!(pres
->flags
& IORESOURCE_MEM
))
1355 pr_debug("hose mem res: %pR\n", pres
);
1356 if ((pres
->start
- offset
) <= 0xa0000 &&
1357 (pres
->end
- offset
) >= 0xbffff)
1362 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1363 BUG_ON(res
== NULL
);
1364 res
->name
= "Legacy VGA memory";
1365 res
->flags
= IORESOURCE_MEM
;
1366 res
->start
= 0xa0000 + offset
;
1367 res
->end
= 0xbffff + offset
;
1368 pr_debug("Candidate VGA memory: %pR\n", res
);
1369 if (request_resource(pres
, res
)) {
1371 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1372 pci_domain_nr(bus
), bus
->number
, res
);
1377 void __init
pcibios_resource_survey(void)
1381 /* Allocate and assign resources */
1382 list_for_each_entry(b
, &pci_root_buses
, node
)
1383 pcibios_allocate_bus_resources(b
);
1384 pcibios_allocate_resources(0);
1385 pcibios_allocate_resources(1);
1387 /* Before we start assigning unassigned resource, we try to reserve
1388 * the low IO area and the VGA memory area if they intersect the
1389 * bus available resources to avoid allocating things on top of them
1391 if (!pci_has_flag(PCI_PROBE_ONLY
)) {
1392 list_for_each_entry(b
, &pci_root_buses
, node
)
1393 pcibios_reserve_legacy_regions(b
);
1396 /* Now, if the platform didn't decide to blindly trust the firmware,
1397 * we proceed to assigning things that were left unassigned
1399 if (!pci_has_flag(PCI_PROBE_ONLY
)) {
1400 pr_debug("PCI: Assigning unassigned resources...\n");
1401 pci_assign_unassigned_resources();
1404 /* Call machine dependent fixup */
1405 if (ppc_md
.pcibios_fixup
)
1406 ppc_md
.pcibios_fixup();
1409 #ifdef CONFIG_HOTPLUG
1411 /* This is used by the PCI hotplug driver to allocate resource
1412 * of newly plugged busses. We can try to consolidate with the
1413 * rest of the code later, for now, keep it as-is as our main
1414 * resource allocation function doesn't deal with sub-trees yet.
1416 void pcibios_claim_one_bus(struct pci_bus
*bus
)
1418 struct pci_dev
*dev
;
1419 struct pci_bus
*child_bus
;
1421 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1424 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1425 struct resource
*r
= &dev
->resource
[i
];
1427 if (r
->parent
|| !r
->start
|| !r
->flags
)
1430 pr_debug("PCI: Claiming %s: "
1431 "Resource %d: %016llx..%016llx [%x]\n",
1433 (unsigned long long)r
->start
,
1434 (unsigned long long)r
->end
,
1435 (unsigned int)r
->flags
);
1437 pci_claim_resource(dev
, i
);
1441 list_for_each_entry(child_bus
, &bus
->children
, node
)
1442 pcibios_claim_one_bus(child_bus
);
1446 /* pcibios_finish_adding_to_bus
1448 * This is to be called by the hotplug code after devices have been
1449 * added to a bus, this include calling it for a PHB that is just
1452 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1454 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1455 pci_domain_nr(bus
), bus
->number
);
1457 /* Allocate bus and devices resources */
1458 pcibios_allocate_bus_resources(bus
);
1459 pcibios_claim_one_bus(bus
);
1461 /* Add new devices to global lists. Register in proc, sysfs. */
1462 pci_bus_add_devices(bus
);
1465 eeh_add_device_tree_late(bus
);
1467 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1469 #endif /* CONFIG_HOTPLUG */
1471 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1473 if (ppc_md
.pcibios_enable_device_hook
)
1474 if (ppc_md
.pcibios_enable_device_hook(dev
))
1477 return pci_enable_resources(dev
, mask
);
1480 resource_size_t
pcibios_io_space_offset(struct pci_controller
*hose
)
1482 return (unsigned long) hose
->io_base_virt
- _IO_BASE
;
1485 static void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
, struct list_head
*resources
)
1487 struct resource
*res
;
1490 /* Hookup PHB IO resource */
1491 res
= &hose
->io_resource
;
1494 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1495 " bridge %s (domain %d)\n",
1496 hose
->dn
->full_name
, hose
->global_number
);
1498 /* Workaround for lack of IO resource only on 32-bit */
1499 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1500 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1501 res
->flags
= IORESOURCE_IO
;
1502 #endif /* CONFIG_PPC32 */
1505 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1506 (unsigned long long)res
->start
,
1507 (unsigned long long)res
->end
,
1508 (unsigned long)res
->flags
);
1509 pci_add_resource_offset(resources
, res
, pcibios_io_space_offset(hose
));
1511 /* Hookup PHB Memory resources */
1512 for (i
= 0; i
< 3; ++i
) {
1513 res
= &hose
->mem_resources
[i
];
1517 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1518 "host bridge %s (domain %d)\n",
1519 hose
->dn
->full_name
, hose
->global_number
);
1521 /* Workaround for lack of MEM resource only on 32-bit */
1522 res
->start
= hose
->pci_mem_offset
;
1523 res
->end
= (resource_size_t
)-1LL;
1524 res
->flags
= IORESOURCE_MEM
;
1525 #endif /* CONFIG_PPC32 */
1528 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i
,
1529 (unsigned long long)res
->start
,
1530 (unsigned long long)res
->end
,
1531 (unsigned long)res
->flags
);
1532 pci_add_resource_offset(resources
, res
, hose
->pci_mem_offset
);
1535 pr_debug("PCI: PHB MEM offset = %016llx\n",
1536 (unsigned long long)hose
->pci_mem_offset
);
1537 pr_debug("PCI: PHB IO offset = %08lx\n",
1538 (unsigned long)hose
->io_base_virt
- _IO_BASE
);
1543 * Null PCI config access functions, for the case when we can't
1546 #define NULL_PCI_OP(rw, size, type) \
1548 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1550 return PCIBIOS_DEVICE_NOT_FOUND; \
1554 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1557 return PCIBIOS_DEVICE_NOT_FOUND
;
1561 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1564 return PCIBIOS_DEVICE_NOT_FOUND
;
1567 static struct pci_ops null_pci_ops
=
1569 .read
= null_read_config
,
1570 .write
= null_write_config
,
1574 * These functions are used early on before PCI scanning is done
1575 * and all of the pci_dev and pci_bus structures have been created.
1577 static struct pci_bus
*
1578 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1580 static struct pci_bus bus
;
1583 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1587 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1591 #define EARLY_PCI_OP(rw, size, type) \
1592 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1593 int devfn, int offset, type value) \
1595 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1596 devfn, offset, value); \
1599 EARLY_PCI_OP(read
, byte
, u8
*)
1600 EARLY_PCI_OP(read
, word
, u16
*)
1601 EARLY_PCI_OP(read
, dword
, u32
*)
1602 EARLY_PCI_OP(write
, byte
, u8
)
1603 EARLY_PCI_OP(write
, word
, u16
)
1604 EARLY_PCI_OP(write
, dword
, u32
)
1606 extern int pci_bus_find_capability (struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1607 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1610 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);
1613 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
)
1615 struct pci_controller
*hose
= bus
->sysdata
;
1617 return of_node_get(hose
->dn
);
1621 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1622 * @hose: Pointer to the PCI host controller instance structure
1624 void __devinit
pcibios_scan_phb(struct pci_controller
*hose
)
1626 LIST_HEAD(resources
);
1627 struct pci_bus
*bus
;
1628 struct device_node
*node
= hose
->dn
;
1631 pr_debug("PCI: Scanning PHB %s\n",
1632 node
? node
->full_name
: "<NO NAME>");
1634 /* Get some IO space for the new PHB */
1635 pcibios_setup_phb_io_space(hose
);
1637 /* Wire up PHB bus resources */
1638 pcibios_setup_phb_resources(hose
, &resources
);
1640 /* Create an empty bus for the toplevel */
1641 bus
= pci_create_root_bus(hose
->parent
, hose
->first_busno
,
1642 hose
->ops
, hose
, &resources
);
1644 pr_err("Failed to create bus for PCI domain %04x\n",
1645 hose
->global_number
);
1646 pci_free_resource_list(&resources
);
1649 bus
->secondary
= hose
->first_busno
;
1652 /* Get probe mode and perform scan */
1653 mode
= PCI_PROBE_NORMAL
;
1654 if (node
&& ppc_md
.pci_probe_mode
)
1655 mode
= ppc_md
.pci_probe_mode(bus
);
1656 pr_debug(" probe mode: %d\n", mode
);
1657 if (mode
== PCI_PROBE_DEVTREE
) {
1658 bus
->subordinate
= hose
->last_busno
;
1659 of_scan_bus(node
, bus
);
1662 if (mode
== PCI_PROBE_NORMAL
)
1663 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
1665 /* Platform gets a chance to do some global fixups before
1666 * we proceed to resource allocation
1668 if (ppc_md
.pcibios_fixup_phb
)
1669 ppc_md
.pcibios_fixup_phb(hose
);
1671 /* Configure PCI Express settings */
1672 if (bus
&& !pci_has_flag(PCI_PROBE_ONLY
)) {
1673 struct pci_bus
*child
;
1674 list_for_each_entry(child
, &bus
->children
, node
) {
1675 struct pci_dev
*self
= child
->self
;
1678 pcie_bus_configure_settings(child
, self
->pcie_mpss
);
1683 static void fixup_hide_host_resource_fsl(struct pci_dev
*dev
)
1685 int i
, class = dev
->class >> 8;
1686 /* When configured as agent, programing interface = 1 */
1687 int prog_if
= dev
->class & 0xf;
1689 if ((class == PCI_CLASS_PROCESSOR_POWERPC
||
1690 class == PCI_CLASS_BRIDGE_OTHER
) &&
1691 (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) &&
1693 (dev
->bus
->parent
== NULL
)) {
1694 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1695 dev
->resource
[i
].start
= 0;
1696 dev
->resource
[i
].end
= 0;
1697 dev
->resource
[i
].flags
= 0;
1701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA
, PCI_ANY_ID
, fixup_hide_host_resource_fsl
);
1702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
, fixup_hide_host_resource_fsl
);