2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
34 #include <asm/processor.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/byteorder.h>
39 #include <asm/machdep.h>
40 #include <asm/ppc-pci.h>
43 static DEFINE_SPINLOCK(hose_spinlock
);
46 /* XXX kill that some day ... */
47 static int global_phb_number
; /* Global phb counter */
49 /* ISA Memory physical address */
50 resource_size_t isa_mem_base
;
52 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
53 unsigned int pci_flags
= 0;
56 static struct dma_map_ops
*pci_dma_ops
= &dma_direct_ops
;
58 void set_pci_dma_ops(struct dma_map_ops
*dma_ops
)
60 pci_dma_ops
= dma_ops
;
63 struct dma_map_ops
*get_pci_dma_ops(void)
67 EXPORT_SYMBOL(get_pci_dma_ops
);
69 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
71 struct pci_controller
*phb
;
73 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
76 spin_lock(&hose_spinlock
);
77 phb
->global_number
= global_phb_number
++;
78 list_add_tail(&phb
->list_node
, &hose_list
);
79 spin_unlock(&hose_spinlock
);
81 phb
->is_dynamic
= mem_init_done
;
84 int nid
= of_node_to_nid(dev
);
86 if (nid
< 0 || !node_online(nid
))
89 PHB_SET_NODE(phb
, nid
);
95 void pcibios_free_controller(struct pci_controller
*phb
)
97 spin_lock(&hose_spinlock
);
98 list_del(&phb
->list_node
);
99 spin_unlock(&hose_spinlock
);
105 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
108 return hose
->pci_io_size
;
110 return resource_size(&hose
->io_resource
);
114 int pcibios_vaddr_is_ioport(void __iomem
*address
)
117 struct pci_controller
*hose
;
118 resource_size_t size
;
120 spin_lock(&hose_spinlock
);
121 list_for_each_entry(hose
, &hose_list
, list_node
) {
122 size
= pcibios_io_size(hose
);
123 if (address
>= hose
->io_base_virt
&&
124 address
< (hose
->io_base_virt
+ size
)) {
129 spin_unlock(&hose_spinlock
);
133 unsigned long pci_address_to_pio(phys_addr_t address
)
135 struct pci_controller
*hose
;
136 resource_size_t size
;
137 unsigned long ret
= ~0;
139 spin_lock(&hose_spinlock
);
140 list_for_each_entry(hose
, &hose_list
, list_node
) {
141 size
= pcibios_io_size(hose
);
142 if (address
>= hose
->io_base_phys
&&
143 address
< (hose
->io_base_phys
+ size
)) {
145 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
146 ret
= base
+ (address
- hose
->io_base_phys
);
150 spin_unlock(&hose_spinlock
);
154 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
157 * Return the domain number for this bus.
159 int pci_domain_nr(struct pci_bus
*bus
)
161 struct pci_controller
*hose
= pci_bus_to_host(bus
);
163 return hose
->global_number
;
165 EXPORT_SYMBOL(pci_domain_nr
);
167 /* This routine is meant to be used early during boot, when the
168 * PCI bus numbers have not yet been assigned, and you need to
169 * issue PCI config cycles to an OF device.
170 * It could also be used to "fix" RTAS config cycles if you want
171 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
174 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
177 struct pci_controller
*hose
, *tmp
;
178 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
179 if (hose
->dn
== node
)
186 static ssize_t
pci_show_devspec(struct device
*dev
,
187 struct device_attribute
*attr
, char *buf
)
189 struct pci_dev
*pdev
;
190 struct device_node
*np
;
192 pdev
= to_pci_dev (dev
);
193 np
= pci_device_to_OF_node(pdev
);
194 if (np
== NULL
|| np
->full_name
== NULL
)
196 return sprintf(buf
, "%s", np
->full_name
);
198 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
200 /* Add sysfs properties */
201 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
203 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
206 char __devinit
*pcibios_setup(char *str
)
212 * Reads the interrupt pin to determine if interrupt is use by card.
213 * If the interrupt is used, then gets the interrupt line from the
214 * openfirmware and sets it in the pci_dev and pci_config line.
216 static int pci_read_irq_line(struct pci_dev
*pci_dev
)
221 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
224 memset(&oirq
, 0xff, sizeof(oirq
));
226 /* Try to get a mapping from the device-tree */
227 if (of_irq_map_pci(pci_dev
, &oirq
)) {
230 /* If that fails, lets fallback to what is in the config
231 * space and map that through the default controller. We
232 * also set the type to level low since that's what PCI
233 * interrupts are. If your platform does differently, then
234 * either provide a proper interrupt tree or don't use this
237 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
241 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
242 line
== 0xff || line
== 0) {
245 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
248 virq
= irq_create_mapping(NULL
, line
);
250 irq_set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
252 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
253 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
254 oirq
.controller
? oirq
.controller
->full_name
:
257 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
261 pr_debug(" Failed to map !\n");
265 pr_debug(" Mapped to linux irq %d\n", virq
);
273 * Platform support for /proc/bus/pci/X/Y mmap()s,
274 * modelled on the sparc64 implementation by Dave Miller.
279 * Adjust vm_pgoff of VMA such that it is the physical page offset
280 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
282 * Basically, the user finds the base address for his device which he wishes
283 * to mmap. They read the 32-bit value from the config space base register,
284 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
285 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
287 * Returns negative error code on failure, zero on success.
289 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
290 resource_size_t
*offset
,
291 enum pci_mmap_state mmap_state
)
293 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
294 unsigned long io_offset
= 0;
298 return NULL
; /* should never happen */
300 /* If memory, add on the PCI bridge address offset */
301 if (mmap_state
== pci_mmap_mem
) {
302 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
303 *offset
+= hose
->pci_mem_offset
;
305 res_bit
= IORESOURCE_MEM
;
307 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
308 *offset
+= io_offset
;
309 res_bit
= IORESOURCE_IO
;
313 * Check that the offset requested corresponds to one of the
314 * resources of the device.
316 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
317 struct resource
*rp
= &dev
->resource
[i
];
318 int flags
= rp
->flags
;
320 /* treat ROM as memory (should be already) */
321 if (i
== PCI_ROM_RESOURCE
)
322 flags
|= IORESOURCE_MEM
;
324 /* Active and same type? */
325 if ((flags
& res_bit
) == 0)
328 /* In the range of this resource? */
329 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
332 /* found it! construct the final physical address */
333 if (mmap_state
== pci_mmap_io
)
334 *offset
+= hose
->io_base_phys
- io_offset
;
342 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
345 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
347 enum pci_mmap_state mmap_state
,
350 unsigned long prot
= pgprot_val(protection
);
352 /* Write combine is always 0 on non-memory space mappings. On
353 * memory space, if the user didn't pass 1, we check for a
354 * "prefetchable" resource. This is a bit hackish, but we use
355 * this to workaround the inability of /sysfs to provide a write
358 if (mmap_state
!= pci_mmap_mem
)
360 else if (write_combine
== 0) {
361 if (rp
->flags
& IORESOURCE_PREFETCH
)
365 /* XXX would be nice to have a way to ask for write-through */
367 return pgprot_noncached_wc(prot
);
369 return pgprot_noncached(prot
);
373 * This one is used by /dev/mem and fbdev who have no clue about the
374 * PCI device, it tries to find the PCI device first and calls the
377 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
382 struct pci_dev
*pdev
= NULL
;
383 struct resource
*found
= NULL
;
384 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
387 if (page_is_ram(pfn
))
390 prot
= pgprot_noncached(prot
);
391 for_each_pci_dev(pdev
) {
392 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
393 struct resource
*rp
= &pdev
->resource
[i
];
394 int flags
= rp
->flags
;
396 /* Active and same type? */
397 if ((flags
& IORESOURCE_MEM
) == 0)
399 /* In the range of this resource? */
400 if (offset
< (rp
->start
& PAGE_MASK
) ||
410 if (found
->flags
& IORESOURCE_PREFETCH
)
411 prot
= pgprot_noncached_wc(prot
);
415 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
416 (unsigned long long)offset
, pgprot_val(prot
));
423 * Perform the actual remap of the pages for a PCI device mapping, as
424 * appropriate for this architecture. The region in the process to map
425 * is described by vm_start and vm_end members of VMA, the base physical
426 * address is found in vm_pgoff.
427 * The pci device structure is provided so that architectures may make mapping
428 * decisions on a per-device or per-bus basis.
430 * Returns a negative error code on failure, zero on success.
432 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
433 enum pci_mmap_state mmap_state
, int write_combine
)
435 resource_size_t offset
=
436 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
440 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
444 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
445 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
447 mmap_state
, write_combine
);
449 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
450 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
455 /* This provides legacy IO read access on a bus */
456 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
458 unsigned long offset
;
459 struct pci_controller
*hose
= pci_bus_to_host(bus
);
460 struct resource
*rp
= &hose
->io_resource
;
463 /* Check if port can be supported by that bus. We only check
464 * the ranges of the PHB though, not the bus itself as the rules
465 * for forwarding legacy cycles down bridges are not our problem
466 * here. So if the host bridge supports it, we do it.
468 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
471 if (!(rp
->flags
& IORESOURCE_IO
))
473 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
475 addr
= hose
->io_base_virt
+ port
;
479 *((u8
*)val
) = in_8(addr
);
484 *((u16
*)val
) = in_le16(addr
);
489 *((u32
*)val
) = in_le32(addr
);
495 /* This provides legacy IO write access on a bus */
496 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
498 unsigned long offset
;
499 struct pci_controller
*hose
= pci_bus_to_host(bus
);
500 struct resource
*rp
= &hose
->io_resource
;
503 /* Check if port can be supported by that bus. We only check
504 * the ranges of the PHB though, not the bus itself as the rules
505 * for forwarding legacy cycles down bridges are not our problem
506 * here. So if the host bridge supports it, we do it.
508 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
511 if (!(rp
->flags
& IORESOURCE_IO
))
513 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
515 addr
= hose
->io_base_virt
+ port
;
517 /* WARNING: The generic code is idiotic. It gets passed a pointer
518 * to what can be a 1, 2 or 4 byte quantity and always reads that
519 * as a u32, which means that we have to correct the location of
520 * the data read within those 32 bits for size 1 and 2
524 out_8(addr
, val
>> 24);
529 out_le16(addr
, val
>> 16);
540 /* This provides legacy IO or memory mmap access on a bus */
541 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
542 struct vm_area_struct
*vma
,
543 enum pci_mmap_state mmap_state
)
545 struct pci_controller
*hose
= pci_bus_to_host(bus
);
546 resource_size_t offset
=
547 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
548 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
551 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
552 pci_domain_nr(bus
), bus
->number
,
553 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
554 (unsigned long long)offset
,
555 (unsigned long long)(offset
+ size
- 1));
557 if (mmap_state
== pci_mmap_mem
) {
560 * Because X is lame and can fail starting if it gets an error trying
561 * to mmap legacy_mem (instead of just moving on without legacy memory
562 * access) we fake it here by giving it anonymous memory, effectively
563 * behaving just like /dev/zero
565 if ((offset
+ size
) > hose
->isa_mem_size
) {
567 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
568 current
->comm
, current
->pid
, pci_domain_nr(bus
), bus
->number
);
569 if (vma
->vm_flags
& VM_SHARED
)
570 return shmem_zero_setup(vma
);
573 offset
+= hose
->isa_mem_phys
;
575 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
576 unsigned long roffset
= offset
+ io_offset
;
577 rp
= &hose
->io_resource
;
578 if (!(rp
->flags
& IORESOURCE_IO
))
580 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
582 offset
+= hose
->io_base_phys
;
584 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
586 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
587 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
588 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
589 vma
->vm_end
- vma
->vm_start
,
593 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
594 const struct resource
*rsrc
,
595 resource_size_t
*start
, resource_size_t
*end
)
597 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
598 resource_size_t offset
= 0;
603 if (rsrc
->flags
& IORESOURCE_IO
)
604 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
606 /* We pass a fully fixed up address to userland for MMIO instead of
607 * a BAR value because X is lame and expects to be able to use that
608 * to pass to /dev/mem !
610 * That means that we'll have potentially 64 bits values where some
611 * userland apps only expect 32 (like X itself since it thinks only
612 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
615 * Hopefully, the sysfs insterface is immune to that gunk. Once X
616 * has been fixed (and the fix spread enough), we can re-enable the
617 * 2 lines below and pass down a BAR value to userland. In that case
618 * we'll also have to re-enable the matching code in
619 * __pci_mmap_make_offset().
624 else if (rsrc
->flags
& IORESOURCE_MEM
)
625 offset
= hose
->pci_mem_offset
;
628 *start
= rsrc
->start
- offset
;
629 *end
= rsrc
->end
- offset
;
633 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
634 * @hose: newly allocated pci_controller to be setup
635 * @dev: device node of the host bridge
636 * @primary: set if primary bus (32 bits only, soon to be deprecated)
638 * This function will parse the "ranges" property of a PCI host bridge device
639 * node and setup the resource mapping of a pci controller based on its
642 * Life would be boring if it wasn't for a few issues that we have to deal
645 * - We can only cope with one IO space range and up to 3 Memory space
646 * ranges. However, some machines (thanks Apple !) tend to split their
647 * space into lots of small contiguous ranges. So we have to coalesce.
649 * - We can only cope with all memory ranges having the same offset
650 * between CPU addresses and PCI addresses. Unfortunately, some bridges
651 * are setup for a large 1:1 mapping along with a small "window" which
652 * maps PCI address 0 to some arbitrary high address of the CPU space in
653 * order to give access to the ISA memory hole.
654 * The way out of here that I've chosen for now is to always set the
655 * offset based on the first resource found, then override it if we
656 * have a different offset and the previous was set by an ISA hole.
658 * - Some busses have IO space not starting at 0, which causes trouble with
659 * the way we do our IO resource renumbering. The code somewhat deals with
660 * it for 64 bits but I would expect problems on 32 bits.
662 * - Some 32 bits platforms such as 4xx can have physical space larger than
663 * 32 bits so we need to use 64 bits values for the parsing
665 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
666 struct device_node
*dev
,
671 int pna
= of_n_addr_cells(dev
);
673 int memno
= 0, isa_hole
= -1;
675 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
676 unsigned long long isa_mb
= 0;
677 struct resource
*res
;
679 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
680 dev
->full_name
, primary
? "(primary)" : "");
682 /* Get ranges property */
683 ranges
= of_get_property(dev
, "ranges", &rlen
);
688 while ((rlen
-= np
* 4) >= 0) {
689 /* Read next ranges element */
690 pci_space
= ranges
[0];
691 pci_addr
= of_read_number(ranges
+ 1, 2);
692 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
693 size
= of_read_number(ranges
+ pna
+ 3, 2);
696 /* If we failed translation or got a zero-sized region
697 * (some FW try to feed us with non sensical zero sized regions
698 * such as power3 which look like some kind of attempt at exposing
699 * the VGA memory hole)
701 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
704 /* Now consume following elements while they are contiguous */
705 for (; rlen
>= np
* sizeof(u32
);
706 ranges
+= np
, rlen
-= np
* 4) {
707 if (ranges
[0] != pci_space
)
709 pci_next
= of_read_number(ranges
+ 1, 2);
710 cpu_next
= of_translate_address(dev
, ranges
+ 3);
711 if (pci_next
!= pci_addr
+ size
||
712 cpu_next
!= cpu_addr
+ size
)
714 size
+= of_read_number(ranges
+ pna
+ 3, 2);
717 /* Act based on address space type */
719 switch ((pci_space
>> 24) & 0x3) {
720 case 1: /* PCI IO space */
722 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
723 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
725 /* We support only one IO range */
726 if (hose
->pci_io_size
) {
728 " \\--> Skipped (too many) !\n");
732 /* On 32 bits, limit I/O space to 16MB */
733 if (size
> 0x01000000)
736 /* 32 bits needs to map IOs here */
737 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
739 /* Expect trouble if pci_addr is not 0 */
742 (unsigned long)hose
->io_base_virt
;
743 #endif /* CONFIG_PPC32 */
744 /* pci_io_size and io_base_phys always represent IO
745 * space starting at 0 so we factor in pci_addr
747 hose
->pci_io_size
= pci_addr
+ size
;
748 hose
->io_base_phys
= cpu_addr
- pci_addr
;
751 res
= &hose
->io_resource
;
752 res
->flags
= IORESOURCE_IO
;
753 res
->start
= pci_addr
;
755 case 2: /* PCI Memory space */
756 case 3: /* PCI 64 bits Memory space */
758 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
759 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
760 (pci_space
& 0x40000000) ? "Prefetch" : "");
762 /* We support only 3 memory ranges */
765 " \\--> Skipped (too many) !\n");
768 /* Handles ISA memory hole space here */
772 if (primary
|| isa_mem_base
== 0)
773 isa_mem_base
= cpu_addr
;
774 hose
->isa_mem_phys
= cpu_addr
;
775 hose
->isa_mem_size
= size
;
778 /* We get the PCI/Mem offset from the first range or
779 * the, current one if the offset came from an ISA
780 * hole. If they don't match, bugger.
783 (isa_hole
>= 0 && pci_addr
!= 0 &&
784 hose
->pci_mem_offset
== isa_mb
))
785 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
786 else if (pci_addr
!= 0 &&
787 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
789 " \\--> Skipped (offset mismatch) !\n");
794 res
= &hose
->mem_resources
[memno
++];
795 res
->flags
= IORESOURCE_MEM
;
796 if (pci_space
& 0x40000000)
797 res
->flags
|= IORESOURCE_PREFETCH
;
798 res
->start
= cpu_addr
;
802 res
->name
= dev
->full_name
;
803 res
->end
= res
->start
+ size
- 1;
810 /* If there's an ISA hole and the pci_mem_offset is -not- matching
811 * the ISA hole offset, then we need to remove the ISA hole from
812 * the resource list for that brige
814 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
815 unsigned int next
= isa_hole
+ 1;
816 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
818 memmove(&hose
->mem_resources
[isa_hole
],
819 &hose
->mem_resources
[next
],
820 sizeof(struct resource
) * (memno
- next
));
821 hose
->mem_resources
[--memno
].flags
= 0;
825 /* Decide whether to display the domain number in /proc */
826 int pci_proc_domain(struct pci_bus
*bus
)
828 struct pci_controller
*hose
= pci_bus_to_host(bus
);
830 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS
))
832 if (pci_has_flag(PCI_COMPAT_DOMAIN_0
))
833 return hose
->global_number
!= 0;
837 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
838 struct resource
*res
)
840 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
841 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
845 if (res
->flags
& IORESOURCE_IO
) {
846 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
848 } else if (res
->flags
& IORESOURCE_MEM
)
849 offset
= hose
->pci_mem_offset
;
851 region
->start
= (res
->start
- offset
) & mask
;
852 region
->end
= (res
->end
- offset
) & mask
;
854 EXPORT_SYMBOL(pcibios_resource_to_bus
);
856 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
857 struct pci_bus_region
*region
)
859 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
860 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
864 if (res
->flags
& IORESOURCE_IO
) {
865 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
867 } else if (res
->flags
& IORESOURCE_MEM
)
868 offset
= hose
->pci_mem_offset
;
869 res
->start
= (region
->start
+ offset
) & mask
;
870 res
->end
= (region
->end
+ offset
) & mask
;
872 EXPORT_SYMBOL(pcibios_bus_to_resource
);
874 /* Fixup a bus resource into a linux resource */
875 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
877 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
878 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
880 if (res
->flags
& IORESOURCE_IO
) {
881 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
883 } else if (res
->flags
& IORESOURCE_MEM
)
884 offset
= hose
->pci_mem_offset
;
886 res
->start
= (res
->start
+ offset
) & mask
;
887 res
->end
= (res
->end
+ offset
) & mask
;
891 /* This header fixup will do the resource fixup for all devices as they are
892 * probed, but not for bridge ranges
894 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
896 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
900 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
904 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
905 struct resource
*res
= dev
->resource
+ i
;
909 /* If we're going to re-assign everything, we mark all resources
910 * as unset (and 0-base them). In addition, we mark BARs starting
911 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
912 * since in that case, we don't want to re-assign anything
914 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC
) ||
915 (res
->start
== 0 && !pci_has_flag(PCI_PROBE_ONLY
))) {
916 /* Only print message if not re-assigning */
917 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC
))
918 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
921 (unsigned long long)res
->start
,
922 (unsigned long long)res
->end
,
923 (unsigned int)res
->flags
);
924 res
->end
-= res
->start
;
926 res
->flags
|= IORESOURCE_UNSET
;
930 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
932 (unsigned long long)res
->start
,\
933 (unsigned long long)res
->end
,
934 (unsigned int)res
->flags
);
936 fixup_resource(res
, dev
);
938 pr_debug("PCI:%s %016llx-%016llx\n",
940 (unsigned long long)res
->start
,
941 (unsigned long long)res
->end
);
944 /* Call machine specific resource fixup */
945 if (ppc_md
.pcibios_fixup_resources
)
946 ppc_md
.pcibios_fixup_resources(dev
);
948 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
950 /* This function tries to figure out if a bridge resource has been initialized
951 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
952 * things go more smoothly when it gets it right. It should covers cases such
953 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
955 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
956 struct resource
*res
)
958 struct pci_controller
*hose
= pci_bus_to_host(bus
);
959 struct pci_dev
*dev
= bus
->self
;
960 resource_size_t offset
;
964 /* We don't do anything if PCI_PROBE_ONLY is set */
965 if (pci_has_flag(PCI_PROBE_ONLY
))
968 /* Job is a bit different between memory and IO */
969 if (res
->flags
& IORESOURCE_MEM
) {
970 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
971 * initialized by somebody
973 if (res
->start
!= hose
->pci_mem_offset
)
976 /* The BAR is 0, let's check if memory decoding is enabled on
977 * the bridge. If not, we consider it unassigned
979 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
980 if ((command
& PCI_COMMAND_MEMORY
) == 0)
983 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
984 * resources covers that starting address (0 then it's good enough for
987 for (i
= 0; i
< 3; i
++) {
988 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
989 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
993 /* Well, it starts at 0 and we know it will collide so we may as
994 * well consider it as unassigned. That covers the Apple case.
998 /* If the BAR is non-0, then we consider it assigned */
999 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1000 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
1003 /* Here, we are a bit different than memory as typically IO space
1004 * starting at low addresses -is- valid. What we do instead if that
1005 * we consider as unassigned anything that doesn't have IO enabled
1006 * in the PCI command register, and that's it.
1008 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1009 if (command
& PCI_COMMAND_IO
)
1012 /* It's starting at 0 and IO is disabled in the bridge, consider
1019 /* Fixup resources of a PCI<->PCI bridge */
1020 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
1022 struct resource
*res
;
1025 struct pci_dev
*dev
= bus
->self
;
1027 pci_bus_for_each_resource(bus
, res
, i
) {
1028 if (!res
|| !res
->flags
)
1030 if (i
>= 3 && bus
->self
->transparent
)
1033 /* If we are going to re-assign everything, mark the resource
1034 * as unset and move it down to 0
1036 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC
)) {
1037 res
->flags
|= IORESOURCE_UNSET
;
1038 res
->end
-= res
->start
;
1043 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1045 (unsigned long long)res
->start
,\
1046 (unsigned long long)res
->end
,
1047 (unsigned int)res
->flags
);
1050 fixup_resource(res
, dev
);
1052 /* Try to detect uninitialized P2P bridge resources,
1053 * and clear them out so they get re-assigned later
1055 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1057 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
1060 pr_debug("PCI:%s %016llx-%016llx\n",
1062 (unsigned long long)res
->start
,
1063 (unsigned long long)res
->end
);
1068 void __devinit
pcibios_setup_bus_self(struct pci_bus
*bus
)
1070 /* Fix up the bus resources for P2P bridges */
1071 if (bus
->self
!= NULL
)
1072 pcibios_fixup_bridge(bus
);
1074 /* Platform specific bus fixups. This is currently only used
1075 * by fsl_pci and I'm hoping to get rid of it at some point
1077 if (ppc_md
.pcibios_fixup_bus
)
1078 ppc_md
.pcibios_fixup_bus(bus
);
1080 /* Setup bus DMA mappings */
1081 if (ppc_md
.pci_dma_bus_setup
)
1082 ppc_md
.pci_dma_bus_setup(bus
);
1085 void __devinit
pcibios_setup_bus_devices(struct pci_bus
*bus
)
1087 struct pci_dev
*dev
;
1089 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1090 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
1092 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1093 /* Cardbus can call us to add new devices to a bus, so ignore
1094 * those who are already fully discovered
1099 /* Fixup NUMA node as it may not be setup yet by the generic
1100 * code and is needed by the DMA init
1102 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
1104 /* Hook up default DMA ops */
1105 set_dma_ops(&dev
->dev
, pci_dma_ops
);
1106 set_dma_offset(&dev
->dev
, PCI_DRAM_OFFSET
);
1108 /* Additional platform DMA/iommu setup */
1109 if (ppc_md
.pci_dma_dev_setup
)
1110 ppc_md
.pci_dma_dev_setup(dev
);
1112 /* Read default IRQs and fixup if necessary */
1113 pci_read_irq_line(dev
);
1114 if (ppc_md
.pci_irq_fixup
)
1115 ppc_md
.pci_irq_fixup(dev
);
1119 void pcibios_set_master(struct pci_dev
*dev
)
1121 /* No special bus mastering setup handling */
1124 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1126 /* When called from the generic PCI probe, read PCI<->PCI bridge
1127 * bases. This is -not- called when generating the PCI tree from
1128 * the OF device-tree.
1130 if (bus
->self
!= NULL
)
1131 pci_read_bridge_bases(bus
);
1133 /* Now fixup the bus bus */
1134 pcibios_setup_bus_self(bus
);
1136 /* Now fixup devices on that bus */
1137 pcibios_setup_bus_devices(bus
);
1139 EXPORT_SYMBOL(pcibios_fixup_bus
);
1141 void __devinit
pci_fixup_cardbus(struct pci_bus
*bus
)
1143 /* Now fixup devices on that bus */
1144 pcibios_setup_bus_devices(bus
);
1148 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1150 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN
) &&
1151 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1157 * We need to avoid collisions with `mirrored' VGA ports
1158 * and other strange ISA hardware, so we always want the
1159 * addresses to be allocated in the 0x000-0x0ff region
1162 * Why? Because some silly external IO cards only decode
1163 * the low 10 bits of the IO address. The 0x00-0xff region
1164 * is reserved for motherboard devices that decode all 16
1165 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1166 * but we want to try to avoid allocating at 0x2900-0x2bff
1167 * which might have be mirrored at 0x0100-0x03ff..
1169 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
1170 resource_size_t size
, resource_size_t align
)
1172 struct pci_dev
*dev
= data
;
1173 resource_size_t start
= res
->start
;
1175 if (res
->flags
& IORESOURCE_IO
) {
1176 if (skip_isa_ioresource_align(dev
))
1179 start
= (start
+ 0x3ff) & ~0x3ff;
1184 EXPORT_SYMBOL(pcibios_align_resource
);
1187 * Reparent resource children of pr that conflict with res
1188 * under res, and make res replace those children.
1190 static int reparent_resources(struct resource
*parent
,
1191 struct resource
*res
)
1193 struct resource
*p
, **pp
;
1194 struct resource
**firstpp
= NULL
;
1196 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1197 if (p
->end
< res
->start
)
1199 if (res
->end
< p
->start
)
1201 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1202 return -1; /* not completely contained */
1203 if (firstpp
== NULL
)
1206 if (firstpp
== NULL
)
1207 return -1; /* didn't find any conflicting entries? */
1208 res
->parent
= parent
;
1209 res
->child
= *firstpp
;
1213 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1215 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1217 (unsigned long long)p
->start
,
1218 (unsigned long long)p
->end
, res
->name
);
1224 * Handle resources of PCI devices. If the world were perfect, we could
1225 * just allocate all the resource regions and do nothing more. It isn't.
1226 * On the other hand, we cannot just re-allocate all devices, as it would
1227 * require us to know lots of host bridge internals. So we attempt to
1228 * keep as much of the original configuration as possible, but tweak it
1229 * when it's found to be wrong.
1231 * Known BIOS problems we have to work around:
1232 * - I/O or memory regions not configured
1233 * - regions configured, but not enabled in the command register
1234 * - bogus I/O addresses above 64K used
1235 * - expansion ROMs left enabled (this may sound harmless, but given
1236 * the fact the PCI specs explicitly allow address decoders to be
1237 * shared between expansion ROMs and other resource regions, it's
1238 * at least dangerous)
1241 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1242 * This gives us fixed barriers on where we can allocate.
1243 * (2) Allocate resources for all enabled devices. If there is
1244 * a collision, just mark the resource as unallocated. Also
1245 * disable expansion ROMs during this step.
1246 * (3) Try to allocate resources for disabled devices. If the
1247 * resources were assigned correctly, everything goes well,
1248 * if they weren't, they won't disturb allocation of other
1250 * (4) Assign new addresses to resources which were either
1251 * not configured at all or misconfigured. If explicitly
1252 * requested by the user, configure expansion ROM address
1256 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1260 struct resource
*res
, *pr
;
1262 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1263 pci_domain_nr(bus
), bus
->number
);
1265 pci_bus_for_each_resource(bus
, res
, i
) {
1266 if (!res
|| !res
->flags
|| res
->start
> res
->end
|| res
->parent
)
1269 /* If the resource was left unset at this point, we clear it */
1270 if (res
->flags
& IORESOURCE_UNSET
)
1271 goto clear_resource
;
1273 if (bus
->parent
== NULL
)
1274 pr
= (res
->flags
& IORESOURCE_IO
) ?
1275 &ioport_resource
: &iomem_resource
;
1277 pr
= pci_find_parent_resource(bus
->self
, res
);
1279 /* this happens when the generic PCI
1280 * code (wrongly) decides that this
1281 * bridge is transparent -- paulus
1287 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1288 "[0x%x], parent %p (%s)\n",
1289 bus
->self
? pci_name(bus
->self
) : "PHB",
1291 (unsigned long long)res
->start
,
1292 (unsigned long long)res
->end
,
1293 (unsigned int)res
->flags
,
1294 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1296 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1297 if (request_resource(pr
, res
) == 0)
1300 * Must be a conflict with an existing entry.
1301 * Move that entry (or entries) under the
1302 * bridge resource and try again.
1304 if (reparent_resources(pr
, res
) == 0)
1307 pr_warning("PCI: Cannot allocate resource region "
1308 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1310 res
->start
= res
->end
= 0;
1314 list_for_each_entry(b
, &bus
->children
, node
)
1315 pcibios_allocate_bus_resources(b
);
1318 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1320 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1322 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1324 (unsigned long long)r
->start
,
1325 (unsigned long long)r
->end
,
1326 (unsigned int)r
->flags
);
1328 pr
= pci_find_parent_resource(dev
, r
);
1329 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1330 request_resource(pr
, r
) < 0) {
1331 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1332 " of device %s, will remap\n", idx
, pci_name(dev
));
1334 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1336 (unsigned long long)pr
->start
,
1337 (unsigned long long)pr
->end
,
1338 (unsigned int)pr
->flags
);
1339 /* We'll assign a new address later */
1340 r
->flags
|= IORESOURCE_UNSET
;
1346 static void __init
pcibios_allocate_resources(int pass
)
1348 struct pci_dev
*dev
= NULL
;
1353 for_each_pci_dev(dev
) {
1354 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1355 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1356 r
= &dev
->resource
[idx
];
1357 if (r
->parent
) /* Already allocated */
1359 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1360 continue; /* Not assigned at all */
1361 /* We only allocate ROMs on pass 1 just in case they
1362 * have been screwed up by firmware
1364 if (idx
== PCI_ROM_RESOURCE
)
1366 if (r
->flags
& IORESOURCE_IO
)
1367 disabled
= !(command
& PCI_COMMAND_IO
);
1369 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1370 if (pass
== disabled
)
1371 alloc_resource(dev
, idx
);
1375 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1377 /* Turn the ROM off, leave the resource region,
1378 * but keep it unregistered.
1381 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1382 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1383 pr_debug("PCI: Switching off ROM of %s\n",
1385 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1386 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1387 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1393 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1395 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1396 resource_size_t offset
;
1397 struct resource
*res
, *pres
;
1400 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus
));
1403 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1405 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1406 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1407 BUG_ON(res
== NULL
);
1408 res
->name
= "Legacy IO";
1409 res
->flags
= IORESOURCE_IO
;
1410 res
->start
= offset
;
1411 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1412 pr_debug("Candidate legacy IO: %pR\n", res
);
1413 if (request_resource(&hose
->io_resource
, res
)) {
1415 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1416 pci_domain_nr(bus
), bus
->number
, res
);
1421 /* Check for memory */
1422 offset
= hose
->pci_mem_offset
;
1423 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1424 for (i
= 0; i
< 3; i
++) {
1425 pres
= &hose
->mem_resources
[i
];
1426 if (!(pres
->flags
& IORESOURCE_MEM
))
1428 pr_debug("hose mem res: %pR\n", pres
);
1429 if ((pres
->start
- offset
) <= 0xa0000 &&
1430 (pres
->end
- offset
) >= 0xbffff)
1435 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1436 BUG_ON(res
== NULL
);
1437 res
->name
= "Legacy VGA memory";
1438 res
->flags
= IORESOURCE_MEM
;
1439 res
->start
= 0xa0000 + offset
;
1440 res
->end
= 0xbffff + offset
;
1441 pr_debug("Candidate VGA memory: %pR\n", res
);
1442 if (request_resource(pres
, res
)) {
1444 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1445 pci_domain_nr(bus
), bus
->number
, res
);
1450 void __init
pcibios_resource_survey(void)
1454 /* Allocate and assign resources */
1455 list_for_each_entry(b
, &pci_root_buses
, node
)
1456 pcibios_allocate_bus_resources(b
);
1457 pcibios_allocate_resources(0);
1458 pcibios_allocate_resources(1);
1460 /* Before we start assigning unassigned resource, we try to reserve
1461 * the low IO area and the VGA memory area if they intersect the
1462 * bus available resources to avoid allocating things on top of them
1464 if (!pci_has_flag(PCI_PROBE_ONLY
)) {
1465 list_for_each_entry(b
, &pci_root_buses
, node
)
1466 pcibios_reserve_legacy_regions(b
);
1469 /* Now, if the platform didn't decide to blindly trust the firmware,
1470 * we proceed to assigning things that were left unassigned
1472 if (!pci_has_flag(PCI_PROBE_ONLY
)) {
1473 pr_debug("PCI: Assigning unassigned resources...\n");
1474 pci_assign_unassigned_resources();
1477 /* Call machine dependent fixup */
1478 if (ppc_md
.pcibios_fixup
)
1479 ppc_md
.pcibios_fixup();
1482 #ifdef CONFIG_HOTPLUG
1484 /* This is used by the PCI hotplug driver to allocate resource
1485 * of newly plugged busses. We can try to consolidate with the
1486 * rest of the code later, for now, keep it as-is as our main
1487 * resource allocation function doesn't deal with sub-trees yet.
1489 void pcibios_claim_one_bus(struct pci_bus
*bus
)
1491 struct pci_dev
*dev
;
1492 struct pci_bus
*child_bus
;
1494 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1497 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1498 struct resource
*r
= &dev
->resource
[i
];
1500 if (r
->parent
|| !r
->start
|| !r
->flags
)
1503 pr_debug("PCI: Claiming %s: "
1504 "Resource %d: %016llx..%016llx [%x]\n",
1506 (unsigned long long)r
->start
,
1507 (unsigned long long)r
->end
,
1508 (unsigned int)r
->flags
);
1510 pci_claim_resource(dev
, i
);
1514 list_for_each_entry(child_bus
, &bus
->children
, node
)
1515 pcibios_claim_one_bus(child_bus
);
1519 /* pcibios_finish_adding_to_bus
1521 * This is to be called by the hotplug code after devices have been
1522 * added to a bus, this include calling it for a PHB that is just
1525 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1527 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1528 pci_domain_nr(bus
), bus
->number
);
1530 /* Allocate bus and devices resources */
1531 pcibios_allocate_bus_resources(bus
);
1532 pcibios_claim_one_bus(bus
);
1534 /* Add new devices to global lists. Register in proc, sysfs. */
1535 pci_bus_add_devices(bus
);
1538 eeh_add_device_tree_late(bus
);
1540 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1542 #endif /* CONFIG_HOTPLUG */
1544 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1546 if (ppc_md
.pcibios_enable_device_hook
)
1547 if (ppc_md
.pcibios_enable_device_hook(dev
))
1550 return pci_enable_resources(dev
, mask
);
1553 static void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
, struct list_head
*resources
)
1555 struct resource
*res
;
1558 /* Hookup PHB IO resource */
1559 res
= &hose
->io_resource
;
1562 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1563 " bridge %s (domain %d)\n",
1564 hose
->dn
->full_name
, hose
->global_number
);
1566 /* Workaround for lack of IO resource only on 32-bit */
1567 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1568 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1569 res
->flags
= IORESOURCE_IO
;
1570 #endif /* CONFIG_PPC32 */
1573 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1574 (unsigned long long)res
->start
,
1575 (unsigned long long)res
->end
,
1576 (unsigned long)res
->flags
);
1577 pci_add_resource(resources
, res
);
1579 /* Hookup PHB Memory resources */
1580 for (i
= 0; i
< 3; ++i
) {
1581 res
= &hose
->mem_resources
[i
];
1585 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1586 "host bridge %s (domain %d)\n",
1587 hose
->dn
->full_name
, hose
->global_number
);
1589 /* Workaround for lack of MEM resource only on 32-bit */
1590 res
->start
= hose
->pci_mem_offset
;
1591 res
->end
= (resource_size_t
)-1LL;
1592 res
->flags
= IORESOURCE_MEM
;
1593 #endif /* CONFIG_PPC32 */
1596 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i
,
1597 (unsigned long long)res
->start
,
1598 (unsigned long long)res
->end
,
1599 (unsigned long)res
->flags
);
1600 pci_add_resource(resources
, res
);
1603 pr_debug("PCI: PHB MEM offset = %016llx\n",
1604 (unsigned long long)hose
->pci_mem_offset
);
1605 pr_debug("PCI: PHB IO offset = %08lx\n",
1606 (unsigned long)hose
->io_base_virt
- _IO_BASE
);
1611 * Null PCI config access functions, for the case when we can't
1614 #define NULL_PCI_OP(rw, size, type) \
1616 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1618 return PCIBIOS_DEVICE_NOT_FOUND; \
1622 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1625 return PCIBIOS_DEVICE_NOT_FOUND
;
1629 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1632 return PCIBIOS_DEVICE_NOT_FOUND
;
1635 static struct pci_ops null_pci_ops
=
1637 .read
= null_read_config
,
1638 .write
= null_write_config
,
1642 * These functions are used early on before PCI scanning is done
1643 * and all of the pci_dev and pci_bus structures have been created.
1645 static struct pci_bus
*
1646 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1648 static struct pci_bus bus
;
1651 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1655 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1659 #define EARLY_PCI_OP(rw, size, type) \
1660 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1661 int devfn, int offset, type value) \
1663 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1664 devfn, offset, value); \
1667 EARLY_PCI_OP(read
, byte
, u8
*)
1668 EARLY_PCI_OP(read
, word
, u16
*)
1669 EARLY_PCI_OP(read
, dword
, u32
*)
1670 EARLY_PCI_OP(write
, byte
, u8
)
1671 EARLY_PCI_OP(write
, word
, u16
)
1672 EARLY_PCI_OP(write
, dword
, u32
)
1674 extern int pci_bus_find_capability (struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1675 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1678 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);
1681 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
)
1683 struct pci_controller
*hose
= bus
->sysdata
;
1685 return of_node_get(hose
->dn
);
1689 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1690 * @hose: Pointer to the PCI host controller instance structure
1692 void __devinit
pcibios_scan_phb(struct pci_controller
*hose
)
1694 LIST_HEAD(resources
);
1695 struct pci_bus
*bus
;
1696 struct device_node
*node
= hose
->dn
;
1699 pr_debug("PCI: Scanning PHB %s\n",
1700 node
? node
->full_name
: "<NO NAME>");
1702 /* Get some IO space for the new PHB */
1703 pcibios_setup_phb_io_space(hose
);
1705 /* Wire up PHB bus resources */
1706 pcibios_setup_phb_resources(hose
, &resources
);
1708 /* Create an empty bus for the toplevel */
1709 bus
= pci_create_root_bus(hose
->parent
, hose
->first_busno
,
1710 hose
->ops
, hose
, &resources
);
1712 pr_err("Failed to create bus for PCI domain %04x\n",
1713 hose
->global_number
);
1714 pci_free_resource_list(&resources
);
1717 bus
->secondary
= hose
->first_busno
;
1720 /* Get probe mode and perform scan */
1721 mode
= PCI_PROBE_NORMAL
;
1722 if (node
&& ppc_md
.pci_probe_mode
)
1723 mode
= ppc_md
.pci_probe_mode(bus
);
1724 pr_debug(" probe mode: %d\n", mode
);
1725 if (mode
== PCI_PROBE_DEVTREE
) {
1726 bus
->subordinate
= hose
->last_busno
;
1727 of_scan_bus(node
, bus
);
1730 if (mode
== PCI_PROBE_NORMAL
)
1731 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
1733 /* Platform gets a chance to do some global fixups before
1734 * we proceed to resource allocation
1736 if (ppc_md
.pcibios_fixup_phb
)
1737 ppc_md
.pcibios_fixup_phb(hose
);
1739 /* Configure PCI Express settings */
1740 if (bus
&& !pci_has_flag(PCI_PROBE_ONLY
)) {
1741 struct pci_bus
*child
;
1742 list_for_each_entry(child
, &bus
->children
, node
) {
1743 struct pci_dev
*self
= child
->self
;
1746 pcie_bus_configure_settings(child
, self
->pcie_mpss
);
1751 static void fixup_hide_host_resource_fsl(struct pci_dev
*dev
)
1753 int i
, class = dev
->class >> 8;
1754 /* When configured as agent, programing interface = 1 */
1755 int prog_if
= dev
->class & 0xf;
1757 if ((class == PCI_CLASS_PROCESSOR_POWERPC
||
1758 class == PCI_CLASS_BRIDGE_OTHER
) &&
1759 (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) &&
1761 (dev
->bus
->parent
== NULL
)) {
1762 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1763 dev
->resource
[i
].start
= 0;
1764 dev
->resource
[i
].end
= 0;
1765 dev
->resource
[i
].flags
= 0;
1769 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA
, PCI_ANY_ID
, fixup_hide_host_resource_fsl
);
1770 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
, fixup_hide_host_resource_fsl
);