2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/prctl.h>
29 #include <linux/init_task.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/mqueue.h>
33 #include <linux/hardirq.h>
34 #include <linux/utsname.h>
35 #include <linux/ftrace.h>
36 #include <linux/kernel_stat.h>
37 #include <linux/personality.h>
38 #include <linux/random.h>
39 #include <linux/hw_breakpoint.h>
40 #include <linux/uaccess.h>
41 #include <linux/elf-randomize.h>
43 #include <asm/pgtable.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
58 #include <asm/code-patching.h>
60 #include <asm/livepatch.h>
61 #include <asm/cpu_has_feature.h>
62 #include <asm/asm-prototypes.h>
64 #include <linux/kprobes.h>
65 #include <linux/kdebug.h>
67 #ifdef CONFIG_CC_STACKPROTECTOR
68 #include <linux/stackprotector.h>
69 unsigned long __stack_chk_guard __read_mostly
;
70 EXPORT_SYMBOL(__stack_chk_guard
);
73 /* Transactional Memory debug */
75 #define TM_DEBUG(x...) printk(KERN_INFO x)
77 #define TM_DEBUG(x...) do { } while(0)
80 extern unsigned long _get_SP(void);
82 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
83 static void check_if_tm_restore_required(struct task_struct
*tsk
)
86 * If we are saving the current thread's registers, and the
87 * thread is in a transactional state, set the TIF_RESTORE_TM
88 * bit so that we know to restore the registers before
89 * returning to userspace.
91 if (tsk
== current
&& tsk
->thread
.regs
&&
92 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
93 !test_thread_flag(TIF_RESTORE_TM
)) {
94 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
95 set_thread_flag(TIF_RESTORE_TM
);
99 static inline bool msr_tm_active(unsigned long msr
)
101 return MSR_TM_ACTIVE(msr
);
104 static inline bool msr_tm_active(unsigned long msr
) { return false; }
105 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
106 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
108 bool strict_msr_control
;
109 EXPORT_SYMBOL(strict_msr_control
);
111 static int __init
enable_strict_msr_control(char *str
)
113 strict_msr_control
= true;
114 pr_info("Enabling strict facility control\n");
118 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
120 unsigned long msr_check_and_set(unsigned long bits
)
122 unsigned long oldmsr
= mfmsr();
123 unsigned long newmsr
;
125 newmsr
= oldmsr
| bits
;
128 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
132 if (oldmsr
!= newmsr
)
138 void __msr_check_and_clear(unsigned long bits
)
140 unsigned long oldmsr
= mfmsr();
141 unsigned long newmsr
;
143 newmsr
= oldmsr
& ~bits
;
146 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
150 if (oldmsr
!= newmsr
)
153 EXPORT_SYMBOL(__msr_check_and_clear
);
155 #ifdef CONFIG_PPC_FPU
156 void __giveup_fpu(struct task_struct
*tsk
)
161 msr
= tsk
->thread
.regs
->msr
;
164 if (cpu_has_feature(CPU_FTR_VSX
))
167 tsk
->thread
.regs
->msr
= msr
;
170 void giveup_fpu(struct task_struct
*tsk
)
172 check_if_tm_restore_required(tsk
);
174 msr_check_and_set(MSR_FP
);
176 msr_check_and_clear(MSR_FP
);
178 EXPORT_SYMBOL(giveup_fpu
);
181 * Make sure the floating-point register state in the
182 * the thread_struct is up to date for task tsk.
184 void flush_fp_to_thread(struct task_struct
*tsk
)
186 if (tsk
->thread
.regs
) {
188 * We need to disable preemption here because if we didn't,
189 * another process could get scheduled after the regs->msr
190 * test but before we have finished saving the FP registers
191 * to the thread_struct. That process could take over the
192 * FPU, and then when we get scheduled again we would store
193 * bogus values for the remaining FP registers.
196 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
198 * This should only ever be called for current or
199 * for a stopped child process. Since we save away
200 * the FP register state on context switch,
201 * there is something wrong if a stopped child appears
202 * to still have its FP state in the CPU registers.
204 BUG_ON(tsk
!= current
);
210 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
212 void enable_kernel_fp(void)
214 unsigned long cpumsr
;
216 WARN_ON(preemptible());
218 cpumsr
= msr_check_and_set(MSR_FP
);
220 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
221 check_if_tm_restore_required(current
);
223 * If a thread has already been reclaimed then the
224 * checkpointed registers are on the CPU but have definitely
225 * been saved by the reclaim code. Don't need to and *cannot*
226 * giveup as this would save to the 'live' structure not the
227 * checkpointed structure.
229 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
231 __giveup_fpu(current
);
234 EXPORT_SYMBOL(enable_kernel_fp
);
236 static int restore_fp(struct task_struct
*tsk
) {
237 if (tsk
->thread
.load_fp
|| msr_tm_active(tsk
->thread
.regs
->msr
)) {
238 load_fp_state(¤t
->thread
.fp_state
);
239 current
->thread
.load_fp
++;
245 static int restore_fp(struct task_struct
*tsk
) { return 0; }
246 #endif /* CONFIG_PPC_FPU */
248 #ifdef CONFIG_ALTIVEC
249 #define loadvec(thr) ((thr).load_vec)
251 static void __giveup_altivec(struct task_struct
*tsk
)
256 msr
= tsk
->thread
.regs
->msr
;
259 if (cpu_has_feature(CPU_FTR_VSX
))
262 tsk
->thread
.regs
->msr
= msr
;
265 void giveup_altivec(struct task_struct
*tsk
)
267 check_if_tm_restore_required(tsk
);
269 msr_check_and_set(MSR_VEC
);
270 __giveup_altivec(tsk
);
271 msr_check_and_clear(MSR_VEC
);
273 EXPORT_SYMBOL(giveup_altivec
);
275 void enable_kernel_altivec(void)
277 unsigned long cpumsr
;
279 WARN_ON(preemptible());
281 cpumsr
= msr_check_and_set(MSR_VEC
);
283 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
284 check_if_tm_restore_required(current
);
286 * If a thread has already been reclaimed then the
287 * checkpointed registers are on the CPU but have definitely
288 * been saved by the reclaim code. Don't need to and *cannot*
289 * giveup as this would save to the 'live' structure not the
290 * checkpointed structure.
292 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
294 __giveup_altivec(current
);
297 EXPORT_SYMBOL(enable_kernel_altivec
);
300 * Make sure the VMX/Altivec register state in the
301 * the thread_struct is up to date for task tsk.
303 void flush_altivec_to_thread(struct task_struct
*tsk
)
305 if (tsk
->thread
.regs
) {
307 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
308 BUG_ON(tsk
!= current
);
314 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
316 static int restore_altivec(struct task_struct
*tsk
)
318 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
319 (tsk
->thread
.load_vec
|| msr_tm_active(tsk
->thread
.regs
->msr
))) {
320 load_vr_state(&tsk
->thread
.vr_state
);
321 tsk
->thread
.used_vr
= 1;
322 tsk
->thread
.load_vec
++;
329 #define loadvec(thr) 0
330 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
331 #endif /* CONFIG_ALTIVEC */
334 static void __giveup_vsx(struct task_struct
*tsk
)
336 if (tsk
->thread
.regs
->msr
& MSR_FP
)
338 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
339 __giveup_altivec(tsk
);
340 tsk
->thread
.regs
->msr
&= ~MSR_VSX
;
343 static void giveup_vsx(struct task_struct
*tsk
)
345 check_if_tm_restore_required(tsk
);
347 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
349 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
352 static void save_vsx(struct task_struct
*tsk
)
354 if (tsk
->thread
.regs
->msr
& MSR_FP
)
356 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
360 void enable_kernel_vsx(void)
362 unsigned long cpumsr
;
364 WARN_ON(preemptible());
366 cpumsr
= msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
368 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VSX
)) {
369 check_if_tm_restore_required(current
);
371 * If a thread has already been reclaimed then the
372 * checkpointed registers are on the CPU but have definitely
373 * been saved by the reclaim code. Don't need to and *cannot*
374 * giveup as this would save to the 'live' structure not the
375 * checkpointed structure.
377 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
379 if (current
->thread
.regs
->msr
& MSR_FP
)
380 __giveup_fpu(current
);
381 if (current
->thread
.regs
->msr
& MSR_VEC
)
382 __giveup_altivec(current
);
383 __giveup_vsx(current
);
386 EXPORT_SYMBOL(enable_kernel_vsx
);
388 void flush_vsx_to_thread(struct task_struct
*tsk
)
390 if (tsk
->thread
.regs
) {
392 if (tsk
->thread
.regs
->msr
& MSR_VSX
) {
393 BUG_ON(tsk
!= current
);
399 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
401 static int restore_vsx(struct task_struct
*tsk
)
403 if (cpu_has_feature(CPU_FTR_VSX
)) {
404 tsk
->thread
.used_vsr
= 1;
411 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
412 static inline void save_vsx(struct task_struct
*tsk
) { }
413 #endif /* CONFIG_VSX */
416 void giveup_spe(struct task_struct
*tsk
)
418 check_if_tm_restore_required(tsk
);
420 msr_check_and_set(MSR_SPE
);
422 msr_check_and_clear(MSR_SPE
);
424 EXPORT_SYMBOL(giveup_spe
);
426 void enable_kernel_spe(void)
428 WARN_ON(preemptible());
430 msr_check_and_set(MSR_SPE
);
432 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
433 check_if_tm_restore_required(current
);
434 __giveup_spe(current
);
437 EXPORT_SYMBOL(enable_kernel_spe
);
439 void flush_spe_to_thread(struct task_struct
*tsk
)
441 if (tsk
->thread
.regs
) {
443 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
444 BUG_ON(tsk
!= current
);
445 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
451 #endif /* CONFIG_SPE */
453 static unsigned long msr_all_available
;
455 static int __init
init_msr_all_available(void)
457 #ifdef CONFIG_PPC_FPU
458 msr_all_available
|= MSR_FP
;
460 #ifdef CONFIG_ALTIVEC
461 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
462 msr_all_available
|= MSR_VEC
;
465 if (cpu_has_feature(CPU_FTR_VSX
))
466 msr_all_available
|= MSR_VSX
;
469 if (cpu_has_feature(CPU_FTR_SPE
))
470 msr_all_available
|= MSR_SPE
;
475 early_initcall(init_msr_all_available
);
477 void giveup_all(struct task_struct
*tsk
)
479 unsigned long usermsr
;
481 if (!tsk
->thread
.regs
)
484 usermsr
= tsk
->thread
.regs
->msr
;
486 if ((usermsr
& msr_all_available
) == 0)
489 msr_check_and_set(msr_all_available
);
490 check_if_tm_restore_required(tsk
);
492 #ifdef CONFIG_PPC_FPU
493 if (usermsr
& MSR_FP
)
496 #ifdef CONFIG_ALTIVEC
497 if (usermsr
& MSR_VEC
)
498 __giveup_altivec(tsk
);
501 if (usermsr
& MSR_VSX
)
505 if (usermsr
& MSR_SPE
)
509 msr_check_and_clear(msr_all_available
);
511 EXPORT_SYMBOL(giveup_all
);
513 void restore_math(struct pt_regs
*regs
)
517 if (!msr_tm_active(regs
->msr
) &&
518 !current
->thread
.load_fp
&& !loadvec(current
->thread
))
522 msr_check_and_set(msr_all_available
);
525 * Only reload if the bit is not set in the user MSR, the bit BEING set
526 * indicates that the registers are hot
528 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
529 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
531 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
534 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
535 restore_vsx(current
)) {
539 msr_check_and_clear(msr_all_available
);
544 void save_all(struct task_struct
*tsk
)
546 unsigned long usermsr
;
548 if (!tsk
->thread
.regs
)
551 usermsr
= tsk
->thread
.regs
->msr
;
553 if ((usermsr
& msr_all_available
) == 0)
556 msr_check_and_set(msr_all_available
);
559 * Saving the way the register space is in hardware, save_vsx boils
560 * down to a save_fpu() and save_altivec()
562 if (usermsr
& MSR_VSX
) {
565 if (usermsr
& MSR_FP
)
568 if (usermsr
& MSR_VEC
)
572 if (usermsr
& MSR_SPE
)
575 msr_check_and_clear(msr_all_available
);
578 void flush_all_to_thread(struct task_struct
*tsk
)
580 if (tsk
->thread
.regs
) {
582 BUG_ON(tsk
!= current
);
586 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
587 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
593 EXPORT_SYMBOL(flush_all_to_thread
);
595 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
596 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
597 unsigned long error_code
, int signal_code
, int breakpt
)
601 current
->thread
.trap_nr
= signal_code
;
602 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
603 11, SIGSEGV
) == NOTIFY_STOP
)
606 /* Deliver the signal to userspace */
607 info
.si_signo
= SIGTRAP
;
608 info
.si_errno
= breakpt
; /* breakpoint or watchpoint id */
609 info
.si_code
= signal_code
;
610 info
.si_addr
= (void __user
*)address
;
611 force_sig_info(SIGTRAP
, &info
, current
);
613 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
614 void do_break (struct pt_regs
*regs
, unsigned long address
,
615 unsigned long error_code
)
619 current
->thread
.trap_nr
= TRAP_HWBKPT
;
620 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
621 11, SIGSEGV
) == NOTIFY_STOP
)
624 if (debugger_break_match(regs
))
627 /* Clear the breakpoint */
628 hw_breakpoint_disable();
630 /* Deliver the signal to userspace */
631 info
.si_signo
= SIGTRAP
;
633 info
.si_code
= TRAP_HWBKPT
;
634 info
.si_addr
= (void __user
*)address
;
635 force_sig_info(SIGTRAP
, &info
, current
);
637 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
639 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
641 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
643 * Set the debug registers back to their default "safe" values.
645 static void set_debug_reg_defaults(struct thread_struct
*thread
)
647 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
648 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
649 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
651 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
652 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
653 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
655 thread
->debug
.dbcr0
= 0;
658 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
660 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
661 DBCR1_IAC3US
| DBCR1_IAC4US
;
663 * Force Data Address Compare User/Supervisor bits to be User-only
664 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
666 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
668 thread
->debug
.dbcr1
= 0;
672 static void prime_debug_regs(struct debug_reg
*debug
)
675 * We could have inherited MSR_DE from userspace, since
676 * it doesn't get cleared on exception entry. Make sure
677 * MSR_DE is clear before we enable any debug events.
679 mtmsr(mfmsr() & ~MSR_DE
);
681 mtspr(SPRN_IAC1
, debug
->iac1
);
682 mtspr(SPRN_IAC2
, debug
->iac2
);
683 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
684 mtspr(SPRN_IAC3
, debug
->iac3
);
685 mtspr(SPRN_IAC4
, debug
->iac4
);
687 mtspr(SPRN_DAC1
, debug
->dac1
);
688 mtspr(SPRN_DAC2
, debug
->dac2
);
689 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
690 mtspr(SPRN_DVC1
, debug
->dvc1
);
691 mtspr(SPRN_DVC2
, debug
->dvc2
);
693 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
694 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
696 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
700 * Unless neither the old or new thread are making use of the
701 * debug registers, set the debug registers from the values
702 * stored in the new thread.
704 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
706 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
707 || (new_debug
->dbcr0
& DBCR0_IDM
))
708 prime_debug_regs(new_debug
);
710 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
711 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
712 #ifndef CONFIG_HAVE_HW_BREAKPOINT
713 static void set_debug_reg_defaults(struct thread_struct
*thread
)
715 thread
->hw_brk
.address
= 0;
716 thread
->hw_brk
.type
= 0;
717 set_breakpoint(&thread
->hw_brk
);
719 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
720 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
722 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
723 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
725 mtspr(SPRN_DAC1
, dabr
);
726 #ifdef CONFIG_PPC_47x
731 #elif defined(CONFIG_PPC_BOOK3S)
732 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
734 mtspr(SPRN_DABR
, dabr
);
735 if (cpu_has_feature(CPU_FTR_DABRX
))
736 mtspr(SPRN_DABRX
, dabrx
);
740 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
746 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
748 unsigned long dabr
, dabrx
;
750 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
751 dabrx
= ((brk
->type
>> 3) & 0x7);
754 return ppc_md
.set_dabr(dabr
, dabrx
);
756 return __set_dabr(dabr
, dabrx
);
759 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
761 unsigned long dawr
, dawrx
, mrd
;
765 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
766 << (63 - 58); //* read/write bits */
767 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
768 << (63 - 59); //* translate */
769 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
770 >> 3; //* PRIM bits */
771 /* dawr length is stored in field MDR bits 48:53. Matches range in
772 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
774 brk->len is in bytes.
775 This aligns up to double word size, shifts and does the bias.
777 mrd
= ((brk
->len
+ 7) >> 3) - 1;
778 dawrx
|= (mrd
& 0x3f) << (63 - 53);
781 return ppc_md
.set_dawr(dawr
, dawrx
);
782 mtspr(SPRN_DAWR
, dawr
);
783 mtspr(SPRN_DAWRX
, dawrx
);
787 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
789 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
791 if (cpu_has_feature(CPU_FTR_DAWR
))
797 void set_breakpoint(struct arch_hw_breakpoint
*brk
)
800 __set_breakpoint(brk
);
805 DEFINE_PER_CPU(struct cpu_usage
, cpu_usage_array
);
808 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
809 struct arch_hw_breakpoint
*b
)
811 if (a
->address
!= b
->address
)
813 if (a
->type
!= b
->type
)
815 if (a
->len
!= b
->len
)
820 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
822 static inline bool tm_enabled(struct task_struct
*tsk
)
824 return tsk
&& tsk
->thread
.regs
&& (tsk
->thread
.regs
->msr
& MSR_TM
);
827 static void tm_reclaim_thread(struct thread_struct
*thr
,
828 struct thread_info
*ti
, uint8_t cause
)
831 * Use the current MSR TM suspended bit to track if we have
832 * checkpointed state outstanding.
833 * On signal delivery, we'd normally reclaim the checkpointed
834 * state to obtain stack pointer (see:get_tm_stackpointer()).
835 * This will then directly return to userspace without going
836 * through __switch_to(). However, if the stack frame is bad,
837 * we need to exit this thread which calls __switch_to() which
838 * will again attempt to reclaim the already saved tm state.
839 * Hence we need to check that we've not already reclaimed
841 * We do this using the current MSR, rather tracking it in
842 * some specific thread_struct bit, as it has the additional
843 * benefit of checking for a potential TM bad thing exception.
845 if (!MSR_TM_SUSPENDED(mfmsr()))
848 giveup_all(container_of(thr
, struct task_struct
, thread
));
850 tm_reclaim(thr
, thr
->ckpt_regs
.msr
, cause
);
853 void tm_reclaim_current(uint8_t cause
)
856 tm_reclaim_thread(¤t
->thread
, current_thread_info(), cause
);
859 static inline void tm_reclaim_task(struct task_struct
*tsk
)
861 /* We have to work out if we're switching from/to a task that's in the
862 * middle of a transaction.
864 * In switching we need to maintain a 2nd register state as
865 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
866 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
869 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
871 struct thread_struct
*thr
= &tsk
->thread
;
876 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
877 goto out_and_saveregs
;
879 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
880 "ccr=%lx, msr=%lx, trap=%lx)\n",
881 tsk
->pid
, thr
->regs
->nip
,
882 thr
->regs
->ccr
, thr
->regs
->msr
,
885 tm_reclaim_thread(thr
, task_thread_info(tsk
), TM_CAUSE_RESCHED
);
887 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
891 /* Always save the regs here, even if a transaction's not active.
892 * This context-switches a thread's TM info SPRs. We do it here to
893 * be consistent with the restore path (in recheckpoint) which
894 * cannot happen later in _switch().
899 extern void __tm_recheckpoint(struct thread_struct
*thread
,
900 unsigned long orig_msr
);
902 void tm_recheckpoint(struct thread_struct
*thread
,
903 unsigned long orig_msr
)
907 if (!(thread
->regs
->msr
& MSR_TM
))
910 /* We really can't be interrupted here as the TEXASR registers can't
911 * change and later in the trecheckpoint code, we have a userspace R1.
912 * So let's hard disable over this region.
914 local_irq_save(flags
);
917 /* The TM SPRs are restored here, so that TEXASR.FS can be set
918 * before the trecheckpoint and no explosion occurs.
920 tm_restore_sprs(thread
);
922 __tm_recheckpoint(thread
, orig_msr
);
924 local_irq_restore(flags
);
927 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
931 if (!cpu_has_feature(CPU_FTR_TM
))
934 /* Recheckpoint the registers of the thread we're about to switch to.
936 * If the task was using FP, we non-lazily reload both the original and
937 * the speculative FP register states. This is because the kernel
938 * doesn't see if/when a TM rollback occurs, so if we take an FP
939 * unavailable later, we are unable to determine which set of FP regs
940 * need to be restored.
942 if (!tm_enabled(new))
945 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
946 tm_restore_sprs(&new->thread
);
949 msr
= new->thread
.ckpt_regs
.msr
;
950 /* Recheckpoint to restore original checkpointed register state. */
951 TM_DEBUG("*** tm_recheckpoint of pid %d "
952 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
953 new->pid
, new->thread
.regs
->msr
, msr
);
955 tm_recheckpoint(&new->thread
, msr
);
958 * The checkpointed state has been restored but the live state has
959 * not, ensure all the math functionality is turned off to trigger
960 * restore_math() to reload.
962 new->thread
.regs
->msr
&= ~(MSR_FP
| MSR_VEC
| MSR_VSX
);
964 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
965 "(kernel msr 0x%lx)\n",
969 static inline void __switch_to_tm(struct task_struct
*prev
,
970 struct task_struct
*new)
972 if (cpu_has_feature(CPU_FTR_TM
)) {
973 if (tm_enabled(prev
) || tm_enabled(new))
976 if (tm_enabled(prev
)) {
977 prev
->thread
.load_tm
++;
978 tm_reclaim_task(prev
);
979 if (!MSR_TM_ACTIVE(prev
->thread
.regs
->msr
) && prev
->thread
.load_tm
== 0)
980 prev
->thread
.regs
->msr
&= ~MSR_TM
;
983 tm_recheckpoint_new_task(new);
988 * This is called if we are on the way out to userspace and the
989 * TIF_RESTORE_TM flag is set. It checks if we need to reload
990 * FP and/or vector state and does so if necessary.
991 * If userspace is inside a transaction (whether active or
992 * suspended) and FP/VMX/VSX instructions have ever been enabled
993 * inside that transaction, then we have to keep them enabled
994 * and keep the FP/VMX/VSX state loaded while ever the transaction
995 * continues. The reason is that if we didn't, and subsequently
996 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
997 * we don't know whether it's the same transaction, and thus we
998 * don't know which of the checkpointed state and the transactional
1001 void restore_tm_state(struct pt_regs
*regs
)
1003 unsigned long msr_diff
;
1006 * This is the only moment we should clear TIF_RESTORE_TM as
1007 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1008 * again, anything else could lead to an incorrect ckpt_msr being
1009 * saved and therefore incorrect signal contexts.
1011 clear_thread_flag(TIF_RESTORE_TM
);
1012 if (!MSR_TM_ACTIVE(regs
->msr
))
1015 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
1016 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
1018 /* Ensure that restore_math() will restore */
1019 if (msr_diff
& MSR_FP
)
1020 current
->thread
.load_fp
= 1;
1021 #ifdef CONFIG_ALTIVEC
1022 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && msr_diff
& MSR_VEC
)
1023 current
->thread
.load_vec
= 1;
1027 regs
->msr
|= msr_diff
;
1031 #define tm_recheckpoint_new_task(new)
1032 #define __switch_to_tm(prev, new)
1033 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1035 static inline void save_sprs(struct thread_struct
*t
)
1037 #ifdef CONFIG_ALTIVEC
1038 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
1039 t
->vrsave
= mfspr(SPRN_VRSAVE
);
1041 #ifdef CONFIG_PPC_BOOK3S_64
1042 if (cpu_has_feature(CPU_FTR_DSCR
))
1043 t
->dscr
= mfspr(SPRN_DSCR
);
1045 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1046 t
->bescr
= mfspr(SPRN_BESCR
);
1047 t
->ebbhr
= mfspr(SPRN_EBBHR
);
1048 t
->ebbrr
= mfspr(SPRN_EBBRR
);
1050 t
->fscr
= mfspr(SPRN_FSCR
);
1053 * Note that the TAR is not available for use in the kernel.
1054 * (To provide this, the TAR should be backed up/restored on
1055 * exception entry/exit instead, and be in pt_regs. FIXME,
1056 * this should be in pt_regs anyway (for debug).)
1058 t
->tar
= mfspr(SPRN_TAR
);
1063 static inline void restore_sprs(struct thread_struct
*old_thread
,
1064 struct thread_struct
*new_thread
)
1066 #ifdef CONFIG_ALTIVEC
1067 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
1068 old_thread
->vrsave
!= new_thread
->vrsave
)
1069 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
1071 #ifdef CONFIG_PPC_BOOK3S_64
1072 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1073 u64 dscr
= get_paca()->dscr_default
;
1074 if (new_thread
->dscr_inherit
)
1075 dscr
= new_thread
->dscr
;
1077 if (old_thread
->dscr
!= dscr
)
1078 mtspr(SPRN_DSCR
, dscr
);
1081 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1082 if (old_thread
->bescr
!= new_thread
->bescr
)
1083 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1084 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1085 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1086 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1087 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1089 if (old_thread
->fscr
!= new_thread
->fscr
)
1090 mtspr(SPRN_FSCR
, new_thread
->fscr
);
1092 if (old_thread
->tar
!= new_thread
->tar
)
1093 mtspr(SPRN_TAR
, new_thread
->tar
);
1098 struct task_struct
*__switch_to(struct task_struct
*prev
,
1099 struct task_struct
*new)
1101 struct thread_struct
*new_thread
, *old_thread
;
1102 struct task_struct
*last
;
1103 #ifdef CONFIG_PPC_BOOK3S_64
1104 struct ppc64_tlb_batch
*batch
;
1107 new_thread
= &new->thread
;
1108 old_thread
= ¤t
->thread
;
1110 WARN_ON(!irqs_disabled());
1114 * Collect processor utilization data per process
1116 if (firmware_has_feature(FW_FEATURE_SPLPAR
)) {
1117 struct cpu_usage
*cu
= this_cpu_ptr(&cpu_usage_array
);
1118 long unsigned start_tb
, current_tb
;
1119 start_tb
= old_thread
->start_tb
;
1120 cu
->current_tb
= current_tb
= mfspr(SPRN_PURR
);
1121 old_thread
->accum_tb
+= (current_tb
- start_tb
);
1122 new_thread
->start_tb
= current_tb
;
1124 #endif /* CONFIG_PPC64 */
1126 #ifdef CONFIG_PPC_STD_MMU_64
1127 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1128 if (batch
->active
) {
1129 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1131 __flush_tlb_pending(batch
);
1134 #endif /* CONFIG_PPC_STD_MMU_64 */
1136 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1137 switch_booke_debug_regs(&new->thread
.debug
);
1140 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1143 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1144 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1145 __set_breakpoint(&new->thread
.hw_brk
);
1146 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1150 * We need to save SPRs before treclaim/trecheckpoint as these will
1151 * change a number of them.
1153 save_sprs(&prev
->thread
);
1155 /* Save FPU, Altivec, VSX and SPE state */
1158 __switch_to_tm(prev
, new);
1161 * We can't take a PMU exception inside _switch() since there is a
1162 * window where the kernel stack SLB and the kernel stack are out
1163 * of sync. Hard disable here.
1168 * Call restore_sprs() before calling _switch(). If we move it after
1169 * _switch() then we miss out on calling it for new tasks. The reason
1170 * for this is we manually create a stack frame for new tasks that
1171 * directly returns through ret_from_fork() or
1172 * ret_from_kernel_thread(). See copy_thread() for details.
1174 restore_sprs(old_thread
, new_thread
);
1176 last
= _switch(old_thread
, new_thread
);
1178 #ifdef CONFIG_PPC_STD_MMU_64
1179 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1180 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1181 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1185 if (current_thread_info()->task
->thread
.regs
)
1186 restore_math(current_thread_info()->task
->thread
.regs
);
1187 #endif /* CONFIG_PPC_STD_MMU_64 */
1192 static int instructions_to_print
= 16;
1194 static void show_instructions(struct pt_regs
*regs
)
1197 unsigned long pc
= regs
->nip
- (instructions_to_print
* 3 / 4 *
1200 printk("Instruction dump:");
1202 for (i
= 0; i
< instructions_to_print
; i
++) {
1208 #if !defined(CONFIG_BOOKE)
1209 /* If executing with the IMMU off, adjust pc rather
1210 * than print XXXXXXXX.
1212 if (!(regs
->msr
& MSR_IR
))
1213 pc
= (unsigned long)phys_to_virt(pc
);
1216 if (!__kernel_text_address(pc
) ||
1217 probe_kernel_address((unsigned int __user
*)pc
, instr
)) {
1218 pr_cont("XXXXXXXX ");
1220 if (regs
->nip
== pc
)
1221 pr_cont("<%08x> ", instr
);
1223 pr_cont("%08x ", instr
);
1237 static struct regbit msr_bits
[] = {
1238 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1260 #ifndef CONFIG_BOOKE
1267 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1271 for (; bits
->bit
; ++bits
)
1272 if (val
& bits
->bit
) {
1273 pr_cont("%s%s", s
, bits
->name
);
1278 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1279 static struct regbit msr_tm_bits
[] = {
1286 static void print_tm_bits(unsigned long val
)
1289 * This only prints something if at least one of the TM bit is set.
1290 * Inside the TM[], the output means:
1291 * E: Enabled (bit 32)
1292 * S: Suspended (bit 33)
1293 * T: Transactional (bit 34)
1295 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1297 print_bits(val
, msr_tm_bits
, "");
1302 static void print_tm_bits(unsigned long val
) {}
1305 static void print_msr_bits(unsigned long val
)
1308 print_bits(val
, msr_bits
, ",");
1314 #define REG "%016lx"
1315 #define REGS_PER_LINE 4
1316 #define LAST_VOLATILE 13
1319 #define REGS_PER_LINE 8
1320 #define LAST_VOLATILE 12
1323 void show_regs(struct pt_regs
* regs
)
1327 show_regs_print_info(KERN_DEFAULT
);
1329 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1330 regs
->nip
, regs
->link
, regs
->ctr
);
1331 printk("REGS: %p TRAP: %04lx %s (%s)\n",
1332 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1333 printk("MSR: "REG
" ", regs
->msr
);
1334 print_msr_bits(regs
->msr
);
1335 printk(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1337 if ((regs
->trap
!= 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1338 pr_cont("CFAR: "REG
" ", regs
->orig_gpr3
);
1339 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1340 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1341 pr_cont("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1343 pr_cont("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1346 pr_cont("SOFTE: %ld ", regs
->softe
);
1348 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1349 if (MSR_TM_ACTIVE(regs
->msr
))
1350 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1353 for (i
= 0; i
< 32; i
++) {
1354 if ((i
% REGS_PER_LINE
) == 0)
1355 pr_cont("\nGPR%02d: ", i
);
1356 pr_cont(REG
" ", regs
->gpr
[i
]);
1357 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1361 #ifdef CONFIG_KALLSYMS
1363 * Lookup NIP late so we have the best change of getting the
1364 * above info out without failing
1366 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1367 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1369 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1370 if (!user_mode(regs
))
1371 show_instructions(regs
);
1374 void flush_thread(void)
1376 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1377 flush_ptrace_hw_breakpoint(current
);
1378 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1379 set_debug_reg_defaults(¤t
->thread
);
1380 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1384 release_thread(struct task_struct
*t
)
1389 * this gets called so that we can store coprocessor state into memory and
1390 * copy the current task into the new thread.
1392 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1394 flush_all_to_thread(src
);
1396 * Flush TM state out so we can copy it. __switch_to_tm() does this
1397 * flush but it removes the checkpointed state from the current CPU and
1398 * transitions the CPU out of TM mode. Hence we need to call
1399 * tm_recheckpoint_new_task() (on the same task) to restore the
1400 * checkpointed state back and the TM mode.
1402 * Can't pass dst because it isn't ready. Doesn't matter, passing
1403 * dst is only important for __switch_to()
1405 __switch_to_tm(src
, src
);
1409 clear_task_ebb(dst
);
1414 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1416 #ifdef CONFIG_PPC_STD_MMU_64
1417 unsigned long sp_vsid
;
1418 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1420 if (radix_enabled())
1423 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1424 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1425 << SLB_VSID_SHIFT_1T
;
1427 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1429 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1430 p
->thread
.ksp_vsid
= sp_vsid
;
1439 * Copy architecture-specific thread state
1441 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1442 unsigned long kthread_arg
, struct task_struct
*p
)
1444 struct pt_regs
*childregs
, *kregs
;
1445 extern void ret_from_fork(void);
1446 extern void ret_from_kernel_thread(void);
1448 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1449 struct thread_info
*ti
= task_thread_info(p
);
1451 klp_init_thread_info(ti
);
1453 /* Copy registers */
1454 sp
-= sizeof(struct pt_regs
);
1455 childregs
= (struct pt_regs
*) sp
;
1456 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1458 memset(childregs
, 0, sizeof(struct pt_regs
));
1459 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1462 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1464 clear_tsk_thread_flag(p
, TIF_32BIT
);
1465 childregs
->softe
= 1;
1467 childregs
->gpr
[15] = kthread_arg
;
1468 p
->thread
.regs
= NULL
; /* no user register state */
1469 ti
->flags
|= _TIF_RESTOREALL
;
1470 f
= ret_from_kernel_thread
;
1473 struct pt_regs
*regs
= current_pt_regs();
1474 CHECK_FULL_REGS(regs
);
1477 childregs
->gpr
[1] = usp
;
1478 p
->thread
.regs
= childregs
;
1479 childregs
->gpr
[3] = 0; /* Result from fork() */
1480 if (clone_flags
& CLONE_SETTLS
) {
1482 if (!is_32bit_task())
1483 childregs
->gpr
[13] = childregs
->gpr
[6];
1486 childregs
->gpr
[2] = childregs
->gpr
[6];
1491 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1492 sp
-= STACK_FRAME_OVERHEAD
;
1495 * The way this works is that at some point in the future
1496 * some task will call _switch to switch to the new task.
1497 * That will pop off the stack frame created below and start
1498 * the new task running at ret_from_fork. The new task will
1499 * do some house keeping and then return from the fork or clone
1500 * system call, using the stack frame created above.
1502 ((unsigned long *)sp
)[0] = 0;
1503 sp
-= sizeof(struct pt_regs
);
1504 kregs
= (struct pt_regs
*) sp
;
1505 sp
-= STACK_FRAME_OVERHEAD
;
1508 p
->thread
.ksp_limit
= (unsigned long)task_stack_page(p
) +
1509 _ALIGN_UP(sizeof(struct thread_info
), 16);
1511 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1512 p
->thread
.ptrace_bps
[0] = NULL
;
1515 p
->thread
.fp_save_area
= NULL
;
1516 #ifdef CONFIG_ALTIVEC
1517 p
->thread
.vr_save_area
= NULL
;
1520 setup_ksp_vsid(p
, sp
);
1523 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1524 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1525 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1527 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1528 p
->thread
.ppr
= INIT_PPR
;
1530 kregs
->nip
= ppc_function_entry(f
);
1535 * Set up a thread for executing a new program
1537 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1540 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1544 * If we exec out of a kernel thread then thread.regs will not be
1547 if (!current
->thread
.regs
) {
1548 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1549 current
->thread
.regs
= regs
- 1;
1552 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1554 * Clear any transactional state, we're exec()ing. The cause is
1555 * not important as there will never be a recheckpoint so it's not
1558 if (MSR_TM_SUSPENDED(mfmsr()))
1559 tm_reclaim_current(0);
1562 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1570 * We have just cleared all the nonvolatile GPRs, so make
1571 * FULL_REGS(regs) return true. This is necessary to allow
1572 * ptrace to examine the thread immediately after exec.
1579 regs
->msr
= MSR_USER
;
1581 if (!is_32bit_task()) {
1582 unsigned long entry
;
1584 if (is_elf2_task()) {
1585 /* Look ma, no function descriptors! */
1590 * The latest iteration of the ABI requires that when
1591 * calling a function (at its global entry point),
1592 * the caller must ensure r12 holds the entry point
1593 * address (so that the function can quickly
1594 * establish addressability).
1596 regs
->gpr
[12] = start
;
1597 /* Make sure that's restored on entry to userspace. */
1598 set_thread_flag(TIF_RESTOREALL
);
1602 /* start is a relocated pointer to the function
1603 * descriptor for the elf _start routine. The first
1604 * entry in the function descriptor is the entry
1605 * address of _start and the second entry is the TOC
1606 * value we need to use.
1608 __get_user(entry
, (unsigned long __user
*)start
);
1609 __get_user(toc
, (unsigned long __user
*)start
+1);
1611 /* Check whether the e_entry function descriptor entries
1612 * need to be relocated before we can use them.
1614 if (load_addr
!= 0) {
1621 regs
->msr
= MSR_USER64
;
1625 regs
->msr
= MSR_USER32
;
1629 current
->thread
.used_vsr
= 0;
1631 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1632 current
->thread
.fp_save_area
= NULL
;
1633 #ifdef CONFIG_ALTIVEC
1634 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1635 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1636 current
->thread
.vr_save_area
= NULL
;
1637 current
->thread
.vrsave
= 0;
1638 current
->thread
.used_vr
= 0;
1639 #endif /* CONFIG_ALTIVEC */
1641 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1642 current
->thread
.acc
= 0;
1643 current
->thread
.spefscr
= 0;
1644 current
->thread
.used_spe
= 0;
1645 #endif /* CONFIG_SPE */
1646 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1647 current
->thread
.tm_tfhar
= 0;
1648 current
->thread
.tm_texasr
= 0;
1649 current
->thread
.tm_tfiar
= 0;
1650 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1652 EXPORT_SYMBOL(start_thread
);
1654 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1655 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1657 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1659 struct pt_regs
*regs
= tsk
->thread
.regs
;
1661 /* This is a bit hairy. If we are an SPE enabled processor
1662 * (have embedded fp) we store the IEEE exception enable flags in
1663 * fpexc_mode. fpexc_mode is also used for setting FP exception
1664 * mode (asyn, precise, disabled) for 'Classic' FP. */
1665 if (val
& PR_FP_EXC_SW_ENABLE
) {
1667 if (cpu_has_feature(CPU_FTR_SPE
)) {
1669 * When the sticky exception bits are set
1670 * directly by userspace, it must call prctl
1671 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1672 * in the existing prctl settings) or
1673 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1674 * the bits being set). <fenv.h> functions
1675 * saving and restoring the whole
1676 * floating-point environment need to do so
1677 * anyway to restore the prctl settings from
1678 * the saved environment.
1680 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1681 tsk
->thread
.fpexc_mode
= val
&
1682 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1692 /* on a CONFIG_SPE this does not hurt us. The bits that
1693 * __pack_fe01 use do not overlap with bits used for
1694 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1695 * on CONFIG_SPE implementations are reserved so writing to
1696 * them does not change anything */
1697 if (val
> PR_FP_EXC_PRECISE
)
1699 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1700 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1701 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1702 | tsk
->thread
.fpexc_mode
;
1706 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1710 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1712 if (cpu_has_feature(CPU_FTR_SPE
)) {
1714 * When the sticky exception bits are set
1715 * directly by userspace, it must call prctl
1716 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1717 * in the existing prctl settings) or
1718 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1719 * the bits being set). <fenv.h> functions
1720 * saving and restoring the whole
1721 * floating-point environment need to do so
1722 * anyway to restore the prctl settings from
1723 * the saved environment.
1725 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1726 val
= tsk
->thread
.fpexc_mode
;
1733 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1734 return put_user(val
, (unsigned int __user
*) adr
);
1737 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1739 struct pt_regs
*regs
= tsk
->thread
.regs
;
1741 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1742 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1748 if (val
== PR_ENDIAN_BIG
)
1749 regs
->msr
&= ~MSR_LE
;
1750 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1751 regs
->msr
|= MSR_LE
;
1758 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1760 struct pt_regs
*regs
= tsk
->thread
.regs
;
1763 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1764 !cpu_has_feature(CPU_FTR_REAL_LE
))
1770 if (regs
->msr
& MSR_LE
) {
1771 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1772 val
= PR_ENDIAN_LITTLE
;
1774 val
= PR_ENDIAN_PPC_LITTLE
;
1776 val
= PR_ENDIAN_BIG
;
1778 return put_user(val
, (unsigned int __user
*)adr
);
1781 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1783 tsk
->thread
.align_ctl
= val
;
1787 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1789 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1792 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1793 unsigned long nbytes
)
1795 unsigned long stack_page
;
1796 unsigned long cpu
= task_cpu(p
);
1799 * Avoid crashing if the stack has overflowed and corrupted
1800 * task_cpu(p), which is in the thread_info struct.
1802 if (cpu
< NR_CPUS
&& cpu_possible(cpu
)) {
1803 stack_page
= (unsigned long) hardirq_ctx
[cpu
];
1804 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1805 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1808 stack_page
= (unsigned long) softirq_ctx
[cpu
];
1809 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1810 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1816 int validate_sp(unsigned long sp
, struct task_struct
*p
,
1817 unsigned long nbytes
)
1819 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
1821 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1822 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1825 return valid_irq_stack(sp
, p
, nbytes
);
1828 EXPORT_SYMBOL(validate_sp
);
1830 unsigned long get_wchan(struct task_struct
*p
)
1832 unsigned long ip
, sp
;
1835 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
1839 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1843 sp
= *(unsigned long *)sp
;
1844 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1847 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
1848 if (!in_sched_functions(ip
))
1851 } while (count
++ < 16);
1855 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
1857 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
1859 unsigned long sp
, ip
, lr
, newsp
;
1862 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1863 int curr_frame
= current
->curr_ret_stack
;
1864 extern void return_to_handler(void);
1865 unsigned long rth
= (unsigned long)return_to_handler
;
1868 sp
= (unsigned long) stack
;
1873 sp
= current_stack_pointer();
1875 sp
= tsk
->thread
.ksp
;
1879 printk("Call Trace:\n");
1881 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
1884 stack
= (unsigned long *) sp
;
1886 ip
= stack
[STACK_FRAME_LR_SAVE
];
1887 if (!firstframe
|| ip
!= lr
) {
1888 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
1889 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1890 if ((ip
== rth
) && curr_frame
>= 0) {
1892 (void *)current
->ret_stack
[curr_frame
].ret
);
1897 pr_cont(" (unreliable)");
1903 * See if this is an exception frame.
1904 * We look for the "regshere" marker in the current frame.
1906 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
1907 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
1908 struct pt_regs
*regs
= (struct pt_regs
*)
1909 (sp
+ STACK_FRAME_OVERHEAD
);
1911 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
1912 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
1917 } while (count
++ < kstack_depth_to_print
);
1921 /* Called with hard IRQs off */
1922 void notrace
__ppc64_runlatch_on(void)
1924 struct thread_info
*ti
= current_thread_info();
1927 ctrl
= mfspr(SPRN_CTRLF
);
1928 ctrl
|= CTRL_RUNLATCH
;
1929 mtspr(SPRN_CTRLT
, ctrl
);
1931 ti
->local_flags
|= _TLF_RUNLATCH
;
1934 /* Called with hard IRQs off */
1935 void notrace
__ppc64_runlatch_off(void)
1937 struct thread_info
*ti
= current_thread_info();
1940 ti
->local_flags
&= ~_TLF_RUNLATCH
;
1942 ctrl
= mfspr(SPRN_CTRLF
);
1943 ctrl
&= ~CTRL_RUNLATCH
;
1944 mtspr(SPRN_CTRLT
, ctrl
);
1946 #endif /* CONFIG_PPC64 */
1948 unsigned long arch_align_stack(unsigned long sp
)
1950 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
1951 sp
-= get_random_int() & ~PAGE_MASK
;
1955 static inline unsigned long brk_rnd(void)
1957 unsigned long rnd
= 0;
1959 /* 8MB for 32bit, 1GB for 64bit */
1960 if (is_32bit_task())
1961 rnd
= (get_random_long() % (1UL<<(23-PAGE_SHIFT
)));
1963 rnd
= (get_random_long() % (1UL<<(30-PAGE_SHIFT
)));
1965 return rnd
<< PAGE_SHIFT
;
1968 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
1970 unsigned long base
= mm
->brk
;
1973 #ifdef CONFIG_PPC_STD_MMU_64
1975 * If we are using 1TB segments and we are allowed to randomise
1976 * the heap, we can put it above 1TB so it is backed by a 1TB
1977 * segment. Otherwise the heap will be in the bottom 1TB
1978 * which always uses 256MB segments and this may result in a
1979 * performance penalty. We don't need to worry about radix. For
1980 * radix, mmu_highuser_ssize remains unchanged from 256MB.
1982 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
1983 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
1986 ret
= PAGE_ALIGN(base
+ brk_rnd());