2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/prctl.h>
29 #include <linux/init_task.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/mqueue.h>
33 #include <linux/hardirq.h>
34 #include <linux/utsname.h>
35 #include <linux/ftrace.h>
36 #include <linux/kernel_stat.h>
37 #include <linux/personality.h>
38 #include <linux/random.h>
39 #include <linux/hw_breakpoint.h>
40 #include <linux/uaccess.h>
41 #include <linux/elf-randomize.h>
43 #include <asm/pgtable.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
58 #include <asm/code-patching.h>
60 #include <asm/livepatch.h>
61 #include <asm/cpu_has_feature.h>
62 #include <asm/asm-prototypes.h>
64 #include <linux/kprobes.h>
65 #include <linux/kdebug.h>
67 /* Transactional Memory debug */
69 #define TM_DEBUG(x...) printk(KERN_INFO x)
71 #define TM_DEBUG(x...) do { } while(0)
74 extern unsigned long _get_SP(void);
76 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
77 static void check_if_tm_restore_required(struct task_struct
*tsk
)
80 * If we are saving the current thread's registers, and the
81 * thread is in a transactional state, set the TIF_RESTORE_TM
82 * bit so that we know to restore the registers before
83 * returning to userspace.
85 if (tsk
== current
&& tsk
->thread
.regs
&&
86 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
87 !test_thread_flag(TIF_RESTORE_TM
)) {
88 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
89 set_thread_flag(TIF_RESTORE_TM
);
93 static inline bool msr_tm_active(unsigned long msr
)
95 return MSR_TM_ACTIVE(msr
);
98 static inline bool msr_tm_active(unsigned long msr
) { return false; }
99 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
100 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
102 bool strict_msr_control
;
103 EXPORT_SYMBOL(strict_msr_control
);
105 static int __init
enable_strict_msr_control(char *str
)
107 strict_msr_control
= true;
108 pr_info("Enabling strict facility control\n");
112 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
114 void msr_check_and_set(unsigned long bits
)
116 unsigned long oldmsr
= mfmsr();
117 unsigned long newmsr
;
119 newmsr
= oldmsr
| bits
;
122 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
126 if (oldmsr
!= newmsr
)
130 void __msr_check_and_clear(unsigned long bits
)
132 unsigned long oldmsr
= mfmsr();
133 unsigned long newmsr
;
135 newmsr
= oldmsr
& ~bits
;
138 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
142 if (oldmsr
!= newmsr
)
145 EXPORT_SYMBOL(__msr_check_and_clear
);
147 #ifdef CONFIG_PPC_FPU
148 void __giveup_fpu(struct task_struct
*tsk
)
153 msr
= tsk
->thread
.regs
->msr
;
156 if (cpu_has_feature(CPU_FTR_VSX
))
159 tsk
->thread
.regs
->msr
= msr
;
162 void giveup_fpu(struct task_struct
*tsk
)
164 check_if_tm_restore_required(tsk
);
166 msr_check_and_set(MSR_FP
);
168 msr_check_and_clear(MSR_FP
);
170 EXPORT_SYMBOL(giveup_fpu
);
173 * Make sure the floating-point register state in the
174 * the thread_struct is up to date for task tsk.
176 void flush_fp_to_thread(struct task_struct
*tsk
)
178 if (tsk
->thread
.regs
) {
180 * We need to disable preemption here because if we didn't,
181 * another process could get scheduled after the regs->msr
182 * test but before we have finished saving the FP registers
183 * to the thread_struct. That process could take over the
184 * FPU, and then when we get scheduled again we would store
185 * bogus values for the remaining FP registers.
188 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
190 * This should only ever be called for current or
191 * for a stopped child process. Since we save away
192 * the FP register state on context switch,
193 * there is something wrong if a stopped child appears
194 * to still have its FP state in the CPU registers.
196 BUG_ON(tsk
!= current
);
202 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
204 void enable_kernel_fp(void)
206 WARN_ON(preemptible());
208 msr_check_and_set(MSR_FP
);
210 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
211 check_if_tm_restore_required(current
);
212 __giveup_fpu(current
);
215 EXPORT_SYMBOL(enable_kernel_fp
);
217 static int restore_fp(struct task_struct
*tsk
) {
218 if (tsk
->thread
.load_fp
|| msr_tm_active(tsk
->thread
.regs
->msr
)) {
219 load_fp_state(¤t
->thread
.fp_state
);
220 current
->thread
.load_fp
++;
226 static int restore_fp(struct task_struct
*tsk
) { return 0; }
227 #endif /* CONFIG_PPC_FPU */
229 #ifdef CONFIG_ALTIVEC
230 #define loadvec(thr) ((thr).load_vec)
232 static void __giveup_altivec(struct task_struct
*tsk
)
237 msr
= tsk
->thread
.regs
->msr
;
240 if (cpu_has_feature(CPU_FTR_VSX
))
243 tsk
->thread
.regs
->msr
= msr
;
246 void giveup_altivec(struct task_struct
*tsk
)
248 check_if_tm_restore_required(tsk
);
250 msr_check_and_set(MSR_VEC
);
251 __giveup_altivec(tsk
);
252 msr_check_and_clear(MSR_VEC
);
254 EXPORT_SYMBOL(giveup_altivec
);
256 void enable_kernel_altivec(void)
258 WARN_ON(preemptible());
260 msr_check_and_set(MSR_VEC
);
262 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
263 check_if_tm_restore_required(current
);
264 __giveup_altivec(current
);
267 EXPORT_SYMBOL(enable_kernel_altivec
);
270 * Make sure the VMX/Altivec register state in the
271 * the thread_struct is up to date for task tsk.
273 void flush_altivec_to_thread(struct task_struct
*tsk
)
275 if (tsk
->thread
.regs
) {
277 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
278 BUG_ON(tsk
!= current
);
284 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
286 static int restore_altivec(struct task_struct
*tsk
)
288 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
289 (tsk
->thread
.load_vec
|| msr_tm_active(tsk
->thread
.regs
->msr
))) {
290 load_vr_state(&tsk
->thread
.vr_state
);
291 tsk
->thread
.used_vr
= 1;
292 tsk
->thread
.load_vec
++;
299 #define loadvec(thr) 0
300 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
301 #endif /* CONFIG_ALTIVEC */
304 static void __giveup_vsx(struct task_struct
*tsk
)
306 if (tsk
->thread
.regs
->msr
& MSR_FP
)
308 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
309 __giveup_altivec(tsk
);
310 tsk
->thread
.regs
->msr
&= ~MSR_VSX
;
313 static void giveup_vsx(struct task_struct
*tsk
)
315 check_if_tm_restore_required(tsk
);
317 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
319 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
322 static void save_vsx(struct task_struct
*tsk
)
324 if (tsk
->thread
.regs
->msr
& MSR_FP
)
326 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
330 void enable_kernel_vsx(void)
332 WARN_ON(preemptible());
334 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
336 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VSX
)) {
337 check_if_tm_restore_required(current
);
338 if (current
->thread
.regs
->msr
& MSR_FP
)
339 __giveup_fpu(current
);
340 if (current
->thread
.regs
->msr
& MSR_VEC
)
341 __giveup_altivec(current
);
342 __giveup_vsx(current
);
345 EXPORT_SYMBOL(enable_kernel_vsx
);
347 void flush_vsx_to_thread(struct task_struct
*tsk
)
349 if (tsk
->thread
.regs
) {
351 if (tsk
->thread
.regs
->msr
& MSR_VSX
) {
352 BUG_ON(tsk
!= current
);
358 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
360 static int restore_vsx(struct task_struct
*tsk
)
362 if (cpu_has_feature(CPU_FTR_VSX
)) {
363 tsk
->thread
.used_vsr
= 1;
370 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
371 static inline void save_vsx(struct task_struct
*tsk
) { }
372 #endif /* CONFIG_VSX */
375 void giveup_spe(struct task_struct
*tsk
)
377 check_if_tm_restore_required(tsk
);
379 msr_check_and_set(MSR_SPE
);
381 msr_check_and_clear(MSR_SPE
);
383 EXPORT_SYMBOL(giveup_spe
);
385 void enable_kernel_spe(void)
387 WARN_ON(preemptible());
389 msr_check_and_set(MSR_SPE
);
391 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
392 check_if_tm_restore_required(current
);
393 __giveup_spe(current
);
396 EXPORT_SYMBOL(enable_kernel_spe
);
398 void flush_spe_to_thread(struct task_struct
*tsk
)
400 if (tsk
->thread
.regs
) {
402 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
403 BUG_ON(tsk
!= current
);
404 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
410 #endif /* CONFIG_SPE */
412 static unsigned long msr_all_available
;
414 static int __init
init_msr_all_available(void)
416 #ifdef CONFIG_PPC_FPU
417 msr_all_available
|= MSR_FP
;
419 #ifdef CONFIG_ALTIVEC
420 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
421 msr_all_available
|= MSR_VEC
;
424 if (cpu_has_feature(CPU_FTR_VSX
))
425 msr_all_available
|= MSR_VSX
;
428 if (cpu_has_feature(CPU_FTR_SPE
))
429 msr_all_available
|= MSR_SPE
;
434 early_initcall(init_msr_all_available
);
436 void giveup_all(struct task_struct
*tsk
)
438 unsigned long usermsr
;
440 if (!tsk
->thread
.regs
)
443 usermsr
= tsk
->thread
.regs
->msr
;
445 if ((usermsr
& msr_all_available
) == 0)
448 msr_check_and_set(msr_all_available
);
450 #ifdef CONFIG_PPC_FPU
451 if (usermsr
& MSR_FP
)
454 #ifdef CONFIG_ALTIVEC
455 if (usermsr
& MSR_VEC
)
456 __giveup_altivec(tsk
);
459 if (usermsr
& MSR_VSX
)
463 if (usermsr
& MSR_SPE
)
467 msr_check_and_clear(msr_all_available
);
469 EXPORT_SYMBOL(giveup_all
);
471 void restore_math(struct pt_regs
*regs
)
475 if (!msr_tm_active(regs
->msr
) &&
476 !current
->thread
.load_fp
&& !loadvec(current
->thread
))
480 msr_check_and_set(msr_all_available
);
483 * Only reload if the bit is not set in the user MSR, the bit BEING set
484 * indicates that the registers are hot
486 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
487 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
489 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
492 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
493 restore_vsx(current
)) {
497 msr_check_and_clear(msr_all_available
);
502 void save_all(struct task_struct
*tsk
)
504 unsigned long usermsr
;
506 if (!tsk
->thread
.regs
)
509 usermsr
= tsk
->thread
.regs
->msr
;
511 if ((usermsr
& msr_all_available
) == 0)
514 msr_check_and_set(msr_all_available
);
517 * Saving the way the register space is in hardware, save_vsx boils
518 * down to a save_fpu() and save_altivec()
520 if (usermsr
& MSR_VSX
) {
523 if (usermsr
& MSR_FP
)
526 if (usermsr
& MSR_VEC
)
530 if (usermsr
& MSR_SPE
)
533 msr_check_and_clear(msr_all_available
);
536 void flush_all_to_thread(struct task_struct
*tsk
)
538 if (tsk
->thread
.regs
) {
540 BUG_ON(tsk
!= current
);
544 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
545 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
551 EXPORT_SYMBOL(flush_all_to_thread
);
553 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
554 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
555 unsigned long error_code
, int signal_code
, int breakpt
)
559 current
->thread
.trap_nr
= signal_code
;
560 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
561 11, SIGSEGV
) == NOTIFY_STOP
)
564 /* Deliver the signal to userspace */
565 info
.si_signo
= SIGTRAP
;
566 info
.si_errno
= breakpt
; /* breakpoint or watchpoint id */
567 info
.si_code
= signal_code
;
568 info
.si_addr
= (void __user
*)address
;
569 force_sig_info(SIGTRAP
, &info
, current
);
571 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
572 void do_break (struct pt_regs
*regs
, unsigned long address
,
573 unsigned long error_code
)
577 current
->thread
.trap_nr
= TRAP_HWBKPT
;
578 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
579 11, SIGSEGV
) == NOTIFY_STOP
)
582 if (debugger_break_match(regs
))
585 /* Clear the breakpoint */
586 hw_breakpoint_disable();
588 /* Deliver the signal to userspace */
589 info
.si_signo
= SIGTRAP
;
591 info
.si_code
= TRAP_HWBKPT
;
592 info
.si_addr
= (void __user
*)address
;
593 force_sig_info(SIGTRAP
, &info
, current
);
595 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
597 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
599 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
601 * Set the debug registers back to their default "safe" values.
603 static void set_debug_reg_defaults(struct thread_struct
*thread
)
605 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
606 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
607 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
609 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
610 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
611 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
613 thread
->debug
.dbcr0
= 0;
616 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
618 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
619 DBCR1_IAC3US
| DBCR1_IAC4US
;
621 * Force Data Address Compare User/Supervisor bits to be User-only
622 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
624 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
626 thread
->debug
.dbcr1
= 0;
630 static void prime_debug_regs(struct debug_reg
*debug
)
633 * We could have inherited MSR_DE from userspace, since
634 * it doesn't get cleared on exception entry. Make sure
635 * MSR_DE is clear before we enable any debug events.
637 mtmsr(mfmsr() & ~MSR_DE
);
639 mtspr(SPRN_IAC1
, debug
->iac1
);
640 mtspr(SPRN_IAC2
, debug
->iac2
);
641 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
642 mtspr(SPRN_IAC3
, debug
->iac3
);
643 mtspr(SPRN_IAC4
, debug
->iac4
);
645 mtspr(SPRN_DAC1
, debug
->dac1
);
646 mtspr(SPRN_DAC2
, debug
->dac2
);
647 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
648 mtspr(SPRN_DVC1
, debug
->dvc1
);
649 mtspr(SPRN_DVC2
, debug
->dvc2
);
651 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
652 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
654 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
658 * Unless neither the old or new thread are making use of the
659 * debug registers, set the debug registers from the values
660 * stored in the new thread.
662 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
664 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
665 || (new_debug
->dbcr0
& DBCR0_IDM
))
666 prime_debug_regs(new_debug
);
668 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
669 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
670 #ifndef CONFIG_HAVE_HW_BREAKPOINT
671 static void set_debug_reg_defaults(struct thread_struct
*thread
)
673 thread
->hw_brk
.address
= 0;
674 thread
->hw_brk
.type
= 0;
675 set_breakpoint(&thread
->hw_brk
);
677 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
678 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
680 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
681 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
683 mtspr(SPRN_DAC1
, dabr
);
684 #ifdef CONFIG_PPC_47x
689 #elif defined(CONFIG_PPC_BOOK3S)
690 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
692 mtspr(SPRN_DABR
, dabr
);
693 if (cpu_has_feature(CPU_FTR_DABRX
))
694 mtspr(SPRN_DABRX
, dabrx
);
698 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
704 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
706 unsigned long dabr
, dabrx
;
708 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
709 dabrx
= ((brk
->type
>> 3) & 0x7);
712 return ppc_md
.set_dabr(dabr
, dabrx
);
714 return __set_dabr(dabr
, dabrx
);
717 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
719 unsigned long dawr
, dawrx
, mrd
;
723 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
724 << (63 - 58); //* read/write bits */
725 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
726 << (63 - 59); //* translate */
727 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
728 >> 3; //* PRIM bits */
729 /* dawr length is stored in field MDR bits 48:53. Matches range in
730 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
732 brk->len is in bytes.
733 This aligns up to double word size, shifts and does the bias.
735 mrd
= ((brk
->len
+ 7) >> 3) - 1;
736 dawrx
|= (mrd
& 0x3f) << (63 - 53);
739 return ppc_md
.set_dawr(dawr
, dawrx
);
740 mtspr(SPRN_DAWR
, dawr
);
741 mtspr(SPRN_DAWRX
, dawrx
);
745 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
747 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
749 if (cpu_has_feature(CPU_FTR_DAWR
))
755 void set_breakpoint(struct arch_hw_breakpoint
*brk
)
758 __set_breakpoint(brk
);
763 DEFINE_PER_CPU(struct cpu_usage
, cpu_usage_array
);
766 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
767 struct arch_hw_breakpoint
*b
)
769 if (a
->address
!= b
->address
)
771 if (a
->type
!= b
->type
)
773 if (a
->len
!= b
->len
)
778 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
779 static void tm_reclaim_thread(struct thread_struct
*thr
,
780 struct thread_info
*ti
, uint8_t cause
)
782 unsigned long msr_diff
= 0;
785 * If FP/VSX registers have been already saved to the
786 * thread_struct, move them to the transact_fp array.
787 * We clear the TIF_RESTORE_TM bit since after the reclaim
788 * the thread will no longer be transactional.
790 if (test_ti_thread_flag(ti
, TIF_RESTORE_TM
)) {
791 msr_diff
= thr
->ckpt_regs
.msr
& ~thr
->regs
->msr
;
792 if (msr_diff
& MSR_FP
)
793 memcpy(&thr
->transact_fp
, &thr
->fp_state
,
794 sizeof(struct thread_fp_state
));
795 if (msr_diff
& MSR_VEC
)
796 memcpy(&thr
->transact_vr
, &thr
->vr_state
,
797 sizeof(struct thread_vr_state
));
798 clear_ti_thread_flag(ti
, TIF_RESTORE_TM
);
799 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
| MSR_FE0
| MSR_FE1
;
803 * Use the current MSR TM suspended bit to track if we have
804 * checkpointed state outstanding.
805 * On signal delivery, we'd normally reclaim the checkpointed
806 * state to obtain stack pointer (see:get_tm_stackpointer()).
807 * This will then directly return to userspace without going
808 * through __switch_to(). However, if the stack frame is bad,
809 * we need to exit this thread which calls __switch_to() which
810 * will again attempt to reclaim the already saved tm state.
811 * Hence we need to check that we've not already reclaimed
813 * We do this using the current MSR, rather tracking it in
814 * some specific thread_struct bit, as it has the additional
815 * benefit of checking for a potential TM bad thing exception.
817 if (!MSR_TM_SUSPENDED(mfmsr()))
820 tm_reclaim(thr
, thr
->regs
->msr
, cause
);
822 /* Having done the reclaim, we now have the checkpointed
823 * FP/VSX values in the registers. These might be valid
824 * even if we have previously called enable_kernel_fp() or
825 * flush_fp_to_thread(), so update thr->regs->msr to
826 * indicate their current validity.
828 thr
->regs
->msr
|= msr_diff
;
831 void tm_reclaim_current(uint8_t cause
)
834 tm_reclaim_thread(¤t
->thread
, current_thread_info(), cause
);
837 static inline void tm_reclaim_task(struct task_struct
*tsk
)
839 /* We have to work out if we're switching from/to a task that's in the
840 * middle of a transaction.
842 * In switching we need to maintain a 2nd register state as
843 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
844 * checkpointed (tbegin) state in ckpt_regs and saves the transactional
845 * (current) FPRs into oldtask->thread.transact_fpr[].
847 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
849 struct thread_struct
*thr
= &tsk
->thread
;
854 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
855 goto out_and_saveregs
;
857 /* Stash the original thread MSR, as giveup_fpu et al will
858 * modify it. We hold onto it to see whether the task used
859 * FP & vector regs. If the TIF_RESTORE_TM flag is set,
860 * ckpt_regs.msr is already set.
862 if (!test_ti_thread_flag(task_thread_info(tsk
), TIF_RESTORE_TM
))
863 thr
->ckpt_regs
.msr
= thr
->regs
->msr
;
865 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
866 "ccr=%lx, msr=%lx, trap=%lx)\n",
867 tsk
->pid
, thr
->regs
->nip
,
868 thr
->regs
->ccr
, thr
->regs
->msr
,
871 tm_reclaim_thread(thr
, task_thread_info(tsk
), TM_CAUSE_RESCHED
);
873 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
877 /* Always save the regs here, even if a transaction's not active.
878 * This context-switches a thread's TM info SPRs. We do it here to
879 * be consistent with the restore path (in recheckpoint) which
880 * cannot happen later in _switch().
885 extern void __tm_recheckpoint(struct thread_struct
*thread
,
886 unsigned long orig_msr
);
888 void tm_recheckpoint(struct thread_struct
*thread
,
889 unsigned long orig_msr
)
893 /* We really can't be interrupted here as the TEXASR registers can't
894 * change and later in the trecheckpoint code, we have a userspace R1.
895 * So let's hard disable over this region.
897 local_irq_save(flags
);
900 /* The TM SPRs are restored here, so that TEXASR.FS can be set
901 * before the trecheckpoint and no explosion occurs.
903 tm_restore_sprs(thread
);
905 __tm_recheckpoint(thread
, orig_msr
);
907 local_irq_restore(flags
);
910 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
914 if (!cpu_has_feature(CPU_FTR_TM
))
917 /* Recheckpoint the registers of the thread we're about to switch to.
919 * If the task was using FP, we non-lazily reload both the original and
920 * the speculative FP register states. This is because the kernel
921 * doesn't see if/when a TM rollback occurs, so if we take an FP
922 * unavoidable later, we are unable to determine which set of FP regs
923 * need to be restored.
925 if (!new->thread
.regs
)
928 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
929 tm_restore_sprs(&new->thread
);
932 msr
= new->thread
.ckpt_regs
.msr
;
933 /* Recheckpoint to restore original checkpointed register state. */
934 TM_DEBUG("*** tm_recheckpoint of pid %d "
935 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
936 new->pid
, new->thread
.regs
->msr
, msr
);
938 /* This loads the checkpointed FP/VEC state, if used */
939 tm_recheckpoint(&new->thread
, msr
);
941 /* This loads the speculative FP/VEC state, if used */
943 do_load_up_transact_fpu(&new->thread
);
944 new->thread
.regs
->msr
|=
945 (MSR_FP
| new->thread
.fpexc_mode
);
947 #ifdef CONFIG_ALTIVEC
949 do_load_up_transact_altivec(&new->thread
);
950 new->thread
.regs
->msr
|= MSR_VEC
;
953 /* We may as well turn on VSX too since all the state is restored now */
955 new->thread
.regs
->msr
|= MSR_VSX
;
957 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
958 "(kernel msr 0x%lx)\n",
962 static inline void __switch_to_tm(struct task_struct
*prev
)
964 if (cpu_has_feature(CPU_FTR_TM
)) {
966 tm_reclaim_task(prev
);
971 * This is called if we are on the way out to userspace and the
972 * TIF_RESTORE_TM flag is set. It checks if we need to reload
973 * FP and/or vector state and does so if necessary.
974 * If userspace is inside a transaction (whether active or
975 * suspended) and FP/VMX/VSX instructions have ever been enabled
976 * inside that transaction, then we have to keep them enabled
977 * and keep the FP/VMX/VSX state loaded while ever the transaction
978 * continues. The reason is that if we didn't, and subsequently
979 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
980 * we don't know whether it's the same transaction, and thus we
981 * don't know which of the checkpointed state and the transactional
984 void restore_tm_state(struct pt_regs
*regs
)
986 unsigned long msr_diff
;
988 clear_thread_flag(TIF_RESTORE_TM
);
989 if (!MSR_TM_ACTIVE(regs
->msr
))
992 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
993 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
995 /* Ensure that restore_math() will restore */
996 if (msr_diff
& MSR_FP
)
997 current
->thread
.load_fp
= 1;
999 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && msr_diff
& MSR_VEC
)
1000 current
->thread
.load_vec
= 1;
1004 regs
->msr
|= msr_diff
;
1008 #define tm_recheckpoint_new_task(new)
1009 #define __switch_to_tm(prev)
1010 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1012 static inline void save_sprs(struct thread_struct
*t
)
1014 #ifdef CONFIG_ALTIVEC
1015 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
1016 t
->vrsave
= mfspr(SPRN_VRSAVE
);
1018 #ifdef CONFIG_PPC_BOOK3S_64
1019 if (cpu_has_feature(CPU_FTR_DSCR
))
1020 t
->dscr
= mfspr(SPRN_DSCR
);
1022 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1023 t
->bescr
= mfspr(SPRN_BESCR
);
1024 t
->ebbhr
= mfspr(SPRN_EBBHR
);
1025 t
->ebbrr
= mfspr(SPRN_EBBRR
);
1027 t
->fscr
= mfspr(SPRN_FSCR
);
1030 * Note that the TAR is not available for use in the kernel.
1031 * (To provide this, the TAR should be backed up/restored on
1032 * exception entry/exit instead, and be in pt_regs. FIXME,
1033 * this should be in pt_regs anyway (for debug).)
1035 t
->tar
= mfspr(SPRN_TAR
);
1038 if (cpu_has_feature(CPU_FTR_ARCH_300
)) {
1039 /* Conditionally save Load Monitor registers, if enabled */
1040 if (t
->fscr
& FSCR_LM
) {
1041 t
->lmrr
= mfspr(SPRN_LMRR
);
1042 t
->lmser
= mfspr(SPRN_LMSER
);
1048 static inline void restore_sprs(struct thread_struct
*old_thread
,
1049 struct thread_struct
*new_thread
)
1051 #ifdef CONFIG_ALTIVEC
1052 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
1053 old_thread
->vrsave
!= new_thread
->vrsave
)
1054 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
1056 #ifdef CONFIG_PPC_BOOK3S_64
1057 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1058 u64 dscr
= get_paca()->dscr_default
;
1059 if (new_thread
->dscr_inherit
)
1060 dscr
= new_thread
->dscr
;
1062 if (old_thread
->dscr
!= dscr
)
1063 mtspr(SPRN_DSCR
, dscr
);
1066 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1067 if (old_thread
->bescr
!= new_thread
->bescr
)
1068 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1069 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1070 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1071 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1072 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1074 if (old_thread
->fscr
!= new_thread
->fscr
)
1075 mtspr(SPRN_FSCR
, new_thread
->fscr
);
1077 if (old_thread
->tar
!= new_thread
->tar
)
1078 mtspr(SPRN_TAR
, new_thread
->tar
);
1081 if (cpu_has_feature(CPU_FTR_ARCH_300
)) {
1082 /* Conditionally restore Load Monitor registers, if enabled */
1083 if (new_thread
->fscr
& FSCR_LM
) {
1084 if (old_thread
->lmrr
!= new_thread
->lmrr
)
1085 mtspr(SPRN_LMRR
, new_thread
->lmrr
);
1086 if (old_thread
->lmser
!= new_thread
->lmser
)
1087 mtspr(SPRN_LMSER
, new_thread
->lmser
);
1093 struct task_struct
*__switch_to(struct task_struct
*prev
,
1094 struct task_struct
*new)
1096 struct thread_struct
*new_thread
, *old_thread
;
1097 struct task_struct
*last
;
1098 #ifdef CONFIG_PPC_BOOK3S_64
1099 struct ppc64_tlb_batch
*batch
;
1102 new_thread
= &new->thread
;
1103 old_thread
= ¤t
->thread
;
1105 WARN_ON(!irqs_disabled());
1109 * Collect processor utilization data per process
1111 if (firmware_has_feature(FW_FEATURE_SPLPAR
)) {
1112 struct cpu_usage
*cu
= this_cpu_ptr(&cpu_usage_array
);
1113 long unsigned start_tb
, current_tb
;
1114 start_tb
= old_thread
->start_tb
;
1115 cu
->current_tb
= current_tb
= mfspr(SPRN_PURR
);
1116 old_thread
->accum_tb
+= (current_tb
- start_tb
);
1117 new_thread
->start_tb
= current_tb
;
1119 #endif /* CONFIG_PPC64 */
1121 #ifdef CONFIG_PPC_STD_MMU_64
1122 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1123 if (batch
->active
) {
1124 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1126 __flush_tlb_pending(batch
);
1129 #endif /* CONFIG_PPC_STD_MMU_64 */
1131 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1132 switch_booke_debug_regs(&new->thread
.debug
);
1135 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1138 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1139 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1140 __set_breakpoint(&new->thread
.hw_brk
);
1141 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1145 * We need to save SPRs before treclaim/trecheckpoint as these will
1146 * change a number of them.
1148 save_sprs(&prev
->thread
);
1150 __switch_to_tm(prev
);
1152 /* Save FPU, Altivec, VSX and SPE state */
1156 * We can't take a PMU exception inside _switch() since there is a
1157 * window where the kernel stack SLB and the kernel stack are out
1158 * of sync. Hard disable here.
1162 tm_recheckpoint_new_task(new);
1165 * Call restore_sprs() before calling _switch(). If we move it after
1166 * _switch() then we miss out on calling it for new tasks. The reason
1167 * for this is we manually create a stack frame for new tasks that
1168 * directly returns through ret_from_fork() or
1169 * ret_from_kernel_thread(). See copy_thread() for details.
1171 restore_sprs(old_thread
, new_thread
);
1173 last
= _switch(old_thread
, new_thread
);
1175 #ifdef CONFIG_PPC_STD_MMU_64
1176 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1177 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1178 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1182 if (current_thread_info()->task
->thread
.regs
)
1183 restore_math(current_thread_info()->task
->thread
.regs
);
1184 #endif /* CONFIG_PPC_STD_MMU_64 */
1189 static int instructions_to_print
= 16;
1191 static void show_instructions(struct pt_regs
*regs
)
1194 unsigned long pc
= regs
->nip
- (instructions_to_print
* 3 / 4 *
1197 printk("Instruction dump:");
1199 for (i
= 0; i
< instructions_to_print
; i
++) {
1205 #if !defined(CONFIG_BOOKE)
1206 /* If executing with the IMMU off, adjust pc rather
1207 * than print XXXXXXXX.
1209 if (!(regs
->msr
& MSR_IR
))
1210 pc
= (unsigned long)phys_to_virt(pc
);
1213 if (!__kernel_text_address(pc
) ||
1214 probe_kernel_address((unsigned int __user
*)pc
, instr
)) {
1215 printk(KERN_CONT
"XXXXXXXX ");
1217 if (regs
->nip
== pc
)
1218 printk(KERN_CONT
"<%08x> ", instr
);
1220 printk(KERN_CONT
"%08x ", instr
);
1234 static struct regbit msr_bits
[] = {
1235 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1257 #ifndef CONFIG_BOOKE
1264 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1268 for (; bits
->bit
; ++bits
)
1269 if (val
& bits
->bit
) {
1270 printk("%s%s", s
, bits
->name
);
1275 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1276 static struct regbit msr_tm_bits
[] = {
1283 static void print_tm_bits(unsigned long val
)
1286 * This only prints something if at least one of the TM bit is set.
1287 * Inside the TM[], the output means:
1288 * E: Enabled (bit 32)
1289 * S: Suspended (bit 33)
1290 * T: Transactional (bit 34)
1292 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1294 print_bits(val
, msr_tm_bits
, "");
1299 static void print_tm_bits(unsigned long val
) {}
1302 static void print_msr_bits(unsigned long val
)
1305 print_bits(val
, msr_bits
, ",");
1311 #define REG "%016lx"
1312 #define REGS_PER_LINE 4
1313 #define LAST_VOLATILE 13
1316 #define REGS_PER_LINE 8
1317 #define LAST_VOLATILE 12
1320 void show_regs(struct pt_regs
* regs
)
1324 show_regs_print_info(KERN_DEFAULT
);
1326 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1327 regs
->nip
, regs
->link
, regs
->ctr
);
1328 printk("REGS: %p TRAP: %04lx %s (%s)\n",
1329 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1330 printk("MSR: "REG
" ", regs
->msr
);
1331 print_msr_bits(regs
->msr
);
1332 printk(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1334 if ((regs
->trap
!= 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1335 printk("CFAR: "REG
" ", regs
->orig_gpr3
);
1336 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1337 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1338 printk("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1340 printk("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1343 printk("SOFTE: %ld ", regs
->softe
);
1345 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1346 if (MSR_TM_ACTIVE(regs
->msr
))
1347 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1350 for (i
= 0; i
< 32; i
++) {
1351 if ((i
% REGS_PER_LINE
) == 0)
1352 printk("\nGPR%02d: ", i
);
1353 printk(REG
" ", regs
->gpr
[i
]);
1354 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1358 #ifdef CONFIG_KALLSYMS
1360 * Lookup NIP late so we have the best change of getting the
1361 * above info out without failing
1363 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1364 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1366 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1367 if (!user_mode(regs
))
1368 show_instructions(regs
);
1371 void flush_thread(void)
1373 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1374 flush_ptrace_hw_breakpoint(current
);
1375 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1376 set_debug_reg_defaults(¤t
->thread
);
1377 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1381 release_thread(struct task_struct
*t
)
1386 * this gets called so that we can store coprocessor state into memory and
1387 * copy the current task into the new thread.
1389 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1391 flush_all_to_thread(src
);
1393 * Flush TM state out so we can copy it. __switch_to_tm() does this
1394 * flush but it removes the checkpointed state from the current CPU and
1395 * transitions the CPU out of TM mode. Hence we need to call
1396 * tm_recheckpoint_new_task() (on the same task) to restore the
1397 * checkpointed state back and the TM mode.
1399 __switch_to_tm(src
);
1400 tm_recheckpoint_new_task(src
);
1404 clear_task_ebb(dst
);
1409 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1411 #ifdef CONFIG_PPC_STD_MMU_64
1412 unsigned long sp_vsid
;
1413 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1415 if (radix_enabled())
1418 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1419 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1420 << SLB_VSID_SHIFT_1T
;
1422 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1424 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1425 p
->thread
.ksp_vsid
= sp_vsid
;
1434 * Copy architecture-specific thread state
1436 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1437 unsigned long kthread_arg
, struct task_struct
*p
)
1439 struct pt_regs
*childregs
, *kregs
;
1440 extern void ret_from_fork(void);
1441 extern void ret_from_kernel_thread(void);
1443 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1444 struct thread_info
*ti
= task_thread_info(p
);
1446 klp_init_thread_info(ti
);
1448 /* Copy registers */
1449 sp
-= sizeof(struct pt_regs
);
1450 childregs
= (struct pt_regs
*) sp
;
1451 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1453 memset(childregs
, 0, sizeof(struct pt_regs
));
1454 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1457 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1459 clear_tsk_thread_flag(p
, TIF_32BIT
);
1460 childregs
->softe
= 1;
1462 childregs
->gpr
[15] = kthread_arg
;
1463 p
->thread
.regs
= NULL
; /* no user register state */
1464 ti
->flags
|= _TIF_RESTOREALL
;
1465 f
= ret_from_kernel_thread
;
1468 struct pt_regs
*regs
= current_pt_regs();
1469 CHECK_FULL_REGS(regs
);
1472 childregs
->gpr
[1] = usp
;
1473 p
->thread
.regs
= childregs
;
1474 childregs
->gpr
[3] = 0; /* Result from fork() */
1475 if (clone_flags
& CLONE_SETTLS
) {
1477 if (!is_32bit_task())
1478 childregs
->gpr
[13] = childregs
->gpr
[6];
1481 childregs
->gpr
[2] = childregs
->gpr
[6];
1486 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1487 sp
-= STACK_FRAME_OVERHEAD
;
1490 * The way this works is that at some point in the future
1491 * some task will call _switch to switch to the new task.
1492 * That will pop off the stack frame created below and start
1493 * the new task running at ret_from_fork. The new task will
1494 * do some house keeping and then return from the fork or clone
1495 * system call, using the stack frame created above.
1497 ((unsigned long *)sp
)[0] = 0;
1498 sp
-= sizeof(struct pt_regs
);
1499 kregs
= (struct pt_regs
*) sp
;
1500 sp
-= STACK_FRAME_OVERHEAD
;
1503 p
->thread
.ksp_limit
= (unsigned long)task_stack_page(p
) +
1504 _ALIGN_UP(sizeof(struct thread_info
), 16);
1506 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1507 p
->thread
.ptrace_bps
[0] = NULL
;
1510 p
->thread
.fp_save_area
= NULL
;
1511 #ifdef CONFIG_ALTIVEC
1512 p
->thread
.vr_save_area
= NULL
;
1515 setup_ksp_vsid(p
, sp
);
1518 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1519 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1520 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1522 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1523 p
->thread
.ppr
= INIT_PPR
;
1525 kregs
->nip
= ppc_function_entry(f
);
1530 * Set up a thread for executing a new program
1532 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1535 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1539 * If we exec out of a kernel thread then thread.regs will not be
1542 if (!current
->thread
.regs
) {
1543 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1544 current
->thread
.regs
= regs
- 1;
1547 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1549 * Clear any transactional state, we're exec()ing. The cause is
1550 * not important as there will never be a recheckpoint so it's not
1553 if (MSR_TM_SUSPENDED(mfmsr()))
1554 tm_reclaim_current(0);
1557 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1565 * We have just cleared all the nonvolatile GPRs, so make
1566 * FULL_REGS(regs) return true. This is necessary to allow
1567 * ptrace to examine the thread immediately after exec.
1574 regs
->msr
= MSR_USER
;
1576 if (!is_32bit_task()) {
1577 unsigned long entry
;
1579 if (is_elf2_task()) {
1580 /* Look ma, no function descriptors! */
1585 * The latest iteration of the ABI requires that when
1586 * calling a function (at its global entry point),
1587 * the caller must ensure r12 holds the entry point
1588 * address (so that the function can quickly
1589 * establish addressability).
1591 regs
->gpr
[12] = start
;
1592 /* Make sure that's restored on entry to userspace. */
1593 set_thread_flag(TIF_RESTOREALL
);
1597 /* start is a relocated pointer to the function
1598 * descriptor for the elf _start routine. The first
1599 * entry in the function descriptor is the entry
1600 * address of _start and the second entry is the TOC
1601 * value we need to use.
1603 __get_user(entry
, (unsigned long __user
*)start
);
1604 __get_user(toc
, (unsigned long __user
*)start
+1);
1606 /* Check whether the e_entry function descriptor entries
1607 * need to be relocated before we can use them.
1609 if (load_addr
!= 0) {
1616 regs
->msr
= MSR_USER64
;
1620 regs
->msr
= MSR_USER32
;
1624 current
->thread
.used_vsr
= 0;
1626 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1627 current
->thread
.fp_save_area
= NULL
;
1628 #ifdef CONFIG_ALTIVEC
1629 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1630 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1631 current
->thread
.vr_save_area
= NULL
;
1632 current
->thread
.vrsave
= 0;
1633 current
->thread
.used_vr
= 0;
1634 #endif /* CONFIG_ALTIVEC */
1636 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1637 current
->thread
.acc
= 0;
1638 current
->thread
.spefscr
= 0;
1639 current
->thread
.used_spe
= 0;
1640 #endif /* CONFIG_SPE */
1641 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1642 if (cpu_has_feature(CPU_FTR_TM
))
1643 regs
->msr
|= MSR_TM
;
1644 current
->thread
.tm_tfhar
= 0;
1645 current
->thread
.tm_texasr
= 0;
1646 current
->thread
.tm_tfiar
= 0;
1647 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1649 EXPORT_SYMBOL(start_thread
);
1651 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1652 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1654 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1656 struct pt_regs
*regs
= tsk
->thread
.regs
;
1658 /* This is a bit hairy. If we are an SPE enabled processor
1659 * (have embedded fp) we store the IEEE exception enable flags in
1660 * fpexc_mode. fpexc_mode is also used for setting FP exception
1661 * mode (asyn, precise, disabled) for 'Classic' FP. */
1662 if (val
& PR_FP_EXC_SW_ENABLE
) {
1664 if (cpu_has_feature(CPU_FTR_SPE
)) {
1666 * When the sticky exception bits are set
1667 * directly by userspace, it must call prctl
1668 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1669 * in the existing prctl settings) or
1670 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1671 * the bits being set). <fenv.h> functions
1672 * saving and restoring the whole
1673 * floating-point environment need to do so
1674 * anyway to restore the prctl settings from
1675 * the saved environment.
1677 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1678 tsk
->thread
.fpexc_mode
= val
&
1679 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1689 /* on a CONFIG_SPE this does not hurt us. The bits that
1690 * __pack_fe01 use do not overlap with bits used for
1691 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1692 * on CONFIG_SPE implementations are reserved so writing to
1693 * them does not change anything */
1694 if (val
> PR_FP_EXC_PRECISE
)
1696 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1697 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1698 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1699 | tsk
->thread
.fpexc_mode
;
1703 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1707 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1709 if (cpu_has_feature(CPU_FTR_SPE
)) {
1711 * When the sticky exception bits are set
1712 * directly by userspace, it must call prctl
1713 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1714 * in the existing prctl settings) or
1715 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1716 * the bits being set). <fenv.h> functions
1717 * saving and restoring the whole
1718 * floating-point environment need to do so
1719 * anyway to restore the prctl settings from
1720 * the saved environment.
1722 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1723 val
= tsk
->thread
.fpexc_mode
;
1730 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1731 return put_user(val
, (unsigned int __user
*) adr
);
1734 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1736 struct pt_regs
*regs
= tsk
->thread
.regs
;
1738 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1739 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1745 if (val
== PR_ENDIAN_BIG
)
1746 regs
->msr
&= ~MSR_LE
;
1747 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1748 regs
->msr
|= MSR_LE
;
1755 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1757 struct pt_regs
*regs
= tsk
->thread
.regs
;
1760 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1761 !cpu_has_feature(CPU_FTR_REAL_LE
))
1767 if (regs
->msr
& MSR_LE
) {
1768 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1769 val
= PR_ENDIAN_LITTLE
;
1771 val
= PR_ENDIAN_PPC_LITTLE
;
1773 val
= PR_ENDIAN_BIG
;
1775 return put_user(val
, (unsigned int __user
*)adr
);
1778 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1780 tsk
->thread
.align_ctl
= val
;
1784 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1786 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1789 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1790 unsigned long nbytes
)
1792 unsigned long stack_page
;
1793 unsigned long cpu
= task_cpu(p
);
1796 * Avoid crashing if the stack has overflowed and corrupted
1797 * task_cpu(p), which is in the thread_info struct.
1799 if (cpu
< NR_CPUS
&& cpu_possible(cpu
)) {
1800 stack_page
= (unsigned long) hardirq_ctx
[cpu
];
1801 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1802 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1805 stack_page
= (unsigned long) softirq_ctx
[cpu
];
1806 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1807 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1813 int validate_sp(unsigned long sp
, struct task_struct
*p
,
1814 unsigned long nbytes
)
1816 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
1818 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1819 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1822 return valid_irq_stack(sp
, p
, nbytes
);
1825 EXPORT_SYMBOL(validate_sp
);
1827 unsigned long get_wchan(struct task_struct
*p
)
1829 unsigned long ip
, sp
;
1832 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
1836 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1840 sp
= *(unsigned long *)sp
;
1841 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1844 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
1845 if (!in_sched_functions(ip
))
1848 } while (count
++ < 16);
1852 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
1854 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
1856 unsigned long sp
, ip
, lr
, newsp
;
1859 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1860 int curr_frame
= current
->curr_ret_stack
;
1861 extern void return_to_handler(void);
1862 unsigned long rth
= (unsigned long)return_to_handler
;
1865 sp
= (unsigned long) stack
;
1870 sp
= current_stack_pointer();
1872 sp
= tsk
->thread
.ksp
;
1876 printk("Call Trace:\n");
1878 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
1881 stack
= (unsigned long *) sp
;
1883 ip
= stack
[STACK_FRAME_LR_SAVE
];
1884 if (!firstframe
|| ip
!= lr
) {
1885 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
1886 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1887 if ((ip
== rth
) && curr_frame
>= 0) {
1889 (void *)current
->ret_stack
[curr_frame
].ret
);
1894 printk(" (unreliable)");
1900 * See if this is an exception frame.
1901 * We look for the "regshere" marker in the current frame.
1903 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
1904 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
1905 struct pt_regs
*regs
= (struct pt_regs
*)
1906 (sp
+ STACK_FRAME_OVERHEAD
);
1908 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
1909 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
1914 } while (count
++ < kstack_depth_to_print
);
1918 /* Called with hard IRQs off */
1919 void notrace
__ppc64_runlatch_on(void)
1921 struct thread_info
*ti
= current_thread_info();
1924 ctrl
= mfspr(SPRN_CTRLF
);
1925 ctrl
|= CTRL_RUNLATCH
;
1926 mtspr(SPRN_CTRLT
, ctrl
);
1928 ti
->local_flags
|= _TLF_RUNLATCH
;
1931 /* Called with hard IRQs off */
1932 void notrace
__ppc64_runlatch_off(void)
1934 struct thread_info
*ti
= current_thread_info();
1937 ti
->local_flags
&= ~_TLF_RUNLATCH
;
1939 ctrl
= mfspr(SPRN_CTRLF
);
1940 ctrl
&= ~CTRL_RUNLATCH
;
1941 mtspr(SPRN_CTRLT
, ctrl
);
1943 #endif /* CONFIG_PPC64 */
1945 unsigned long arch_align_stack(unsigned long sp
)
1947 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
1948 sp
-= get_random_int() & ~PAGE_MASK
;
1952 static inline unsigned long brk_rnd(void)
1954 unsigned long rnd
= 0;
1956 /* 8MB for 32bit, 1GB for 64bit */
1957 if (is_32bit_task())
1958 rnd
= (get_random_long() % (1UL<<(23-PAGE_SHIFT
)));
1960 rnd
= (get_random_long() % (1UL<<(30-PAGE_SHIFT
)));
1962 return rnd
<< PAGE_SHIFT
;
1965 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
1967 unsigned long base
= mm
->brk
;
1970 #ifdef CONFIG_PPC_STD_MMU_64
1972 * If we are using 1TB segments and we are allowed to randomise
1973 * the heap, we can put it above 1TB so it is backed by a 1TB
1974 * segment. Otherwise the heap will be in the bottom 1TB
1975 * which always uses 256MB segments and this may result in a
1976 * performance penalty. We don't need to worry about radix. For
1977 * radix, mmu_highuser_ssize remains unchanged from 256MB.
1979 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
1980 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
1983 ret
= PAGE_ALIGN(base
+ brk_rnd());