2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/sched/debug.h>
20 #include <linux/sched/task.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/kernel.h>
24 #include <linux/smp.h>
25 #include <linux/stddef.h>
26 #include <linux/unistd.h>
27 #include <linux/ptrace.h>
28 #include <linux/slab.h>
29 #include <linux/user.h>
30 #include <linux/elf.h>
31 #include <linux/prctl.h>
32 #include <linux/init_task.h>
33 #include <linux/export.h>
34 #include <linux/kallsyms.h>
35 #include <linux/mqueue.h>
36 #include <linux/hardirq.h>
37 #include <linux/utsname.h>
38 #include <linux/ftrace.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/personality.h>
41 #include <linux/random.h>
42 #include <linux/hw_breakpoint.h>
43 #include <linux/uaccess.h>
44 #include <linux/elf-randomize.h>
46 #include <asm/pgtable.h>
48 #include <asm/processor.h>
51 #include <asm/machdep.h>
53 #include <asm/runlatch.h>
54 #include <asm/syscalls.h>
55 #include <asm/switch_to.h>
57 #include <asm/debug.h>
59 #include <asm/firmware.h>
61 #include <asm/code-patching.h>
63 #include <asm/livepatch.h>
64 #include <asm/cpu_has_feature.h>
65 #include <asm/asm-prototypes.h>
67 #include <linux/kprobes.h>
68 #include <linux/kdebug.h>
70 /* Transactional Memory debug */
72 #define TM_DEBUG(x...) printk(KERN_INFO x)
74 #define TM_DEBUG(x...) do { } while(0)
77 extern unsigned long _get_SP(void);
79 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
80 static void check_if_tm_restore_required(struct task_struct
*tsk
)
83 * If we are saving the current thread's registers, and the
84 * thread is in a transactional state, set the TIF_RESTORE_TM
85 * bit so that we know to restore the registers before
86 * returning to userspace.
88 if (tsk
== current
&& tsk
->thread
.regs
&&
89 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
90 !test_thread_flag(TIF_RESTORE_TM
)) {
91 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
92 set_thread_flag(TIF_RESTORE_TM
);
96 static inline bool msr_tm_active(unsigned long msr
)
98 return MSR_TM_ACTIVE(msr
);
101 static inline bool msr_tm_active(unsigned long msr
) { return false; }
102 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
103 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
105 bool strict_msr_control
;
106 EXPORT_SYMBOL(strict_msr_control
);
108 static int __init
enable_strict_msr_control(char *str
)
110 strict_msr_control
= true;
111 pr_info("Enabling strict facility control\n");
115 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
117 unsigned long msr_check_and_set(unsigned long bits
)
119 unsigned long oldmsr
= mfmsr();
120 unsigned long newmsr
;
122 newmsr
= oldmsr
| bits
;
125 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
129 if (oldmsr
!= newmsr
)
135 void __msr_check_and_clear(unsigned long bits
)
137 unsigned long oldmsr
= mfmsr();
138 unsigned long newmsr
;
140 newmsr
= oldmsr
& ~bits
;
143 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
147 if (oldmsr
!= newmsr
)
150 EXPORT_SYMBOL(__msr_check_and_clear
);
152 #ifdef CONFIG_PPC_FPU
153 void __giveup_fpu(struct task_struct
*tsk
)
158 msr
= tsk
->thread
.regs
->msr
;
161 if (cpu_has_feature(CPU_FTR_VSX
))
164 tsk
->thread
.regs
->msr
= msr
;
167 void giveup_fpu(struct task_struct
*tsk
)
169 check_if_tm_restore_required(tsk
);
171 msr_check_and_set(MSR_FP
);
173 msr_check_and_clear(MSR_FP
);
175 EXPORT_SYMBOL(giveup_fpu
);
178 * Make sure the floating-point register state in the
179 * the thread_struct is up to date for task tsk.
181 void flush_fp_to_thread(struct task_struct
*tsk
)
183 if (tsk
->thread
.regs
) {
185 * We need to disable preemption here because if we didn't,
186 * another process could get scheduled after the regs->msr
187 * test but before we have finished saving the FP registers
188 * to the thread_struct. That process could take over the
189 * FPU, and then when we get scheduled again we would store
190 * bogus values for the remaining FP registers.
193 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
195 * This should only ever be called for current or
196 * for a stopped child process. Since we save away
197 * the FP register state on context switch,
198 * there is something wrong if a stopped child appears
199 * to still have its FP state in the CPU registers.
201 BUG_ON(tsk
!= current
);
207 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
209 void enable_kernel_fp(void)
211 unsigned long cpumsr
;
213 WARN_ON(preemptible());
215 cpumsr
= msr_check_and_set(MSR_FP
);
217 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
218 check_if_tm_restore_required(current
);
220 * If a thread has already been reclaimed then the
221 * checkpointed registers are on the CPU but have definitely
222 * been saved by the reclaim code. Don't need to and *cannot*
223 * giveup as this would save to the 'live' structure not the
224 * checkpointed structure.
226 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
228 __giveup_fpu(current
);
231 EXPORT_SYMBOL(enable_kernel_fp
);
233 static int restore_fp(struct task_struct
*tsk
) {
234 if (tsk
->thread
.load_fp
|| msr_tm_active(tsk
->thread
.regs
->msr
)) {
235 load_fp_state(¤t
->thread
.fp_state
);
236 current
->thread
.load_fp
++;
242 static int restore_fp(struct task_struct
*tsk
) { return 0; }
243 #endif /* CONFIG_PPC_FPU */
245 #ifdef CONFIG_ALTIVEC
246 #define loadvec(thr) ((thr).load_vec)
248 static void __giveup_altivec(struct task_struct
*tsk
)
253 msr
= tsk
->thread
.regs
->msr
;
256 if (cpu_has_feature(CPU_FTR_VSX
))
259 tsk
->thread
.regs
->msr
= msr
;
262 void giveup_altivec(struct task_struct
*tsk
)
264 check_if_tm_restore_required(tsk
);
266 msr_check_and_set(MSR_VEC
);
267 __giveup_altivec(tsk
);
268 msr_check_and_clear(MSR_VEC
);
270 EXPORT_SYMBOL(giveup_altivec
);
272 void enable_kernel_altivec(void)
274 unsigned long cpumsr
;
276 WARN_ON(preemptible());
278 cpumsr
= msr_check_and_set(MSR_VEC
);
280 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
281 check_if_tm_restore_required(current
);
283 * If a thread has already been reclaimed then the
284 * checkpointed registers are on the CPU but have definitely
285 * been saved by the reclaim code. Don't need to and *cannot*
286 * giveup as this would save to the 'live' structure not the
287 * checkpointed structure.
289 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
291 __giveup_altivec(current
);
294 EXPORT_SYMBOL(enable_kernel_altivec
);
297 * Make sure the VMX/Altivec register state in the
298 * the thread_struct is up to date for task tsk.
300 void flush_altivec_to_thread(struct task_struct
*tsk
)
302 if (tsk
->thread
.regs
) {
304 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
305 BUG_ON(tsk
!= current
);
311 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
313 static int restore_altivec(struct task_struct
*tsk
)
315 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
316 (tsk
->thread
.load_vec
|| msr_tm_active(tsk
->thread
.regs
->msr
))) {
317 load_vr_state(&tsk
->thread
.vr_state
);
318 tsk
->thread
.used_vr
= 1;
319 tsk
->thread
.load_vec
++;
326 #define loadvec(thr) 0
327 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
328 #endif /* CONFIG_ALTIVEC */
331 static void __giveup_vsx(struct task_struct
*tsk
)
333 if (tsk
->thread
.regs
->msr
& MSR_FP
)
335 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
336 __giveup_altivec(tsk
);
337 tsk
->thread
.regs
->msr
&= ~MSR_VSX
;
340 static void giveup_vsx(struct task_struct
*tsk
)
342 check_if_tm_restore_required(tsk
);
344 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
346 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
349 static void save_vsx(struct task_struct
*tsk
)
351 if (tsk
->thread
.regs
->msr
& MSR_FP
)
353 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
357 void enable_kernel_vsx(void)
359 unsigned long cpumsr
;
361 WARN_ON(preemptible());
363 cpumsr
= msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
365 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VSX
)) {
366 check_if_tm_restore_required(current
);
368 * If a thread has already been reclaimed then the
369 * checkpointed registers are on the CPU but have definitely
370 * been saved by the reclaim code. Don't need to and *cannot*
371 * giveup as this would save to the 'live' structure not the
372 * checkpointed structure.
374 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
376 if (current
->thread
.regs
->msr
& MSR_FP
)
377 __giveup_fpu(current
);
378 if (current
->thread
.regs
->msr
& MSR_VEC
)
379 __giveup_altivec(current
);
380 __giveup_vsx(current
);
383 EXPORT_SYMBOL(enable_kernel_vsx
);
385 void flush_vsx_to_thread(struct task_struct
*tsk
)
387 if (tsk
->thread
.regs
) {
389 if (tsk
->thread
.regs
->msr
& MSR_VSX
) {
390 BUG_ON(tsk
!= current
);
396 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
398 static int restore_vsx(struct task_struct
*tsk
)
400 if (cpu_has_feature(CPU_FTR_VSX
)) {
401 tsk
->thread
.used_vsr
= 1;
408 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
409 static inline void save_vsx(struct task_struct
*tsk
) { }
410 #endif /* CONFIG_VSX */
413 void giveup_spe(struct task_struct
*tsk
)
415 check_if_tm_restore_required(tsk
);
417 msr_check_and_set(MSR_SPE
);
419 msr_check_and_clear(MSR_SPE
);
421 EXPORT_SYMBOL(giveup_spe
);
423 void enable_kernel_spe(void)
425 WARN_ON(preemptible());
427 msr_check_and_set(MSR_SPE
);
429 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
430 check_if_tm_restore_required(current
);
431 __giveup_spe(current
);
434 EXPORT_SYMBOL(enable_kernel_spe
);
436 void flush_spe_to_thread(struct task_struct
*tsk
)
438 if (tsk
->thread
.regs
) {
440 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
441 BUG_ON(tsk
!= current
);
442 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
448 #endif /* CONFIG_SPE */
450 static unsigned long msr_all_available
;
452 static int __init
init_msr_all_available(void)
454 #ifdef CONFIG_PPC_FPU
455 msr_all_available
|= MSR_FP
;
457 #ifdef CONFIG_ALTIVEC
458 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
459 msr_all_available
|= MSR_VEC
;
462 if (cpu_has_feature(CPU_FTR_VSX
))
463 msr_all_available
|= MSR_VSX
;
466 if (cpu_has_feature(CPU_FTR_SPE
))
467 msr_all_available
|= MSR_SPE
;
472 early_initcall(init_msr_all_available
);
474 void giveup_all(struct task_struct
*tsk
)
476 unsigned long usermsr
;
478 if (!tsk
->thread
.regs
)
481 usermsr
= tsk
->thread
.regs
->msr
;
483 if ((usermsr
& msr_all_available
) == 0)
486 msr_check_and_set(msr_all_available
);
487 check_if_tm_restore_required(tsk
);
489 #ifdef CONFIG_PPC_FPU
490 if (usermsr
& MSR_FP
)
493 #ifdef CONFIG_ALTIVEC
494 if (usermsr
& MSR_VEC
)
495 __giveup_altivec(tsk
);
498 if (usermsr
& MSR_VSX
)
502 if (usermsr
& MSR_SPE
)
506 msr_check_and_clear(msr_all_available
);
508 EXPORT_SYMBOL(giveup_all
);
510 void restore_math(struct pt_regs
*regs
)
515 * Syscall exit makes a similar initial check before branching
516 * to restore_math. Keep them in synch.
518 if (!msr_tm_active(regs
->msr
) &&
519 !current
->thread
.load_fp
&& !loadvec(current
->thread
))
523 msr_check_and_set(msr_all_available
);
526 * Only reload if the bit is not set in the user MSR, the bit BEING set
527 * indicates that the registers are hot
529 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
530 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
532 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
535 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
536 restore_vsx(current
)) {
540 msr_check_and_clear(msr_all_available
);
545 void save_all(struct task_struct
*tsk
)
547 unsigned long usermsr
;
549 if (!tsk
->thread
.regs
)
552 usermsr
= tsk
->thread
.regs
->msr
;
554 if ((usermsr
& msr_all_available
) == 0)
557 msr_check_and_set(msr_all_available
);
560 * Saving the way the register space is in hardware, save_vsx boils
561 * down to a save_fpu() and save_altivec()
563 if (usermsr
& MSR_VSX
) {
566 if (usermsr
& MSR_FP
)
569 if (usermsr
& MSR_VEC
)
573 if (usermsr
& MSR_SPE
)
576 msr_check_and_clear(msr_all_available
);
579 void flush_all_to_thread(struct task_struct
*tsk
)
581 if (tsk
->thread
.regs
) {
583 BUG_ON(tsk
!= current
);
587 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
588 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
594 EXPORT_SYMBOL(flush_all_to_thread
);
596 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
597 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
598 unsigned long error_code
, int signal_code
, int breakpt
)
602 current
->thread
.trap_nr
= signal_code
;
603 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
604 11, SIGSEGV
) == NOTIFY_STOP
)
607 /* Deliver the signal to userspace */
608 info
.si_signo
= SIGTRAP
;
609 info
.si_errno
= breakpt
; /* breakpoint or watchpoint id */
610 info
.si_code
= signal_code
;
611 info
.si_addr
= (void __user
*)address
;
612 force_sig_info(SIGTRAP
, &info
, current
);
614 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
615 void do_break (struct pt_regs
*regs
, unsigned long address
,
616 unsigned long error_code
)
620 current
->thread
.trap_nr
= TRAP_HWBKPT
;
621 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
622 11, SIGSEGV
) == NOTIFY_STOP
)
625 if (debugger_break_match(regs
))
628 /* Clear the breakpoint */
629 hw_breakpoint_disable();
631 /* Deliver the signal to userspace */
632 info
.si_signo
= SIGTRAP
;
634 info
.si_code
= TRAP_HWBKPT
;
635 info
.si_addr
= (void __user
*)address
;
636 force_sig_info(SIGTRAP
, &info
, current
);
638 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
640 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
642 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
644 * Set the debug registers back to their default "safe" values.
646 static void set_debug_reg_defaults(struct thread_struct
*thread
)
648 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
649 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
650 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
652 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
653 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
654 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
656 thread
->debug
.dbcr0
= 0;
659 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
661 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
662 DBCR1_IAC3US
| DBCR1_IAC4US
;
664 * Force Data Address Compare User/Supervisor bits to be User-only
665 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
667 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
669 thread
->debug
.dbcr1
= 0;
673 static void prime_debug_regs(struct debug_reg
*debug
)
676 * We could have inherited MSR_DE from userspace, since
677 * it doesn't get cleared on exception entry. Make sure
678 * MSR_DE is clear before we enable any debug events.
680 mtmsr(mfmsr() & ~MSR_DE
);
682 mtspr(SPRN_IAC1
, debug
->iac1
);
683 mtspr(SPRN_IAC2
, debug
->iac2
);
684 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
685 mtspr(SPRN_IAC3
, debug
->iac3
);
686 mtspr(SPRN_IAC4
, debug
->iac4
);
688 mtspr(SPRN_DAC1
, debug
->dac1
);
689 mtspr(SPRN_DAC2
, debug
->dac2
);
690 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
691 mtspr(SPRN_DVC1
, debug
->dvc1
);
692 mtspr(SPRN_DVC2
, debug
->dvc2
);
694 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
695 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
697 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
701 * Unless neither the old or new thread are making use of the
702 * debug registers, set the debug registers from the values
703 * stored in the new thread.
705 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
707 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
708 || (new_debug
->dbcr0
& DBCR0_IDM
))
709 prime_debug_regs(new_debug
);
711 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
712 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
713 #ifndef CONFIG_HAVE_HW_BREAKPOINT
714 static void set_debug_reg_defaults(struct thread_struct
*thread
)
716 thread
->hw_brk
.address
= 0;
717 thread
->hw_brk
.type
= 0;
718 set_breakpoint(&thread
->hw_brk
);
720 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
721 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
723 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
724 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
726 mtspr(SPRN_DAC1
, dabr
);
727 #ifdef CONFIG_PPC_47x
732 #elif defined(CONFIG_PPC_BOOK3S)
733 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
735 mtspr(SPRN_DABR
, dabr
);
736 if (cpu_has_feature(CPU_FTR_DABRX
))
737 mtspr(SPRN_DABRX
, dabrx
);
740 #elif defined(CONFIG_PPC_8xx)
741 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
743 unsigned long addr
= dabr
& ~HW_BRK_TYPE_DABR
;
744 unsigned long lctrl1
= 0x90000000; /* compare type: equal on E & F */
745 unsigned long lctrl2
= 0x8e000002; /* watchpoint 1 on cmp E | F */
747 if ((dabr
& HW_BRK_TYPE_RDWR
) == HW_BRK_TYPE_READ
)
749 else if ((dabr
& HW_BRK_TYPE_RDWR
) == HW_BRK_TYPE_WRITE
)
751 else if ((dabr
& HW_BRK_TYPE_RDWR
) == 0)
754 mtspr(SPRN_LCTRL2
, 0);
755 mtspr(SPRN_CMPE
, addr
);
756 mtspr(SPRN_CMPF
, addr
+ 4);
757 mtspr(SPRN_LCTRL1
, lctrl1
);
758 mtspr(SPRN_LCTRL2
, lctrl2
);
763 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
769 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
771 unsigned long dabr
, dabrx
;
773 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
774 dabrx
= ((brk
->type
>> 3) & 0x7);
777 return ppc_md
.set_dabr(dabr
, dabrx
);
779 return __set_dabr(dabr
, dabrx
);
782 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
784 unsigned long dawr
, dawrx
, mrd
;
788 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
789 << (63 - 58); //* read/write bits */
790 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
791 << (63 - 59); //* translate */
792 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
793 >> 3; //* PRIM bits */
794 /* dawr length is stored in field MDR bits 48:53. Matches range in
795 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
797 brk->len is in bytes.
798 This aligns up to double word size, shifts and does the bias.
800 mrd
= ((brk
->len
+ 7) >> 3) - 1;
801 dawrx
|= (mrd
& 0x3f) << (63 - 53);
804 return ppc_md
.set_dawr(dawr
, dawrx
);
805 mtspr(SPRN_DAWR
, dawr
);
806 mtspr(SPRN_DAWRX
, dawrx
);
810 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
812 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
814 if (cpu_has_feature(CPU_FTR_DAWR
))
820 void set_breakpoint(struct arch_hw_breakpoint
*brk
)
823 __set_breakpoint(brk
);
828 DEFINE_PER_CPU(struct cpu_usage
, cpu_usage_array
);
831 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
832 struct arch_hw_breakpoint
*b
)
834 if (a
->address
!= b
->address
)
836 if (a
->type
!= b
->type
)
838 if (a
->len
!= b
->len
)
843 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
845 static inline bool tm_enabled(struct task_struct
*tsk
)
847 return tsk
&& tsk
->thread
.regs
&& (tsk
->thread
.regs
->msr
& MSR_TM
);
850 static void tm_reclaim_thread(struct thread_struct
*thr
,
851 struct thread_info
*ti
, uint8_t cause
)
854 * Use the current MSR TM suspended bit to track if we have
855 * checkpointed state outstanding.
856 * On signal delivery, we'd normally reclaim the checkpointed
857 * state to obtain stack pointer (see:get_tm_stackpointer()).
858 * This will then directly return to userspace without going
859 * through __switch_to(). However, if the stack frame is bad,
860 * we need to exit this thread which calls __switch_to() which
861 * will again attempt to reclaim the already saved tm state.
862 * Hence we need to check that we've not already reclaimed
864 * We do this using the current MSR, rather tracking it in
865 * some specific thread_struct bit, as it has the additional
866 * benefit of checking for a potential TM bad thing exception.
868 if (!MSR_TM_SUSPENDED(mfmsr()))
872 * If we are in a transaction and FP is off then we can't have
873 * used FP inside that transaction. Hence the checkpointed
874 * state is the same as the live state. We need to copy the
875 * live state to the checkpointed state so that when the
876 * transaction is restored, the checkpointed state is correct
877 * and the aborted transaction sees the correct state. We use
878 * ckpt_regs.msr here as that's what tm_reclaim will use to
879 * determine if it's going to write the checkpointed state or
880 * not. So either this will write the checkpointed registers,
881 * or reclaim will. Similarly for VMX.
883 if ((thr
->ckpt_regs
.msr
& MSR_FP
) == 0)
884 memcpy(&thr
->ckfp_state
, &thr
->fp_state
,
885 sizeof(struct thread_fp_state
));
886 if ((thr
->ckpt_regs
.msr
& MSR_VEC
) == 0)
887 memcpy(&thr
->ckvr_state
, &thr
->vr_state
,
888 sizeof(struct thread_vr_state
));
890 giveup_all(container_of(thr
, struct task_struct
, thread
));
892 tm_reclaim(thr
, thr
->ckpt_regs
.msr
, cause
);
895 void tm_reclaim_current(uint8_t cause
)
898 tm_reclaim_thread(¤t
->thread
, current_thread_info(), cause
);
901 static inline void tm_reclaim_task(struct task_struct
*tsk
)
903 /* We have to work out if we're switching from/to a task that's in the
904 * middle of a transaction.
906 * In switching we need to maintain a 2nd register state as
907 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
908 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
911 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
913 struct thread_struct
*thr
= &tsk
->thread
;
918 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
919 goto out_and_saveregs
;
921 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
922 "ccr=%lx, msr=%lx, trap=%lx)\n",
923 tsk
->pid
, thr
->regs
->nip
,
924 thr
->regs
->ccr
, thr
->regs
->msr
,
927 tm_reclaim_thread(thr
, task_thread_info(tsk
), TM_CAUSE_RESCHED
);
929 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
933 /* Always save the regs here, even if a transaction's not active.
934 * This context-switches a thread's TM info SPRs. We do it here to
935 * be consistent with the restore path (in recheckpoint) which
936 * cannot happen later in _switch().
941 extern void __tm_recheckpoint(struct thread_struct
*thread
,
942 unsigned long orig_msr
);
944 void tm_recheckpoint(struct thread_struct
*thread
,
945 unsigned long orig_msr
)
949 if (!(thread
->regs
->msr
& MSR_TM
))
952 /* We really can't be interrupted here as the TEXASR registers can't
953 * change and later in the trecheckpoint code, we have a userspace R1.
954 * So let's hard disable over this region.
956 local_irq_save(flags
);
959 /* The TM SPRs are restored here, so that TEXASR.FS can be set
960 * before the trecheckpoint and no explosion occurs.
962 tm_restore_sprs(thread
);
964 __tm_recheckpoint(thread
, orig_msr
);
966 local_irq_restore(flags
);
969 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
973 if (!cpu_has_feature(CPU_FTR_TM
))
976 /* Recheckpoint the registers of the thread we're about to switch to.
978 * If the task was using FP, we non-lazily reload both the original and
979 * the speculative FP register states. This is because the kernel
980 * doesn't see if/when a TM rollback occurs, so if we take an FP
981 * unavailable later, we are unable to determine which set of FP regs
982 * need to be restored.
984 if (!tm_enabled(new))
987 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
988 tm_restore_sprs(&new->thread
);
991 msr
= new->thread
.ckpt_regs
.msr
;
992 /* Recheckpoint to restore original checkpointed register state. */
993 TM_DEBUG("*** tm_recheckpoint of pid %d "
994 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
995 new->pid
, new->thread
.regs
->msr
, msr
);
997 tm_recheckpoint(&new->thread
, msr
);
1000 * The checkpointed state has been restored but the live state has
1001 * not, ensure all the math functionality is turned off to trigger
1002 * restore_math() to reload.
1004 new->thread
.regs
->msr
&= ~(MSR_FP
| MSR_VEC
| MSR_VSX
);
1006 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1007 "(kernel msr 0x%lx)\n",
1011 static inline void __switch_to_tm(struct task_struct
*prev
,
1012 struct task_struct
*new)
1014 if (cpu_has_feature(CPU_FTR_TM
)) {
1015 if (tm_enabled(prev
) || tm_enabled(new))
1018 if (tm_enabled(prev
)) {
1019 prev
->thread
.load_tm
++;
1020 tm_reclaim_task(prev
);
1021 if (!MSR_TM_ACTIVE(prev
->thread
.regs
->msr
) && prev
->thread
.load_tm
== 0)
1022 prev
->thread
.regs
->msr
&= ~MSR_TM
;
1025 tm_recheckpoint_new_task(new);
1030 * This is called if we are on the way out to userspace and the
1031 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1032 * FP and/or vector state and does so if necessary.
1033 * If userspace is inside a transaction (whether active or
1034 * suspended) and FP/VMX/VSX instructions have ever been enabled
1035 * inside that transaction, then we have to keep them enabled
1036 * and keep the FP/VMX/VSX state loaded while ever the transaction
1037 * continues. The reason is that if we didn't, and subsequently
1038 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1039 * we don't know whether it's the same transaction, and thus we
1040 * don't know which of the checkpointed state and the transactional
1043 void restore_tm_state(struct pt_regs
*regs
)
1045 unsigned long msr_diff
;
1048 * This is the only moment we should clear TIF_RESTORE_TM as
1049 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1050 * again, anything else could lead to an incorrect ckpt_msr being
1051 * saved and therefore incorrect signal contexts.
1053 clear_thread_flag(TIF_RESTORE_TM
);
1054 if (!MSR_TM_ACTIVE(regs
->msr
))
1057 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
1058 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
1060 /* Ensure that restore_math() will restore */
1061 if (msr_diff
& MSR_FP
)
1062 current
->thread
.load_fp
= 1;
1063 #ifdef CONFIG_ALTIVEC
1064 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && msr_diff
& MSR_VEC
)
1065 current
->thread
.load_vec
= 1;
1069 regs
->msr
|= msr_diff
;
1073 #define tm_recheckpoint_new_task(new)
1074 #define __switch_to_tm(prev, new)
1075 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1077 static inline void save_sprs(struct thread_struct
*t
)
1079 #ifdef CONFIG_ALTIVEC
1080 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
1081 t
->vrsave
= mfspr(SPRN_VRSAVE
);
1083 #ifdef CONFIG_PPC_BOOK3S_64
1084 if (cpu_has_feature(CPU_FTR_DSCR
))
1085 t
->dscr
= mfspr(SPRN_DSCR
);
1087 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1088 t
->bescr
= mfspr(SPRN_BESCR
);
1089 t
->ebbhr
= mfspr(SPRN_EBBHR
);
1090 t
->ebbrr
= mfspr(SPRN_EBBRR
);
1092 t
->fscr
= mfspr(SPRN_FSCR
);
1095 * Note that the TAR is not available for use in the kernel.
1096 * (To provide this, the TAR should be backed up/restored on
1097 * exception entry/exit instead, and be in pt_regs. FIXME,
1098 * this should be in pt_regs anyway (for debug).)
1100 t
->tar
= mfspr(SPRN_TAR
);
1105 static inline void restore_sprs(struct thread_struct
*old_thread
,
1106 struct thread_struct
*new_thread
)
1108 #ifdef CONFIG_ALTIVEC
1109 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
1110 old_thread
->vrsave
!= new_thread
->vrsave
)
1111 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
1113 #ifdef CONFIG_PPC_BOOK3S_64
1114 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1115 u64 dscr
= get_paca()->dscr_default
;
1116 if (new_thread
->dscr_inherit
)
1117 dscr
= new_thread
->dscr
;
1119 if (old_thread
->dscr
!= dscr
)
1120 mtspr(SPRN_DSCR
, dscr
);
1123 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1124 if (old_thread
->bescr
!= new_thread
->bescr
)
1125 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1126 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1127 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1128 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1129 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1131 if (old_thread
->fscr
!= new_thread
->fscr
)
1132 mtspr(SPRN_FSCR
, new_thread
->fscr
);
1134 if (old_thread
->tar
!= new_thread
->tar
)
1135 mtspr(SPRN_TAR
, new_thread
->tar
);
1140 #ifdef CONFIG_PPC_BOOK3S_64
1142 static const u8 dummy_copy_buffer
[CP_SIZE
] __attribute__((aligned(CP_SIZE
)));
1145 struct task_struct
*__switch_to(struct task_struct
*prev
,
1146 struct task_struct
*new)
1148 struct thread_struct
*new_thread
, *old_thread
;
1149 struct task_struct
*last
;
1150 #ifdef CONFIG_PPC_BOOK3S_64
1151 struct ppc64_tlb_batch
*batch
;
1154 new_thread
= &new->thread
;
1155 old_thread
= ¤t
->thread
;
1157 WARN_ON(!irqs_disabled());
1161 * Collect processor utilization data per process
1163 if (firmware_has_feature(FW_FEATURE_SPLPAR
)) {
1164 struct cpu_usage
*cu
= this_cpu_ptr(&cpu_usage_array
);
1165 long unsigned start_tb
, current_tb
;
1166 start_tb
= old_thread
->start_tb
;
1167 cu
->current_tb
= current_tb
= mfspr(SPRN_PURR
);
1168 old_thread
->accum_tb
+= (current_tb
- start_tb
);
1169 new_thread
->start_tb
= current_tb
;
1171 #endif /* CONFIG_PPC64 */
1173 #ifdef CONFIG_PPC_STD_MMU_64
1174 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1175 if (batch
->active
) {
1176 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1178 __flush_tlb_pending(batch
);
1181 #endif /* CONFIG_PPC_STD_MMU_64 */
1183 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1184 switch_booke_debug_regs(&new->thread
.debug
);
1187 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1190 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1191 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1192 __set_breakpoint(&new->thread
.hw_brk
);
1193 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1197 * We need to save SPRs before treclaim/trecheckpoint as these will
1198 * change a number of them.
1200 save_sprs(&prev
->thread
);
1202 /* Save FPU, Altivec, VSX and SPE state */
1205 __switch_to_tm(prev
, new);
1207 if (!radix_enabled()) {
1209 * We can't take a PMU exception inside _switch() since there
1210 * is a window where the kernel stack SLB and the kernel stack
1211 * are out of sync. Hard disable here.
1217 * Call restore_sprs() before calling _switch(). If we move it after
1218 * _switch() then we miss out on calling it for new tasks. The reason
1219 * for this is we manually create a stack frame for new tasks that
1220 * directly returns through ret_from_fork() or
1221 * ret_from_kernel_thread(). See copy_thread() for details.
1223 restore_sprs(old_thread
, new_thread
);
1225 last
= _switch(old_thread
, new_thread
);
1227 #ifdef CONFIG_PPC_STD_MMU_64
1228 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1229 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1230 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1234 if (current_thread_info()->task
->thread
.regs
) {
1235 restore_math(current_thread_info()->task
->thread
.regs
);
1238 * The copy-paste buffer can only store into foreign real
1239 * addresses, so unprivileged processes can not see the
1240 * data or use it in any way unless they have foreign real
1241 * mappings. We don't have a VAS driver that allocates those
1242 * yet, so no cpabort is required.
1244 if (cpu_has_feature(CPU_FTR_POWER9_DD1
)) {
1246 * DD1 allows paste into normal system memory, so we
1247 * do an unpaired copy here to clear the buffer and
1248 * prevent a covert channel being set up.
1250 * cpabort is not used because it is quite expensive.
1252 asm volatile(PPC_COPY(%0, %1)
1253 : : "r"(dummy_copy_buffer
), "r"(0));
1256 #endif /* CONFIG_PPC_STD_MMU_64 */
1261 static int instructions_to_print
= 16;
1263 static void show_instructions(struct pt_regs
*regs
)
1266 unsigned long pc
= regs
->nip
- (instructions_to_print
* 3 / 4 *
1269 printk("Instruction dump:");
1271 for (i
= 0; i
< instructions_to_print
; i
++) {
1277 #if !defined(CONFIG_BOOKE)
1278 /* If executing with the IMMU off, adjust pc rather
1279 * than print XXXXXXXX.
1281 if (!(regs
->msr
& MSR_IR
))
1282 pc
= (unsigned long)phys_to_virt(pc
);
1285 if (!__kernel_text_address(pc
) ||
1286 probe_kernel_address((unsigned int __user
*)pc
, instr
)) {
1287 pr_cont("XXXXXXXX ");
1289 if (regs
->nip
== pc
)
1290 pr_cont("<%08x> ", instr
);
1292 pr_cont("%08x ", instr
);
1306 static struct regbit msr_bits
[] = {
1307 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1329 #ifndef CONFIG_BOOKE
1336 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1340 for (; bits
->bit
; ++bits
)
1341 if (val
& bits
->bit
) {
1342 pr_cont("%s%s", s
, bits
->name
);
1347 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1348 static struct regbit msr_tm_bits
[] = {
1355 static void print_tm_bits(unsigned long val
)
1358 * This only prints something if at least one of the TM bit is set.
1359 * Inside the TM[], the output means:
1360 * E: Enabled (bit 32)
1361 * S: Suspended (bit 33)
1362 * T: Transactional (bit 34)
1364 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1366 print_bits(val
, msr_tm_bits
, "");
1371 static void print_tm_bits(unsigned long val
) {}
1374 static void print_msr_bits(unsigned long val
)
1377 print_bits(val
, msr_bits
, ",");
1383 #define REG "%016lx"
1384 #define REGS_PER_LINE 4
1385 #define LAST_VOLATILE 13
1388 #define REGS_PER_LINE 8
1389 #define LAST_VOLATILE 12
1392 void show_regs(struct pt_regs
* regs
)
1396 show_regs_print_info(KERN_DEFAULT
);
1398 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1399 regs
->nip
, regs
->link
, regs
->ctr
);
1400 printk("REGS: %p TRAP: %04lx %s (%s)\n",
1401 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1402 printk("MSR: "REG
" ", regs
->msr
);
1403 print_msr_bits(regs
->msr
);
1404 printk(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1406 if ((regs
->trap
!= 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1407 pr_cont("CFAR: "REG
" ", regs
->orig_gpr3
);
1408 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1409 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1410 pr_cont("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1412 pr_cont("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1415 pr_cont("SOFTE: %ld ", regs
->softe
);
1417 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1418 if (MSR_TM_ACTIVE(regs
->msr
))
1419 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1422 for (i
= 0; i
< 32; i
++) {
1423 if ((i
% REGS_PER_LINE
) == 0)
1424 pr_cont("\nGPR%02d: ", i
);
1425 pr_cont(REG
" ", regs
->gpr
[i
]);
1426 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1430 #ifdef CONFIG_KALLSYMS
1432 * Lookup NIP late so we have the best change of getting the
1433 * above info out without failing
1435 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1436 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1438 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1439 if (!user_mode(regs
))
1440 show_instructions(regs
);
1443 void flush_thread(void)
1445 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1446 flush_ptrace_hw_breakpoint(current
);
1447 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1448 set_debug_reg_defaults(¤t
->thread
);
1449 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1453 release_thread(struct task_struct
*t
)
1458 * this gets called so that we can store coprocessor state into memory and
1459 * copy the current task into the new thread.
1461 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1463 flush_all_to_thread(src
);
1465 * Flush TM state out so we can copy it. __switch_to_tm() does this
1466 * flush but it removes the checkpointed state from the current CPU and
1467 * transitions the CPU out of TM mode. Hence we need to call
1468 * tm_recheckpoint_new_task() (on the same task) to restore the
1469 * checkpointed state back and the TM mode.
1471 * Can't pass dst because it isn't ready. Doesn't matter, passing
1472 * dst is only important for __switch_to()
1474 __switch_to_tm(src
, src
);
1478 clear_task_ebb(dst
);
1483 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1485 #ifdef CONFIG_PPC_STD_MMU_64
1486 unsigned long sp_vsid
;
1487 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1489 if (radix_enabled())
1492 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1493 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1494 << SLB_VSID_SHIFT_1T
;
1496 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1498 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1499 p
->thread
.ksp_vsid
= sp_vsid
;
1508 * Copy architecture-specific thread state
1510 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1511 unsigned long kthread_arg
, struct task_struct
*p
)
1513 struct pt_regs
*childregs
, *kregs
;
1514 extern void ret_from_fork(void);
1515 extern void ret_from_kernel_thread(void);
1517 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1518 struct thread_info
*ti
= task_thread_info(p
);
1520 klp_init_thread_info(ti
);
1522 /* Copy registers */
1523 sp
-= sizeof(struct pt_regs
);
1524 childregs
= (struct pt_regs
*) sp
;
1525 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1527 memset(childregs
, 0, sizeof(struct pt_regs
));
1528 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1531 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1533 clear_tsk_thread_flag(p
, TIF_32BIT
);
1534 childregs
->softe
= 1;
1536 childregs
->gpr
[15] = kthread_arg
;
1537 p
->thread
.regs
= NULL
; /* no user register state */
1538 ti
->flags
|= _TIF_RESTOREALL
;
1539 f
= ret_from_kernel_thread
;
1542 struct pt_regs
*regs
= current_pt_regs();
1543 CHECK_FULL_REGS(regs
);
1546 childregs
->gpr
[1] = usp
;
1547 p
->thread
.regs
= childregs
;
1548 childregs
->gpr
[3] = 0; /* Result from fork() */
1549 if (clone_flags
& CLONE_SETTLS
) {
1551 if (!is_32bit_task())
1552 childregs
->gpr
[13] = childregs
->gpr
[6];
1555 childregs
->gpr
[2] = childregs
->gpr
[6];
1560 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1561 sp
-= STACK_FRAME_OVERHEAD
;
1564 * The way this works is that at some point in the future
1565 * some task will call _switch to switch to the new task.
1566 * That will pop off the stack frame created below and start
1567 * the new task running at ret_from_fork. The new task will
1568 * do some house keeping and then return from the fork or clone
1569 * system call, using the stack frame created above.
1571 ((unsigned long *)sp
)[0] = 0;
1572 sp
-= sizeof(struct pt_regs
);
1573 kregs
= (struct pt_regs
*) sp
;
1574 sp
-= STACK_FRAME_OVERHEAD
;
1577 p
->thread
.ksp_limit
= (unsigned long)task_stack_page(p
) +
1578 _ALIGN_UP(sizeof(struct thread_info
), 16);
1580 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1581 p
->thread
.ptrace_bps
[0] = NULL
;
1584 p
->thread
.fp_save_area
= NULL
;
1585 #ifdef CONFIG_ALTIVEC
1586 p
->thread
.vr_save_area
= NULL
;
1589 setup_ksp_vsid(p
, sp
);
1592 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1593 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1594 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1596 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1597 p
->thread
.ppr
= INIT_PPR
;
1599 kregs
->nip
= ppc_function_entry(f
);
1604 * Set up a thread for executing a new program
1606 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1609 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1613 * If we exec out of a kernel thread then thread.regs will not be
1616 if (!current
->thread
.regs
) {
1617 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1618 current
->thread
.regs
= regs
- 1;
1621 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1623 * Clear any transactional state, we're exec()ing. The cause is
1624 * not important as there will never be a recheckpoint so it's not
1627 if (MSR_TM_SUSPENDED(mfmsr()))
1628 tm_reclaim_current(0);
1631 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1639 * We have just cleared all the nonvolatile GPRs, so make
1640 * FULL_REGS(regs) return true. This is necessary to allow
1641 * ptrace to examine the thread immediately after exec.
1648 regs
->msr
= MSR_USER
;
1650 if (!is_32bit_task()) {
1651 unsigned long entry
;
1653 if (is_elf2_task()) {
1654 /* Look ma, no function descriptors! */
1659 * The latest iteration of the ABI requires that when
1660 * calling a function (at its global entry point),
1661 * the caller must ensure r12 holds the entry point
1662 * address (so that the function can quickly
1663 * establish addressability).
1665 regs
->gpr
[12] = start
;
1666 /* Make sure that's restored on entry to userspace. */
1667 set_thread_flag(TIF_RESTOREALL
);
1671 /* start is a relocated pointer to the function
1672 * descriptor for the elf _start routine. The first
1673 * entry in the function descriptor is the entry
1674 * address of _start and the second entry is the TOC
1675 * value we need to use.
1677 __get_user(entry
, (unsigned long __user
*)start
);
1678 __get_user(toc
, (unsigned long __user
*)start
+1);
1680 /* Check whether the e_entry function descriptor entries
1681 * need to be relocated before we can use them.
1683 if (load_addr
!= 0) {
1690 regs
->msr
= MSR_USER64
;
1694 regs
->msr
= MSR_USER32
;
1698 current
->thread
.used_vsr
= 0;
1700 current
->thread
.load_fp
= 0;
1701 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1702 current
->thread
.fp_save_area
= NULL
;
1703 #ifdef CONFIG_ALTIVEC
1704 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1705 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1706 current
->thread
.vr_save_area
= NULL
;
1707 current
->thread
.vrsave
= 0;
1708 current
->thread
.used_vr
= 0;
1709 current
->thread
.load_vec
= 0;
1710 #endif /* CONFIG_ALTIVEC */
1712 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1713 current
->thread
.acc
= 0;
1714 current
->thread
.spefscr
= 0;
1715 current
->thread
.used_spe
= 0;
1716 #endif /* CONFIG_SPE */
1717 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1718 current
->thread
.tm_tfhar
= 0;
1719 current
->thread
.tm_texasr
= 0;
1720 current
->thread
.tm_tfiar
= 0;
1721 current
->thread
.load_tm
= 0;
1722 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1724 EXPORT_SYMBOL(start_thread
);
1726 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1727 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1729 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1731 struct pt_regs
*regs
= tsk
->thread
.regs
;
1733 /* This is a bit hairy. If we are an SPE enabled processor
1734 * (have embedded fp) we store the IEEE exception enable flags in
1735 * fpexc_mode. fpexc_mode is also used for setting FP exception
1736 * mode (asyn, precise, disabled) for 'Classic' FP. */
1737 if (val
& PR_FP_EXC_SW_ENABLE
) {
1739 if (cpu_has_feature(CPU_FTR_SPE
)) {
1741 * When the sticky exception bits are set
1742 * directly by userspace, it must call prctl
1743 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1744 * in the existing prctl settings) or
1745 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1746 * the bits being set). <fenv.h> functions
1747 * saving and restoring the whole
1748 * floating-point environment need to do so
1749 * anyway to restore the prctl settings from
1750 * the saved environment.
1752 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1753 tsk
->thread
.fpexc_mode
= val
&
1754 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1764 /* on a CONFIG_SPE this does not hurt us. The bits that
1765 * __pack_fe01 use do not overlap with bits used for
1766 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1767 * on CONFIG_SPE implementations are reserved so writing to
1768 * them does not change anything */
1769 if (val
> PR_FP_EXC_PRECISE
)
1771 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1772 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1773 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1774 | tsk
->thread
.fpexc_mode
;
1778 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1782 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1784 if (cpu_has_feature(CPU_FTR_SPE
)) {
1786 * When the sticky exception bits are set
1787 * directly by userspace, it must call prctl
1788 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1789 * in the existing prctl settings) or
1790 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1791 * the bits being set). <fenv.h> functions
1792 * saving and restoring the whole
1793 * floating-point environment need to do so
1794 * anyway to restore the prctl settings from
1795 * the saved environment.
1797 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1798 val
= tsk
->thread
.fpexc_mode
;
1805 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1806 return put_user(val
, (unsigned int __user
*) adr
);
1809 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1811 struct pt_regs
*regs
= tsk
->thread
.regs
;
1813 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1814 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1820 if (val
== PR_ENDIAN_BIG
)
1821 regs
->msr
&= ~MSR_LE
;
1822 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1823 regs
->msr
|= MSR_LE
;
1830 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1832 struct pt_regs
*regs
= tsk
->thread
.regs
;
1835 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1836 !cpu_has_feature(CPU_FTR_REAL_LE
))
1842 if (regs
->msr
& MSR_LE
) {
1843 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1844 val
= PR_ENDIAN_LITTLE
;
1846 val
= PR_ENDIAN_PPC_LITTLE
;
1848 val
= PR_ENDIAN_BIG
;
1850 return put_user(val
, (unsigned int __user
*)adr
);
1853 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1855 tsk
->thread
.align_ctl
= val
;
1859 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1861 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1864 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1865 unsigned long nbytes
)
1867 unsigned long stack_page
;
1868 unsigned long cpu
= task_cpu(p
);
1871 * Avoid crashing if the stack has overflowed and corrupted
1872 * task_cpu(p), which is in the thread_info struct.
1874 if (cpu
< NR_CPUS
&& cpu_possible(cpu
)) {
1875 stack_page
= (unsigned long) hardirq_ctx
[cpu
];
1876 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1877 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1880 stack_page
= (unsigned long) softirq_ctx
[cpu
];
1881 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1882 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1888 int validate_sp(unsigned long sp
, struct task_struct
*p
,
1889 unsigned long nbytes
)
1891 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
1893 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1894 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1897 return valid_irq_stack(sp
, p
, nbytes
);
1900 EXPORT_SYMBOL(validate_sp
);
1902 unsigned long get_wchan(struct task_struct
*p
)
1904 unsigned long ip
, sp
;
1907 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
1911 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1915 sp
= *(unsigned long *)sp
;
1916 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1919 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
1920 if (!in_sched_functions(ip
))
1923 } while (count
++ < 16);
1927 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
1929 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
1931 unsigned long sp
, ip
, lr
, newsp
;
1934 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1935 int curr_frame
= current
->curr_ret_stack
;
1936 extern void return_to_handler(void);
1937 unsigned long rth
= (unsigned long)return_to_handler
;
1940 sp
= (unsigned long) stack
;
1945 sp
= current_stack_pointer();
1947 sp
= tsk
->thread
.ksp
;
1951 printk("Call Trace:\n");
1953 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
1956 stack
= (unsigned long *) sp
;
1958 ip
= stack
[STACK_FRAME_LR_SAVE
];
1959 if (!firstframe
|| ip
!= lr
) {
1960 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
1961 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1962 if ((ip
== rth
) && curr_frame
>= 0) {
1964 (void *)current
->ret_stack
[curr_frame
].ret
);
1969 pr_cont(" (unreliable)");
1975 * See if this is an exception frame.
1976 * We look for the "regshere" marker in the current frame.
1978 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
1979 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
1980 struct pt_regs
*regs
= (struct pt_regs
*)
1981 (sp
+ STACK_FRAME_OVERHEAD
);
1983 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
1984 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
1989 } while (count
++ < kstack_depth_to_print
);
1993 /* Called with hard IRQs off */
1994 void notrace
__ppc64_runlatch_on(void)
1996 struct thread_info
*ti
= current_thread_info();
1999 ctrl
= mfspr(SPRN_CTRLF
);
2000 ctrl
|= CTRL_RUNLATCH
;
2001 mtspr(SPRN_CTRLT
, ctrl
);
2003 ti
->local_flags
|= _TLF_RUNLATCH
;
2006 /* Called with hard IRQs off */
2007 void notrace
__ppc64_runlatch_off(void)
2009 struct thread_info
*ti
= current_thread_info();
2012 ti
->local_flags
&= ~_TLF_RUNLATCH
;
2014 ctrl
= mfspr(SPRN_CTRLF
);
2015 ctrl
&= ~CTRL_RUNLATCH
;
2016 mtspr(SPRN_CTRLT
, ctrl
);
2018 #endif /* CONFIG_PPC64 */
2020 unsigned long arch_align_stack(unsigned long sp
)
2022 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
2023 sp
-= get_random_int() & ~PAGE_MASK
;
2027 static inline unsigned long brk_rnd(void)
2029 unsigned long rnd
= 0;
2031 /* 8MB for 32bit, 1GB for 64bit */
2032 if (is_32bit_task())
2033 rnd
= (get_random_long() % (1UL<<(23-PAGE_SHIFT
)));
2035 rnd
= (get_random_long() % (1UL<<(30-PAGE_SHIFT
)));
2037 return rnd
<< PAGE_SHIFT
;
2040 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
2042 unsigned long base
= mm
->brk
;
2045 #ifdef CONFIG_PPC_STD_MMU_64
2047 * If we are using 1TB segments and we are allowed to randomise
2048 * the heap, we can put it above 1TB so it is backed by a 1TB
2049 * segment. Otherwise the heap will be in the bottom 1TB
2050 * which always uses 256MB segments and this may result in a
2051 * performance penalty. We don't need to worry about radix. For
2052 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2054 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
2055 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
2058 ret
= PAGE_ALIGN(base
+ brk_rnd());