2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/sched/debug.h>
20 #include <linux/sched/task.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/kernel.h>
24 #include <linux/smp.h>
25 #include <linux/stddef.h>
26 #include <linux/unistd.h>
27 #include <linux/ptrace.h>
28 #include <linux/slab.h>
29 #include <linux/user.h>
30 #include <linux/elf.h>
31 #include <linux/prctl.h>
32 #include <linux/init_task.h>
33 #include <linux/export.h>
34 #include <linux/kallsyms.h>
35 #include <linux/mqueue.h>
36 #include <linux/hardirq.h>
37 #include <linux/utsname.h>
38 #include <linux/ftrace.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/personality.h>
41 #include <linux/random.h>
42 #include <linux/hw_breakpoint.h>
43 #include <linux/uaccess.h>
44 #include <linux/elf-randomize.h>
46 #include <asm/pgtable.h>
48 #include <asm/processor.h>
51 #include <asm/machdep.h>
53 #include <asm/runlatch.h>
54 #include <asm/syscalls.h>
55 #include <asm/switch_to.h>
57 #include <asm/debug.h>
59 #include <asm/firmware.h>
61 #include <asm/code-patching.h>
63 #include <asm/livepatch.h>
64 #include <asm/cpu_has_feature.h>
65 #include <asm/asm-prototypes.h>
67 #include <linux/kprobes.h>
68 #include <linux/kdebug.h>
70 /* Transactional Memory debug */
72 #define TM_DEBUG(x...) printk(KERN_INFO x)
74 #define TM_DEBUG(x...) do { } while(0)
77 extern unsigned long _get_SP(void);
79 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
80 static void check_if_tm_restore_required(struct task_struct
*tsk
)
83 * If we are saving the current thread's registers, and the
84 * thread is in a transactional state, set the TIF_RESTORE_TM
85 * bit so that we know to restore the registers before
86 * returning to userspace.
88 if (tsk
== current
&& tsk
->thread
.regs
&&
89 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
90 !test_thread_flag(TIF_RESTORE_TM
)) {
91 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
92 set_thread_flag(TIF_RESTORE_TM
);
96 static inline bool msr_tm_active(unsigned long msr
)
98 return MSR_TM_ACTIVE(msr
);
101 static inline bool msr_tm_active(unsigned long msr
) { return false; }
102 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
103 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
105 bool strict_msr_control
;
106 EXPORT_SYMBOL(strict_msr_control
);
108 static int __init
enable_strict_msr_control(char *str
)
110 strict_msr_control
= true;
111 pr_info("Enabling strict facility control\n");
115 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
117 unsigned long msr_check_and_set(unsigned long bits
)
119 unsigned long oldmsr
= mfmsr();
120 unsigned long newmsr
;
122 newmsr
= oldmsr
| bits
;
125 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
129 if (oldmsr
!= newmsr
)
135 void __msr_check_and_clear(unsigned long bits
)
137 unsigned long oldmsr
= mfmsr();
138 unsigned long newmsr
;
140 newmsr
= oldmsr
& ~bits
;
143 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
147 if (oldmsr
!= newmsr
)
150 EXPORT_SYMBOL(__msr_check_and_clear
);
152 #ifdef CONFIG_PPC_FPU
153 void __giveup_fpu(struct task_struct
*tsk
)
158 msr
= tsk
->thread
.regs
->msr
;
161 if (cpu_has_feature(CPU_FTR_VSX
))
164 tsk
->thread
.regs
->msr
= msr
;
167 void giveup_fpu(struct task_struct
*tsk
)
169 check_if_tm_restore_required(tsk
);
171 msr_check_and_set(MSR_FP
);
173 msr_check_and_clear(MSR_FP
);
175 EXPORT_SYMBOL(giveup_fpu
);
178 * Make sure the floating-point register state in the
179 * the thread_struct is up to date for task tsk.
181 void flush_fp_to_thread(struct task_struct
*tsk
)
183 if (tsk
->thread
.regs
) {
185 * We need to disable preemption here because if we didn't,
186 * another process could get scheduled after the regs->msr
187 * test but before we have finished saving the FP registers
188 * to the thread_struct. That process could take over the
189 * FPU, and then when we get scheduled again we would store
190 * bogus values for the remaining FP registers.
193 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
195 * This should only ever be called for current or
196 * for a stopped child process. Since we save away
197 * the FP register state on context switch,
198 * there is something wrong if a stopped child appears
199 * to still have its FP state in the CPU registers.
201 BUG_ON(tsk
!= current
);
207 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
209 void enable_kernel_fp(void)
211 unsigned long cpumsr
;
213 WARN_ON(preemptible());
215 cpumsr
= msr_check_and_set(MSR_FP
);
217 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
218 check_if_tm_restore_required(current
);
220 * If a thread has already been reclaimed then the
221 * checkpointed registers are on the CPU but have definitely
222 * been saved by the reclaim code. Don't need to and *cannot*
223 * giveup as this would save to the 'live' structure not the
224 * checkpointed structure.
226 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
228 __giveup_fpu(current
);
231 EXPORT_SYMBOL(enable_kernel_fp
);
233 static int restore_fp(struct task_struct
*tsk
) {
234 if (tsk
->thread
.load_fp
|| msr_tm_active(tsk
->thread
.regs
->msr
)) {
235 load_fp_state(¤t
->thread
.fp_state
);
236 current
->thread
.load_fp
++;
242 static int restore_fp(struct task_struct
*tsk
) { return 0; }
243 #endif /* CONFIG_PPC_FPU */
245 #ifdef CONFIG_ALTIVEC
246 #define loadvec(thr) ((thr).load_vec)
248 static void __giveup_altivec(struct task_struct
*tsk
)
253 msr
= tsk
->thread
.regs
->msr
;
256 if (cpu_has_feature(CPU_FTR_VSX
))
259 tsk
->thread
.regs
->msr
= msr
;
262 void giveup_altivec(struct task_struct
*tsk
)
264 check_if_tm_restore_required(tsk
);
266 msr_check_and_set(MSR_VEC
);
267 __giveup_altivec(tsk
);
268 msr_check_and_clear(MSR_VEC
);
270 EXPORT_SYMBOL(giveup_altivec
);
272 void enable_kernel_altivec(void)
274 unsigned long cpumsr
;
276 WARN_ON(preemptible());
278 cpumsr
= msr_check_and_set(MSR_VEC
);
280 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
281 check_if_tm_restore_required(current
);
283 * If a thread has already been reclaimed then the
284 * checkpointed registers are on the CPU but have definitely
285 * been saved by the reclaim code. Don't need to and *cannot*
286 * giveup as this would save to the 'live' structure not the
287 * checkpointed structure.
289 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
291 __giveup_altivec(current
);
294 EXPORT_SYMBOL(enable_kernel_altivec
);
297 * Make sure the VMX/Altivec register state in the
298 * the thread_struct is up to date for task tsk.
300 void flush_altivec_to_thread(struct task_struct
*tsk
)
302 if (tsk
->thread
.regs
) {
304 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
305 BUG_ON(tsk
!= current
);
311 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
313 static int restore_altivec(struct task_struct
*tsk
)
315 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
316 (tsk
->thread
.load_vec
|| msr_tm_active(tsk
->thread
.regs
->msr
))) {
317 load_vr_state(&tsk
->thread
.vr_state
);
318 tsk
->thread
.used_vr
= 1;
319 tsk
->thread
.load_vec
++;
326 #define loadvec(thr) 0
327 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
328 #endif /* CONFIG_ALTIVEC */
331 static void __giveup_vsx(struct task_struct
*tsk
)
333 if (tsk
->thread
.regs
->msr
& MSR_FP
)
335 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
336 __giveup_altivec(tsk
);
337 tsk
->thread
.regs
->msr
&= ~MSR_VSX
;
340 static void giveup_vsx(struct task_struct
*tsk
)
342 check_if_tm_restore_required(tsk
);
344 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
346 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
349 static void save_vsx(struct task_struct
*tsk
)
351 if (tsk
->thread
.regs
->msr
& MSR_FP
)
353 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
357 void enable_kernel_vsx(void)
359 unsigned long cpumsr
;
361 WARN_ON(preemptible());
363 cpumsr
= msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
365 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VSX
)) {
366 check_if_tm_restore_required(current
);
368 * If a thread has already been reclaimed then the
369 * checkpointed registers are on the CPU but have definitely
370 * been saved by the reclaim code. Don't need to and *cannot*
371 * giveup as this would save to the 'live' structure not the
372 * checkpointed structure.
374 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
376 if (current
->thread
.regs
->msr
& MSR_FP
)
377 __giveup_fpu(current
);
378 if (current
->thread
.regs
->msr
& MSR_VEC
)
379 __giveup_altivec(current
);
380 __giveup_vsx(current
);
383 EXPORT_SYMBOL(enable_kernel_vsx
);
385 void flush_vsx_to_thread(struct task_struct
*tsk
)
387 if (tsk
->thread
.regs
) {
389 if (tsk
->thread
.regs
->msr
& MSR_VSX
) {
390 BUG_ON(tsk
!= current
);
396 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
398 static int restore_vsx(struct task_struct
*tsk
)
400 if (cpu_has_feature(CPU_FTR_VSX
)) {
401 tsk
->thread
.used_vsr
= 1;
408 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
409 static inline void save_vsx(struct task_struct
*tsk
) { }
410 #endif /* CONFIG_VSX */
413 void giveup_spe(struct task_struct
*tsk
)
415 check_if_tm_restore_required(tsk
);
417 msr_check_and_set(MSR_SPE
);
419 msr_check_and_clear(MSR_SPE
);
421 EXPORT_SYMBOL(giveup_spe
);
423 void enable_kernel_spe(void)
425 WARN_ON(preemptible());
427 msr_check_and_set(MSR_SPE
);
429 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
430 check_if_tm_restore_required(current
);
431 __giveup_spe(current
);
434 EXPORT_SYMBOL(enable_kernel_spe
);
436 void flush_spe_to_thread(struct task_struct
*tsk
)
438 if (tsk
->thread
.regs
) {
440 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
441 BUG_ON(tsk
!= current
);
442 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
448 #endif /* CONFIG_SPE */
450 static unsigned long msr_all_available
;
452 static int __init
init_msr_all_available(void)
454 #ifdef CONFIG_PPC_FPU
455 msr_all_available
|= MSR_FP
;
457 #ifdef CONFIG_ALTIVEC
458 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
459 msr_all_available
|= MSR_VEC
;
462 if (cpu_has_feature(CPU_FTR_VSX
))
463 msr_all_available
|= MSR_VSX
;
466 if (cpu_has_feature(CPU_FTR_SPE
))
467 msr_all_available
|= MSR_SPE
;
472 early_initcall(init_msr_all_available
);
474 void giveup_all(struct task_struct
*tsk
)
476 unsigned long usermsr
;
478 if (!tsk
->thread
.regs
)
481 usermsr
= tsk
->thread
.regs
->msr
;
483 if ((usermsr
& msr_all_available
) == 0)
486 msr_check_and_set(msr_all_available
);
487 check_if_tm_restore_required(tsk
);
489 #ifdef CONFIG_PPC_FPU
490 if (usermsr
& MSR_FP
)
493 #ifdef CONFIG_ALTIVEC
494 if (usermsr
& MSR_VEC
)
495 __giveup_altivec(tsk
);
498 if (usermsr
& MSR_VSX
)
502 if (usermsr
& MSR_SPE
)
506 msr_check_and_clear(msr_all_available
);
508 EXPORT_SYMBOL(giveup_all
);
510 void restore_math(struct pt_regs
*regs
)
514 if (!msr_tm_active(regs
->msr
) &&
515 !current
->thread
.load_fp
&& !loadvec(current
->thread
))
519 msr_check_and_set(msr_all_available
);
522 * Only reload if the bit is not set in the user MSR, the bit BEING set
523 * indicates that the registers are hot
525 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
526 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
528 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
531 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
532 restore_vsx(current
)) {
536 msr_check_and_clear(msr_all_available
);
541 void save_all(struct task_struct
*tsk
)
543 unsigned long usermsr
;
545 if (!tsk
->thread
.regs
)
548 usermsr
= tsk
->thread
.regs
->msr
;
550 if ((usermsr
& msr_all_available
) == 0)
553 msr_check_and_set(msr_all_available
);
556 * Saving the way the register space is in hardware, save_vsx boils
557 * down to a save_fpu() and save_altivec()
559 if (usermsr
& MSR_VSX
) {
562 if (usermsr
& MSR_FP
)
565 if (usermsr
& MSR_VEC
)
569 if (usermsr
& MSR_SPE
)
572 msr_check_and_clear(msr_all_available
);
575 void flush_all_to_thread(struct task_struct
*tsk
)
577 if (tsk
->thread
.regs
) {
579 BUG_ON(tsk
!= current
);
583 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
584 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
590 EXPORT_SYMBOL(flush_all_to_thread
);
592 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
593 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
594 unsigned long error_code
, int signal_code
, int breakpt
)
598 current
->thread
.trap_nr
= signal_code
;
599 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
600 11, SIGSEGV
) == NOTIFY_STOP
)
603 /* Deliver the signal to userspace */
604 info
.si_signo
= SIGTRAP
;
605 info
.si_errno
= breakpt
; /* breakpoint or watchpoint id */
606 info
.si_code
= signal_code
;
607 info
.si_addr
= (void __user
*)address
;
608 force_sig_info(SIGTRAP
, &info
, current
);
610 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
611 void do_break (struct pt_regs
*regs
, unsigned long address
,
612 unsigned long error_code
)
616 current
->thread
.trap_nr
= TRAP_HWBKPT
;
617 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
618 11, SIGSEGV
) == NOTIFY_STOP
)
621 if (debugger_break_match(regs
))
624 /* Clear the breakpoint */
625 hw_breakpoint_disable();
627 /* Deliver the signal to userspace */
628 info
.si_signo
= SIGTRAP
;
630 info
.si_code
= TRAP_HWBKPT
;
631 info
.si_addr
= (void __user
*)address
;
632 force_sig_info(SIGTRAP
, &info
, current
);
634 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
636 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
638 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
640 * Set the debug registers back to their default "safe" values.
642 static void set_debug_reg_defaults(struct thread_struct
*thread
)
644 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
645 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
646 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
648 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
649 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
650 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
652 thread
->debug
.dbcr0
= 0;
655 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
657 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
658 DBCR1_IAC3US
| DBCR1_IAC4US
;
660 * Force Data Address Compare User/Supervisor bits to be User-only
661 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
663 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
665 thread
->debug
.dbcr1
= 0;
669 static void prime_debug_regs(struct debug_reg
*debug
)
672 * We could have inherited MSR_DE from userspace, since
673 * it doesn't get cleared on exception entry. Make sure
674 * MSR_DE is clear before we enable any debug events.
676 mtmsr(mfmsr() & ~MSR_DE
);
678 mtspr(SPRN_IAC1
, debug
->iac1
);
679 mtspr(SPRN_IAC2
, debug
->iac2
);
680 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
681 mtspr(SPRN_IAC3
, debug
->iac3
);
682 mtspr(SPRN_IAC4
, debug
->iac4
);
684 mtspr(SPRN_DAC1
, debug
->dac1
);
685 mtspr(SPRN_DAC2
, debug
->dac2
);
686 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
687 mtspr(SPRN_DVC1
, debug
->dvc1
);
688 mtspr(SPRN_DVC2
, debug
->dvc2
);
690 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
691 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
693 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
697 * Unless neither the old or new thread are making use of the
698 * debug registers, set the debug registers from the values
699 * stored in the new thread.
701 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
703 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
704 || (new_debug
->dbcr0
& DBCR0_IDM
))
705 prime_debug_regs(new_debug
);
707 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
708 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
709 #ifndef CONFIG_HAVE_HW_BREAKPOINT
710 static void set_debug_reg_defaults(struct thread_struct
*thread
)
712 thread
->hw_brk
.address
= 0;
713 thread
->hw_brk
.type
= 0;
714 set_breakpoint(&thread
->hw_brk
);
716 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
717 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
719 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
720 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
722 mtspr(SPRN_DAC1
, dabr
);
723 #ifdef CONFIG_PPC_47x
728 #elif defined(CONFIG_PPC_BOOK3S)
729 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
731 mtspr(SPRN_DABR
, dabr
);
732 if (cpu_has_feature(CPU_FTR_DABRX
))
733 mtspr(SPRN_DABRX
, dabrx
);
736 #elif defined(CONFIG_PPC_8xx)
737 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
739 unsigned long addr
= dabr
& ~HW_BRK_TYPE_DABR
;
740 unsigned long lctrl1
= 0x90000000; /* compare type: equal on E & F */
741 unsigned long lctrl2
= 0x8e000002; /* watchpoint 1 on cmp E | F */
743 if ((dabr
& HW_BRK_TYPE_RDWR
) == HW_BRK_TYPE_READ
)
745 else if ((dabr
& HW_BRK_TYPE_RDWR
) == HW_BRK_TYPE_WRITE
)
747 else if ((dabr
& HW_BRK_TYPE_RDWR
) == 0)
750 mtspr(SPRN_LCTRL2
, 0);
751 mtspr(SPRN_CMPE
, addr
);
752 mtspr(SPRN_CMPF
, addr
+ 4);
753 mtspr(SPRN_LCTRL1
, lctrl1
);
754 mtspr(SPRN_LCTRL2
, lctrl2
);
759 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
765 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
767 unsigned long dabr
, dabrx
;
769 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
770 dabrx
= ((brk
->type
>> 3) & 0x7);
773 return ppc_md
.set_dabr(dabr
, dabrx
);
775 return __set_dabr(dabr
, dabrx
);
778 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
780 unsigned long dawr
, dawrx
, mrd
;
784 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
785 << (63 - 58); //* read/write bits */
786 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
787 << (63 - 59); //* translate */
788 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
789 >> 3; //* PRIM bits */
790 /* dawr length is stored in field MDR bits 48:53. Matches range in
791 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
793 brk->len is in bytes.
794 This aligns up to double word size, shifts and does the bias.
796 mrd
= ((brk
->len
+ 7) >> 3) - 1;
797 dawrx
|= (mrd
& 0x3f) << (63 - 53);
800 return ppc_md
.set_dawr(dawr
, dawrx
);
801 mtspr(SPRN_DAWR
, dawr
);
802 mtspr(SPRN_DAWRX
, dawrx
);
806 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
808 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
810 if (cpu_has_feature(CPU_FTR_DAWR
))
816 void set_breakpoint(struct arch_hw_breakpoint
*brk
)
819 __set_breakpoint(brk
);
824 DEFINE_PER_CPU(struct cpu_usage
, cpu_usage_array
);
827 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
828 struct arch_hw_breakpoint
*b
)
830 if (a
->address
!= b
->address
)
832 if (a
->type
!= b
->type
)
834 if (a
->len
!= b
->len
)
839 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
841 static inline bool tm_enabled(struct task_struct
*tsk
)
843 return tsk
&& tsk
->thread
.regs
&& (tsk
->thread
.regs
->msr
& MSR_TM
);
846 static void tm_reclaim_thread(struct thread_struct
*thr
,
847 struct thread_info
*ti
, uint8_t cause
)
850 * Use the current MSR TM suspended bit to track if we have
851 * checkpointed state outstanding.
852 * On signal delivery, we'd normally reclaim the checkpointed
853 * state to obtain stack pointer (see:get_tm_stackpointer()).
854 * This will then directly return to userspace without going
855 * through __switch_to(). However, if the stack frame is bad,
856 * we need to exit this thread which calls __switch_to() which
857 * will again attempt to reclaim the already saved tm state.
858 * Hence we need to check that we've not already reclaimed
860 * We do this using the current MSR, rather tracking it in
861 * some specific thread_struct bit, as it has the additional
862 * benefit of checking for a potential TM bad thing exception.
864 if (!MSR_TM_SUSPENDED(mfmsr()))
867 giveup_all(container_of(thr
, struct task_struct
, thread
));
869 tm_reclaim(thr
, thr
->ckpt_regs
.msr
, cause
);
872 void tm_reclaim_current(uint8_t cause
)
875 tm_reclaim_thread(¤t
->thread
, current_thread_info(), cause
);
878 static inline void tm_reclaim_task(struct task_struct
*tsk
)
880 /* We have to work out if we're switching from/to a task that's in the
881 * middle of a transaction.
883 * In switching we need to maintain a 2nd register state as
884 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
885 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
888 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
890 struct thread_struct
*thr
= &tsk
->thread
;
895 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
896 goto out_and_saveregs
;
898 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
899 "ccr=%lx, msr=%lx, trap=%lx)\n",
900 tsk
->pid
, thr
->regs
->nip
,
901 thr
->regs
->ccr
, thr
->regs
->msr
,
904 tm_reclaim_thread(thr
, task_thread_info(tsk
), TM_CAUSE_RESCHED
);
906 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
910 /* Always save the regs here, even if a transaction's not active.
911 * This context-switches a thread's TM info SPRs. We do it here to
912 * be consistent with the restore path (in recheckpoint) which
913 * cannot happen later in _switch().
918 extern void __tm_recheckpoint(struct thread_struct
*thread
,
919 unsigned long orig_msr
);
921 void tm_recheckpoint(struct thread_struct
*thread
,
922 unsigned long orig_msr
)
926 if (!(thread
->regs
->msr
& MSR_TM
))
929 /* We really can't be interrupted here as the TEXASR registers can't
930 * change and later in the trecheckpoint code, we have a userspace R1.
931 * So let's hard disable over this region.
933 local_irq_save(flags
);
936 /* The TM SPRs are restored here, so that TEXASR.FS can be set
937 * before the trecheckpoint and no explosion occurs.
939 tm_restore_sprs(thread
);
941 __tm_recheckpoint(thread
, orig_msr
);
943 local_irq_restore(flags
);
946 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
950 if (!cpu_has_feature(CPU_FTR_TM
))
953 /* Recheckpoint the registers of the thread we're about to switch to.
955 * If the task was using FP, we non-lazily reload both the original and
956 * the speculative FP register states. This is because the kernel
957 * doesn't see if/when a TM rollback occurs, so if we take an FP
958 * unavailable later, we are unable to determine which set of FP regs
959 * need to be restored.
961 if (!tm_enabled(new))
964 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
965 tm_restore_sprs(&new->thread
);
968 msr
= new->thread
.ckpt_regs
.msr
;
969 /* Recheckpoint to restore original checkpointed register state. */
970 TM_DEBUG("*** tm_recheckpoint of pid %d "
971 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
972 new->pid
, new->thread
.regs
->msr
, msr
);
974 tm_recheckpoint(&new->thread
, msr
);
977 * The checkpointed state has been restored but the live state has
978 * not, ensure all the math functionality is turned off to trigger
979 * restore_math() to reload.
981 new->thread
.regs
->msr
&= ~(MSR_FP
| MSR_VEC
| MSR_VSX
);
983 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
984 "(kernel msr 0x%lx)\n",
988 static inline void __switch_to_tm(struct task_struct
*prev
,
989 struct task_struct
*new)
991 if (cpu_has_feature(CPU_FTR_TM
)) {
992 if (tm_enabled(prev
) || tm_enabled(new))
995 if (tm_enabled(prev
)) {
996 prev
->thread
.load_tm
++;
997 tm_reclaim_task(prev
);
998 if (!MSR_TM_ACTIVE(prev
->thread
.regs
->msr
) && prev
->thread
.load_tm
== 0)
999 prev
->thread
.regs
->msr
&= ~MSR_TM
;
1002 tm_recheckpoint_new_task(new);
1007 * This is called if we are on the way out to userspace and the
1008 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1009 * FP and/or vector state and does so if necessary.
1010 * If userspace is inside a transaction (whether active or
1011 * suspended) and FP/VMX/VSX instructions have ever been enabled
1012 * inside that transaction, then we have to keep them enabled
1013 * and keep the FP/VMX/VSX state loaded while ever the transaction
1014 * continues. The reason is that if we didn't, and subsequently
1015 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1016 * we don't know whether it's the same transaction, and thus we
1017 * don't know which of the checkpointed state and the transactional
1020 void restore_tm_state(struct pt_regs
*regs
)
1022 unsigned long msr_diff
;
1025 * This is the only moment we should clear TIF_RESTORE_TM as
1026 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1027 * again, anything else could lead to an incorrect ckpt_msr being
1028 * saved and therefore incorrect signal contexts.
1030 clear_thread_flag(TIF_RESTORE_TM
);
1031 if (!MSR_TM_ACTIVE(regs
->msr
))
1034 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
1035 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
1037 /* Ensure that restore_math() will restore */
1038 if (msr_diff
& MSR_FP
)
1039 current
->thread
.load_fp
= 1;
1040 #ifdef CONFIG_ALTIVEC
1041 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && msr_diff
& MSR_VEC
)
1042 current
->thread
.load_vec
= 1;
1046 regs
->msr
|= msr_diff
;
1050 #define tm_recheckpoint_new_task(new)
1051 #define __switch_to_tm(prev, new)
1052 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1054 static inline void save_sprs(struct thread_struct
*t
)
1056 #ifdef CONFIG_ALTIVEC
1057 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
1058 t
->vrsave
= mfspr(SPRN_VRSAVE
);
1060 #ifdef CONFIG_PPC_BOOK3S_64
1061 if (cpu_has_feature(CPU_FTR_DSCR
))
1062 t
->dscr
= mfspr(SPRN_DSCR
);
1064 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1065 t
->bescr
= mfspr(SPRN_BESCR
);
1066 t
->ebbhr
= mfspr(SPRN_EBBHR
);
1067 t
->ebbrr
= mfspr(SPRN_EBBRR
);
1069 t
->fscr
= mfspr(SPRN_FSCR
);
1072 * Note that the TAR is not available for use in the kernel.
1073 * (To provide this, the TAR should be backed up/restored on
1074 * exception entry/exit instead, and be in pt_regs. FIXME,
1075 * this should be in pt_regs anyway (for debug).)
1077 t
->tar
= mfspr(SPRN_TAR
);
1082 static inline void restore_sprs(struct thread_struct
*old_thread
,
1083 struct thread_struct
*new_thread
)
1085 #ifdef CONFIG_ALTIVEC
1086 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
1087 old_thread
->vrsave
!= new_thread
->vrsave
)
1088 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
1090 #ifdef CONFIG_PPC_BOOK3S_64
1091 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1092 u64 dscr
= get_paca()->dscr_default
;
1093 if (new_thread
->dscr_inherit
)
1094 dscr
= new_thread
->dscr
;
1096 if (old_thread
->dscr
!= dscr
)
1097 mtspr(SPRN_DSCR
, dscr
);
1100 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1101 if (old_thread
->bescr
!= new_thread
->bescr
)
1102 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1103 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1104 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1105 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1106 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1108 if (old_thread
->fscr
!= new_thread
->fscr
)
1109 mtspr(SPRN_FSCR
, new_thread
->fscr
);
1111 if (old_thread
->tar
!= new_thread
->tar
)
1112 mtspr(SPRN_TAR
, new_thread
->tar
);
1117 struct task_struct
*__switch_to(struct task_struct
*prev
,
1118 struct task_struct
*new)
1120 struct thread_struct
*new_thread
, *old_thread
;
1121 struct task_struct
*last
;
1122 #ifdef CONFIG_PPC_BOOK3S_64
1123 struct ppc64_tlb_batch
*batch
;
1126 new_thread
= &new->thread
;
1127 old_thread
= ¤t
->thread
;
1129 WARN_ON(!irqs_disabled());
1133 * Collect processor utilization data per process
1135 if (firmware_has_feature(FW_FEATURE_SPLPAR
)) {
1136 struct cpu_usage
*cu
= this_cpu_ptr(&cpu_usage_array
);
1137 long unsigned start_tb
, current_tb
;
1138 start_tb
= old_thread
->start_tb
;
1139 cu
->current_tb
= current_tb
= mfspr(SPRN_PURR
);
1140 old_thread
->accum_tb
+= (current_tb
- start_tb
);
1141 new_thread
->start_tb
= current_tb
;
1143 #endif /* CONFIG_PPC64 */
1145 #ifdef CONFIG_PPC_STD_MMU_64
1146 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1147 if (batch
->active
) {
1148 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1150 __flush_tlb_pending(batch
);
1153 #endif /* CONFIG_PPC_STD_MMU_64 */
1155 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1156 switch_booke_debug_regs(&new->thread
.debug
);
1159 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1162 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1163 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1164 __set_breakpoint(&new->thread
.hw_brk
);
1165 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1169 * We need to save SPRs before treclaim/trecheckpoint as these will
1170 * change a number of them.
1172 save_sprs(&prev
->thread
);
1174 /* Save FPU, Altivec, VSX and SPE state */
1177 __switch_to_tm(prev
, new);
1180 * We can't take a PMU exception inside _switch() since there is a
1181 * window where the kernel stack SLB and the kernel stack are out
1182 * of sync. Hard disable here.
1187 * Call restore_sprs() before calling _switch(). If we move it after
1188 * _switch() then we miss out on calling it for new tasks. The reason
1189 * for this is we manually create a stack frame for new tasks that
1190 * directly returns through ret_from_fork() or
1191 * ret_from_kernel_thread(). See copy_thread() for details.
1193 restore_sprs(old_thread
, new_thread
);
1195 last
= _switch(old_thread
, new_thread
);
1197 #ifdef CONFIG_PPC_STD_MMU_64
1198 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1199 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1200 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1204 if (current_thread_info()->task
->thread
.regs
)
1205 restore_math(current_thread_info()->task
->thread
.regs
);
1206 #endif /* CONFIG_PPC_STD_MMU_64 */
1211 static int instructions_to_print
= 16;
1213 static void show_instructions(struct pt_regs
*regs
)
1216 unsigned long pc
= regs
->nip
- (instructions_to_print
* 3 / 4 *
1219 printk("Instruction dump:");
1221 for (i
= 0; i
< instructions_to_print
; i
++) {
1227 #if !defined(CONFIG_BOOKE)
1228 /* If executing with the IMMU off, adjust pc rather
1229 * than print XXXXXXXX.
1231 if (!(regs
->msr
& MSR_IR
))
1232 pc
= (unsigned long)phys_to_virt(pc
);
1235 if (!__kernel_text_address(pc
) ||
1236 probe_kernel_address((unsigned int __user
*)pc
, instr
)) {
1237 pr_cont("XXXXXXXX ");
1239 if (regs
->nip
== pc
)
1240 pr_cont("<%08x> ", instr
);
1242 pr_cont("%08x ", instr
);
1256 static struct regbit msr_bits
[] = {
1257 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1279 #ifndef CONFIG_BOOKE
1286 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1290 for (; bits
->bit
; ++bits
)
1291 if (val
& bits
->bit
) {
1292 pr_cont("%s%s", s
, bits
->name
);
1297 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1298 static struct regbit msr_tm_bits
[] = {
1305 static void print_tm_bits(unsigned long val
)
1308 * This only prints something if at least one of the TM bit is set.
1309 * Inside the TM[], the output means:
1310 * E: Enabled (bit 32)
1311 * S: Suspended (bit 33)
1312 * T: Transactional (bit 34)
1314 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1316 print_bits(val
, msr_tm_bits
, "");
1321 static void print_tm_bits(unsigned long val
) {}
1324 static void print_msr_bits(unsigned long val
)
1327 print_bits(val
, msr_bits
, ",");
1333 #define REG "%016lx"
1334 #define REGS_PER_LINE 4
1335 #define LAST_VOLATILE 13
1338 #define REGS_PER_LINE 8
1339 #define LAST_VOLATILE 12
1342 void show_regs(struct pt_regs
* regs
)
1346 show_regs_print_info(KERN_DEFAULT
);
1348 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1349 regs
->nip
, regs
->link
, regs
->ctr
);
1350 printk("REGS: %p TRAP: %04lx %s (%s)\n",
1351 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1352 printk("MSR: "REG
" ", regs
->msr
);
1353 print_msr_bits(regs
->msr
);
1354 printk(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1356 if ((regs
->trap
!= 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1357 pr_cont("CFAR: "REG
" ", regs
->orig_gpr3
);
1358 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1359 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1360 pr_cont("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1362 pr_cont("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1365 pr_cont("SOFTE: %ld ", regs
->softe
);
1367 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1368 if (MSR_TM_ACTIVE(regs
->msr
))
1369 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1372 for (i
= 0; i
< 32; i
++) {
1373 if ((i
% REGS_PER_LINE
) == 0)
1374 pr_cont("\nGPR%02d: ", i
);
1375 pr_cont(REG
" ", regs
->gpr
[i
]);
1376 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1380 #ifdef CONFIG_KALLSYMS
1382 * Lookup NIP late so we have the best change of getting the
1383 * above info out without failing
1385 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1386 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1388 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1389 if (!user_mode(regs
))
1390 show_instructions(regs
);
1393 void flush_thread(void)
1395 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1396 flush_ptrace_hw_breakpoint(current
);
1397 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1398 set_debug_reg_defaults(¤t
->thread
);
1399 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1403 release_thread(struct task_struct
*t
)
1408 * this gets called so that we can store coprocessor state into memory and
1409 * copy the current task into the new thread.
1411 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1413 flush_all_to_thread(src
);
1415 * Flush TM state out so we can copy it. __switch_to_tm() does this
1416 * flush but it removes the checkpointed state from the current CPU and
1417 * transitions the CPU out of TM mode. Hence we need to call
1418 * tm_recheckpoint_new_task() (on the same task) to restore the
1419 * checkpointed state back and the TM mode.
1421 * Can't pass dst because it isn't ready. Doesn't matter, passing
1422 * dst is only important for __switch_to()
1424 __switch_to_tm(src
, src
);
1428 clear_task_ebb(dst
);
1433 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1435 #ifdef CONFIG_PPC_STD_MMU_64
1436 unsigned long sp_vsid
;
1437 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1439 if (radix_enabled())
1442 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1443 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1444 << SLB_VSID_SHIFT_1T
;
1446 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1448 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1449 p
->thread
.ksp_vsid
= sp_vsid
;
1458 * Copy architecture-specific thread state
1460 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1461 unsigned long kthread_arg
, struct task_struct
*p
)
1463 struct pt_regs
*childregs
, *kregs
;
1464 extern void ret_from_fork(void);
1465 extern void ret_from_kernel_thread(void);
1467 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1468 struct thread_info
*ti
= task_thread_info(p
);
1470 klp_init_thread_info(ti
);
1472 /* Copy registers */
1473 sp
-= sizeof(struct pt_regs
);
1474 childregs
= (struct pt_regs
*) sp
;
1475 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1477 memset(childregs
, 0, sizeof(struct pt_regs
));
1478 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1481 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1483 clear_tsk_thread_flag(p
, TIF_32BIT
);
1484 childregs
->softe
= 1;
1486 childregs
->gpr
[15] = kthread_arg
;
1487 p
->thread
.regs
= NULL
; /* no user register state */
1488 ti
->flags
|= _TIF_RESTOREALL
;
1489 f
= ret_from_kernel_thread
;
1492 struct pt_regs
*regs
= current_pt_regs();
1493 CHECK_FULL_REGS(regs
);
1496 childregs
->gpr
[1] = usp
;
1497 p
->thread
.regs
= childregs
;
1498 childregs
->gpr
[3] = 0; /* Result from fork() */
1499 if (clone_flags
& CLONE_SETTLS
) {
1501 if (!is_32bit_task())
1502 childregs
->gpr
[13] = childregs
->gpr
[6];
1505 childregs
->gpr
[2] = childregs
->gpr
[6];
1510 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1511 sp
-= STACK_FRAME_OVERHEAD
;
1514 * The way this works is that at some point in the future
1515 * some task will call _switch to switch to the new task.
1516 * That will pop off the stack frame created below and start
1517 * the new task running at ret_from_fork. The new task will
1518 * do some house keeping and then return from the fork or clone
1519 * system call, using the stack frame created above.
1521 ((unsigned long *)sp
)[0] = 0;
1522 sp
-= sizeof(struct pt_regs
);
1523 kregs
= (struct pt_regs
*) sp
;
1524 sp
-= STACK_FRAME_OVERHEAD
;
1527 p
->thread
.ksp_limit
= (unsigned long)task_stack_page(p
) +
1528 _ALIGN_UP(sizeof(struct thread_info
), 16);
1530 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1531 p
->thread
.ptrace_bps
[0] = NULL
;
1534 p
->thread
.fp_save_area
= NULL
;
1535 #ifdef CONFIG_ALTIVEC
1536 p
->thread
.vr_save_area
= NULL
;
1539 setup_ksp_vsid(p
, sp
);
1542 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1543 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1544 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1546 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1547 p
->thread
.ppr
= INIT_PPR
;
1549 kregs
->nip
= ppc_function_entry(f
);
1554 * Set up a thread for executing a new program
1556 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1559 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1563 * If we exec out of a kernel thread then thread.regs will not be
1566 if (!current
->thread
.regs
) {
1567 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1568 current
->thread
.regs
= regs
- 1;
1571 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1573 * Clear any transactional state, we're exec()ing. The cause is
1574 * not important as there will never be a recheckpoint so it's not
1577 if (MSR_TM_SUSPENDED(mfmsr()))
1578 tm_reclaim_current(0);
1581 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1589 * We have just cleared all the nonvolatile GPRs, so make
1590 * FULL_REGS(regs) return true. This is necessary to allow
1591 * ptrace to examine the thread immediately after exec.
1598 regs
->msr
= MSR_USER
;
1600 if (!is_32bit_task()) {
1601 unsigned long entry
;
1603 if (is_elf2_task()) {
1604 /* Look ma, no function descriptors! */
1609 * The latest iteration of the ABI requires that when
1610 * calling a function (at its global entry point),
1611 * the caller must ensure r12 holds the entry point
1612 * address (so that the function can quickly
1613 * establish addressability).
1615 regs
->gpr
[12] = start
;
1616 /* Make sure that's restored on entry to userspace. */
1617 set_thread_flag(TIF_RESTOREALL
);
1621 /* start is a relocated pointer to the function
1622 * descriptor for the elf _start routine. The first
1623 * entry in the function descriptor is the entry
1624 * address of _start and the second entry is the TOC
1625 * value we need to use.
1627 __get_user(entry
, (unsigned long __user
*)start
);
1628 __get_user(toc
, (unsigned long __user
*)start
+1);
1630 /* Check whether the e_entry function descriptor entries
1631 * need to be relocated before we can use them.
1633 if (load_addr
!= 0) {
1640 regs
->msr
= MSR_USER64
;
1644 regs
->msr
= MSR_USER32
;
1648 current
->thread
.used_vsr
= 0;
1650 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1651 current
->thread
.fp_save_area
= NULL
;
1652 #ifdef CONFIG_ALTIVEC
1653 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1654 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1655 current
->thread
.vr_save_area
= NULL
;
1656 current
->thread
.vrsave
= 0;
1657 current
->thread
.used_vr
= 0;
1658 #endif /* CONFIG_ALTIVEC */
1660 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1661 current
->thread
.acc
= 0;
1662 current
->thread
.spefscr
= 0;
1663 current
->thread
.used_spe
= 0;
1664 #endif /* CONFIG_SPE */
1665 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1666 current
->thread
.tm_tfhar
= 0;
1667 current
->thread
.tm_texasr
= 0;
1668 current
->thread
.tm_tfiar
= 0;
1669 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1671 EXPORT_SYMBOL(start_thread
);
1673 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1674 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1676 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1678 struct pt_regs
*regs
= tsk
->thread
.regs
;
1680 /* This is a bit hairy. If we are an SPE enabled processor
1681 * (have embedded fp) we store the IEEE exception enable flags in
1682 * fpexc_mode. fpexc_mode is also used for setting FP exception
1683 * mode (asyn, precise, disabled) for 'Classic' FP. */
1684 if (val
& PR_FP_EXC_SW_ENABLE
) {
1686 if (cpu_has_feature(CPU_FTR_SPE
)) {
1688 * When the sticky exception bits are set
1689 * directly by userspace, it must call prctl
1690 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1691 * in the existing prctl settings) or
1692 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1693 * the bits being set). <fenv.h> functions
1694 * saving and restoring the whole
1695 * floating-point environment need to do so
1696 * anyway to restore the prctl settings from
1697 * the saved environment.
1699 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1700 tsk
->thread
.fpexc_mode
= val
&
1701 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1711 /* on a CONFIG_SPE this does not hurt us. The bits that
1712 * __pack_fe01 use do not overlap with bits used for
1713 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1714 * on CONFIG_SPE implementations are reserved so writing to
1715 * them does not change anything */
1716 if (val
> PR_FP_EXC_PRECISE
)
1718 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1719 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1720 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1721 | tsk
->thread
.fpexc_mode
;
1725 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1729 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1731 if (cpu_has_feature(CPU_FTR_SPE
)) {
1733 * When the sticky exception bits are set
1734 * directly by userspace, it must call prctl
1735 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1736 * in the existing prctl settings) or
1737 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1738 * the bits being set). <fenv.h> functions
1739 * saving and restoring the whole
1740 * floating-point environment need to do so
1741 * anyway to restore the prctl settings from
1742 * the saved environment.
1744 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1745 val
= tsk
->thread
.fpexc_mode
;
1752 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1753 return put_user(val
, (unsigned int __user
*) adr
);
1756 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1758 struct pt_regs
*regs
= tsk
->thread
.regs
;
1760 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1761 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1767 if (val
== PR_ENDIAN_BIG
)
1768 regs
->msr
&= ~MSR_LE
;
1769 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1770 regs
->msr
|= MSR_LE
;
1777 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1779 struct pt_regs
*regs
= tsk
->thread
.regs
;
1782 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1783 !cpu_has_feature(CPU_FTR_REAL_LE
))
1789 if (regs
->msr
& MSR_LE
) {
1790 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1791 val
= PR_ENDIAN_LITTLE
;
1793 val
= PR_ENDIAN_PPC_LITTLE
;
1795 val
= PR_ENDIAN_BIG
;
1797 return put_user(val
, (unsigned int __user
*)adr
);
1800 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1802 tsk
->thread
.align_ctl
= val
;
1806 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1808 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1811 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1812 unsigned long nbytes
)
1814 unsigned long stack_page
;
1815 unsigned long cpu
= task_cpu(p
);
1818 * Avoid crashing if the stack has overflowed and corrupted
1819 * task_cpu(p), which is in the thread_info struct.
1821 if (cpu
< NR_CPUS
&& cpu_possible(cpu
)) {
1822 stack_page
= (unsigned long) hardirq_ctx
[cpu
];
1823 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1824 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1827 stack_page
= (unsigned long) softirq_ctx
[cpu
];
1828 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1829 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1835 int validate_sp(unsigned long sp
, struct task_struct
*p
,
1836 unsigned long nbytes
)
1838 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
1840 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1841 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1844 return valid_irq_stack(sp
, p
, nbytes
);
1847 EXPORT_SYMBOL(validate_sp
);
1849 unsigned long get_wchan(struct task_struct
*p
)
1851 unsigned long ip
, sp
;
1854 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
1858 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1862 sp
= *(unsigned long *)sp
;
1863 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1866 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
1867 if (!in_sched_functions(ip
))
1870 } while (count
++ < 16);
1874 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
1876 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
1878 unsigned long sp
, ip
, lr
, newsp
;
1881 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1882 int curr_frame
= current
->curr_ret_stack
;
1883 extern void return_to_handler(void);
1884 unsigned long rth
= (unsigned long)return_to_handler
;
1887 sp
= (unsigned long) stack
;
1892 sp
= current_stack_pointer();
1894 sp
= tsk
->thread
.ksp
;
1898 printk("Call Trace:\n");
1900 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
1903 stack
= (unsigned long *) sp
;
1905 ip
= stack
[STACK_FRAME_LR_SAVE
];
1906 if (!firstframe
|| ip
!= lr
) {
1907 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
1908 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1909 if ((ip
== rth
) && curr_frame
>= 0) {
1911 (void *)current
->ret_stack
[curr_frame
].ret
);
1916 pr_cont(" (unreliable)");
1922 * See if this is an exception frame.
1923 * We look for the "regshere" marker in the current frame.
1925 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
1926 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
1927 struct pt_regs
*regs
= (struct pt_regs
*)
1928 (sp
+ STACK_FRAME_OVERHEAD
);
1930 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
1931 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
1936 } while (count
++ < kstack_depth_to_print
);
1940 /* Called with hard IRQs off */
1941 void notrace
__ppc64_runlatch_on(void)
1943 struct thread_info
*ti
= current_thread_info();
1946 ctrl
= mfspr(SPRN_CTRLF
);
1947 ctrl
|= CTRL_RUNLATCH
;
1948 mtspr(SPRN_CTRLT
, ctrl
);
1950 ti
->local_flags
|= _TLF_RUNLATCH
;
1953 /* Called with hard IRQs off */
1954 void notrace
__ppc64_runlatch_off(void)
1956 struct thread_info
*ti
= current_thread_info();
1959 ti
->local_flags
&= ~_TLF_RUNLATCH
;
1961 ctrl
= mfspr(SPRN_CTRLF
);
1962 ctrl
&= ~CTRL_RUNLATCH
;
1963 mtspr(SPRN_CTRLT
, ctrl
);
1965 #endif /* CONFIG_PPC64 */
1967 unsigned long arch_align_stack(unsigned long sp
)
1969 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
1970 sp
-= get_random_int() & ~PAGE_MASK
;
1974 static inline unsigned long brk_rnd(void)
1976 unsigned long rnd
= 0;
1978 /* 8MB for 32bit, 1GB for 64bit */
1979 if (is_32bit_task())
1980 rnd
= (get_random_long() % (1UL<<(23-PAGE_SHIFT
)));
1982 rnd
= (get_random_long() % (1UL<<(30-PAGE_SHIFT
)));
1984 return rnd
<< PAGE_SHIFT
;
1987 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
1989 unsigned long base
= mm
->brk
;
1992 #ifdef CONFIG_PPC_STD_MMU_64
1994 * If we are using 1TB segments and we are allowed to randomise
1995 * the heap, we can put it above 1TB so it is backed by a 1TB
1996 * segment. Otherwise the heap will be in the bottom 1TB
1997 * which always uses 256MB segments and this may result in a
1998 * performance penalty. We don't need to worry about radix. For
1999 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2001 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
2002 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
2005 ret
= PAGE_ALIGN(base
+ brk_rnd());