1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from "arch/i386/kernel/process.c"
4 * Copyright (C) 1995 Linus Torvalds
6 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
7 * Paul Mackerras (paulus@cs.anu.edu.au)
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
20 #include <linux/smp.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/elf.h>
27 #include <linux/prctl.h>
28 #include <linux/init_task.h>
29 #include <linux/export.h>
30 #include <linux/kallsyms.h>
31 #include <linux/mqueue.h>
32 #include <linux/hardirq.h>
33 #include <linux/utsname.h>
34 #include <linux/ftrace.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/personality.h>
37 #include <linux/random.h>
38 #include <linux/hw_breakpoint.h>
39 #include <linux/uaccess.h>
40 #include <linux/elf-randomize.h>
41 #include <linux/pkeys.h>
42 #include <linux/seq_buf.h>
44 #include <asm/pgtable.h>
46 #include <asm/processor.h>
49 #include <asm/machdep.h>
51 #include <asm/runlatch.h>
52 #include <asm/syscalls.h>
53 #include <asm/switch_to.h>
55 #include <asm/debug.h>
57 #include <asm/firmware.h>
58 #include <asm/hw_irq.h>
60 #include <asm/code-patching.h>
62 #include <asm/livepatch.h>
63 #include <asm/cpu_has_feature.h>
64 #include <asm/asm-prototypes.h>
65 #include <asm/stacktrace.h>
66 #include <asm/hw_breakpoint.h>
68 #include <linux/kprobes.h>
69 #include <linux/kdebug.h>
71 /* Transactional Memory debug */
73 #define TM_DEBUG(x...) printk(KERN_INFO x)
75 #define TM_DEBUG(x...) do { } while(0)
78 extern unsigned long _get_SP(void);
80 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
82 * Are we running in "Suspend disabled" mode? If so we have to block any
83 * sigreturn that would get us into suspended state, and we also warn in some
84 * other paths that we should never reach with suspend disabled.
86 bool tm_suspend_disabled __ro_after_init
= false;
88 static void check_if_tm_restore_required(struct task_struct
*tsk
)
91 * If we are saving the current thread's registers, and the
92 * thread is in a transactional state, set the TIF_RESTORE_TM
93 * bit so that we know to restore the registers before
94 * returning to userspace.
96 if (tsk
== current
&& tsk
->thread
.regs
&&
97 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
98 !test_thread_flag(TIF_RESTORE_TM
)) {
99 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
100 set_thread_flag(TIF_RESTORE_TM
);
104 static bool tm_active_with_fp(struct task_struct
*tsk
)
106 return MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
107 (tsk
->thread
.ckpt_regs
.msr
& MSR_FP
);
110 static bool tm_active_with_altivec(struct task_struct
*tsk
)
112 return MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
113 (tsk
->thread
.ckpt_regs
.msr
& MSR_VEC
);
116 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
117 static inline bool tm_active_with_fp(struct task_struct
*tsk
) { return false; }
118 static inline bool tm_active_with_altivec(struct task_struct
*tsk
) { return false; }
119 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
121 bool strict_msr_control
;
122 EXPORT_SYMBOL(strict_msr_control
);
124 static int __init
enable_strict_msr_control(char *str
)
126 strict_msr_control
= true;
127 pr_info("Enabling strict facility control\n");
131 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
133 /* notrace because it's called by restore_math */
134 unsigned long notrace
msr_check_and_set(unsigned long bits
)
136 unsigned long oldmsr
= mfmsr();
137 unsigned long newmsr
;
139 newmsr
= oldmsr
| bits
;
142 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
146 if (oldmsr
!= newmsr
)
151 EXPORT_SYMBOL_GPL(msr_check_and_set
);
153 /* notrace because it's called by restore_math */
154 void notrace
__msr_check_and_clear(unsigned long bits
)
156 unsigned long oldmsr
= mfmsr();
157 unsigned long newmsr
;
159 newmsr
= oldmsr
& ~bits
;
162 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
166 if (oldmsr
!= newmsr
)
169 EXPORT_SYMBOL(__msr_check_and_clear
);
171 #ifdef CONFIG_PPC_FPU
172 static void __giveup_fpu(struct task_struct
*tsk
)
177 msr
= tsk
->thread
.regs
->msr
;
178 msr
&= ~(MSR_FP
|MSR_FE0
|MSR_FE1
);
180 if (cpu_has_feature(CPU_FTR_VSX
))
183 tsk
->thread
.regs
->msr
= msr
;
186 void giveup_fpu(struct task_struct
*tsk
)
188 check_if_tm_restore_required(tsk
);
190 msr_check_and_set(MSR_FP
);
192 msr_check_and_clear(MSR_FP
);
194 EXPORT_SYMBOL(giveup_fpu
);
197 * Make sure the floating-point register state in the
198 * the thread_struct is up to date for task tsk.
200 void flush_fp_to_thread(struct task_struct
*tsk
)
202 if (tsk
->thread
.regs
) {
204 * We need to disable preemption here because if we didn't,
205 * another process could get scheduled after the regs->msr
206 * test but before we have finished saving the FP registers
207 * to the thread_struct. That process could take over the
208 * FPU, and then when we get scheduled again we would store
209 * bogus values for the remaining FP registers.
212 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
214 * This should only ever be called for current or
215 * for a stopped child process. Since we save away
216 * the FP register state on context switch,
217 * there is something wrong if a stopped child appears
218 * to still have its FP state in the CPU registers.
220 BUG_ON(tsk
!= current
);
226 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
228 void enable_kernel_fp(void)
230 unsigned long cpumsr
;
232 WARN_ON(preemptible());
234 cpumsr
= msr_check_and_set(MSR_FP
);
236 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
237 check_if_tm_restore_required(current
);
239 * If a thread has already been reclaimed then the
240 * checkpointed registers are on the CPU but have definitely
241 * been saved by the reclaim code. Don't need to and *cannot*
242 * giveup as this would save to the 'live' structure not the
243 * checkpointed structure.
245 if (!MSR_TM_ACTIVE(cpumsr
) &&
246 MSR_TM_ACTIVE(current
->thread
.regs
->msr
))
248 __giveup_fpu(current
);
251 EXPORT_SYMBOL(enable_kernel_fp
);
253 static int restore_fp(struct task_struct
*tsk
)
255 if (tsk
->thread
.load_fp
|| tm_active_with_fp(tsk
)) {
256 load_fp_state(¤t
->thread
.fp_state
);
257 current
->thread
.load_fp
++;
263 static int restore_fp(struct task_struct
*tsk
) { return 0; }
264 #endif /* CONFIG_PPC_FPU */
266 #ifdef CONFIG_ALTIVEC
267 #define loadvec(thr) ((thr).load_vec)
269 static void __giveup_altivec(struct task_struct
*tsk
)
274 msr
= tsk
->thread
.regs
->msr
;
277 if (cpu_has_feature(CPU_FTR_VSX
))
280 tsk
->thread
.regs
->msr
= msr
;
283 void giveup_altivec(struct task_struct
*tsk
)
285 check_if_tm_restore_required(tsk
);
287 msr_check_and_set(MSR_VEC
);
288 __giveup_altivec(tsk
);
289 msr_check_and_clear(MSR_VEC
);
291 EXPORT_SYMBOL(giveup_altivec
);
293 void enable_kernel_altivec(void)
295 unsigned long cpumsr
;
297 WARN_ON(preemptible());
299 cpumsr
= msr_check_and_set(MSR_VEC
);
301 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
302 check_if_tm_restore_required(current
);
304 * If a thread has already been reclaimed then the
305 * checkpointed registers are on the CPU but have definitely
306 * been saved by the reclaim code. Don't need to and *cannot*
307 * giveup as this would save to the 'live' structure not the
308 * checkpointed structure.
310 if (!MSR_TM_ACTIVE(cpumsr
) &&
311 MSR_TM_ACTIVE(current
->thread
.regs
->msr
))
313 __giveup_altivec(current
);
316 EXPORT_SYMBOL(enable_kernel_altivec
);
319 * Make sure the VMX/Altivec register state in the
320 * the thread_struct is up to date for task tsk.
322 void flush_altivec_to_thread(struct task_struct
*tsk
)
324 if (tsk
->thread
.regs
) {
326 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
327 BUG_ON(tsk
!= current
);
333 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
335 static int restore_altivec(struct task_struct
*tsk
)
337 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
338 (tsk
->thread
.load_vec
|| tm_active_with_altivec(tsk
))) {
339 load_vr_state(&tsk
->thread
.vr_state
);
340 tsk
->thread
.used_vr
= 1;
341 tsk
->thread
.load_vec
++;
348 #define loadvec(thr) 0
349 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
350 #endif /* CONFIG_ALTIVEC */
353 static void __giveup_vsx(struct task_struct
*tsk
)
355 unsigned long msr
= tsk
->thread
.regs
->msr
;
358 * We should never be ssetting MSR_VSX without also setting
361 WARN_ON((msr
& MSR_VSX
) && !((msr
& MSR_FP
) && (msr
& MSR_VEC
)));
363 /* __giveup_fpu will clear MSR_VSX */
367 __giveup_altivec(tsk
);
370 static void giveup_vsx(struct task_struct
*tsk
)
372 check_if_tm_restore_required(tsk
);
374 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
376 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
379 void enable_kernel_vsx(void)
381 unsigned long cpumsr
;
383 WARN_ON(preemptible());
385 cpumsr
= msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
387 if (current
->thread
.regs
&&
388 (current
->thread
.regs
->msr
& (MSR_VSX
|MSR_VEC
|MSR_FP
))) {
389 check_if_tm_restore_required(current
);
391 * If a thread has already been reclaimed then the
392 * checkpointed registers are on the CPU but have definitely
393 * been saved by the reclaim code. Don't need to and *cannot*
394 * giveup as this would save to the 'live' structure not the
395 * checkpointed structure.
397 if (!MSR_TM_ACTIVE(cpumsr
) &&
398 MSR_TM_ACTIVE(current
->thread
.regs
->msr
))
400 __giveup_vsx(current
);
403 EXPORT_SYMBOL(enable_kernel_vsx
);
405 void flush_vsx_to_thread(struct task_struct
*tsk
)
407 if (tsk
->thread
.regs
) {
409 if (tsk
->thread
.regs
->msr
& (MSR_VSX
|MSR_VEC
|MSR_FP
)) {
410 BUG_ON(tsk
!= current
);
416 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
418 static int restore_vsx(struct task_struct
*tsk
)
420 if (cpu_has_feature(CPU_FTR_VSX
)) {
421 tsk
->thread
.used_vsr
= 1;
428 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
429 #endif /* CONFIG_VSX */
432 void giveup_spe(struct task_struct
*tsk
)
434 check_if_tm_restore_required(tsk
);
436 msr_check_and_set(MSR_SPE
);
438 msr_check_and_clear(MSR_SPE
);
440 EXPORT_SYMBOL(giveup_spe
);
442 void enable_kernel_spe(void)
444 WARN_ON(preemptible());
446 msr_check_and_set(MSR_SPE
);
448 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
449 check_if_tm_restore_required(current
);
450 __giveup_spe(current
);
453 EXPORT_SYMBOL(enable_kernel_spe
);
455 void flush_spe_to_thread(struct task_struct
*tsk
)
457 if (tsk
->thread
.regs
) {
459 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
460 BUG_ON(tsk
!= current
);
461 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
467 #endif /* CONFIG_SPE */
469 static unsigned long msr_all_available
;
471 static int __init
init_msr_all_available(void)
473 #ifdef CONFIG_PPC_FPU
474 msr_all_available
|= MSR_FP
;
476 #ifdef CONFIG_ALTIVEC
477 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
478 msr_all_available
|= MSR_VEC
;
481 if (cpu_has_feature(CPU_FTR_VSX
))
482 msr_all_available
|= MSR_VSX
;
485 if (cpu_has_feature(CPU_FTR_SPE
))
486 msr_all_available
|= MSR_SPE
;
491 early_initcall(init_msr_all_available
);
493 void giveup_all(struct task_struct
*tsk
)
495 unsigned long usermsr
;
497 if (!tsk
->thread
.regs
)
500 usermsr
= tsk
->thread
.regs
->msr
;
502 if ((usermsr
& msr_all_available
) == 0)
505 msr_check_and_set(msr_all_available
);
506 check_if_tm_restore_required(tsk
);
508 WARN_ON((usermsr
& MSR_VSX
) && !((usermsr
& MSR_FP
) && (usermsr
& MSR_VEC
)));
510 #ifdef CONFIG_PPC_FPU
511 if (usermsr
& MSR_FP
)
514 #ifdef CONFIG_ALTIVEC
515 if (usermsr
& MSR_VEC
)
516 __giveup_altivec(tsk
);
519 if (usermsr
& MSR_SPE
)
523 msr_check_and_clear(msr_all_available
);
525 EXPORT_SYMBOL(giveup_all
);
528 * The exception exit path calls restore_math() with interrupts hard disabled
529 * but the soft irq state not "reconciled". ftrace code that calls
530 * local_irq_save/restore causes warnings.
532 * Rather than complicate the exit path, just don't trace restore_math. This
533 * could be done by having ftrace entry code check for this un-reconciled
534 * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and
535 * temporarily fix it up for the duration of the ftrace call.
537 void notrace
restore_math(struct pt_regs
*regs
)
541 if (!MSR_TM_ACTIVE(regs
->msr
) &&
542 !current
->thread
.load_fp
&& !loadvec(current
->thread
))
546 msr_check_and_set(msr_all_available
);
549 * Only reload if the bit is not set in the user MSR, the bit BEING set
550 * indicates that the registers are hot
552 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
553 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
555 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
558 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
559 restore_vsx(current
)) {
563 msr_check_and_clear(msr_all_available
);
568 static void save_all(struct task_struct
*tsk
)
570 unsigned long usermsr
;
572 if (!tsk
->thread
.regs
)
575 usermsr
= tsk
->thread
.regs
->msr
;
577 if ((usermsr
& msr_all_available
) == 0)
580 msr_check_and_set(msr_all_available
);
582 WARN_ON((usermsr
& MSR_VSX
) && !((usermsr
& MSR_FP
) && (usermsr
& MSR_VEC
)));
584 if (usermsr
& MSR_FP
)
587 if (usermsr
& MSR_VEC
)
590 if (usermsr
& MSR_SPE
)
593 msr_check_and_clear(msr_all_available
);
594 thread_pkey_regs_save(&tsk
->thread
);
597 void flush_all_to_thread(struct task_struct
*tsk
)
599 if (tsk
->thread
.regs
) {
601 BUG_ON(tsk
!= current
);
603 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
604 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
611 EXPORT_SYMBOL(flush_all_to_thread
);
613 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
614 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
615 unsigned long error_code
, int breakpt
)
617 current
->thread
.trap_nr
= TRAP_HWBKPT
;
618 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
619 11, SIGSEGV
) == NOTIFY_STOP
)
622 /* Deliver the signal to userspace */
623 force_sig_ptrace_errno_trap(breakpt
, /* breakpoint or watchpoint id */
624 (void __user
*)address
);
626 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
627 void do_break (struct pt_regs
*regs
, unsigned long address
,
628 unsigned long error_code
)
630 current
->thread
.trap_nr
= TRAP_HWBKPT
;
631 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
632 11, SIGSEGV
) == NOTIFY_STOP
)
635 if (debugger_break_match(regs
))
638 /* Clear the breakpoint */
639 hw_breakpoint_disable();
641 /* Deliver the signal to userspace */
642 force_sig_fault(SIGTRAP
, TRAP_HWBKPT
, (void __user
*)address
, current
);
644 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
646 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
648 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
650 * Set the debug registers back to their default "safe" values.
652 static void set_debug_reg_defaults(struct thread_struct
*thread
)
654 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
655 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
656 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
658 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
659 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
660 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
662 thread
->debug
.dbcr0
= 0;
665 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
667 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
668 DBCR1_IAC3US
| DBCR1_IAC4US
;
670 * Force Data Address Compare User/Supervisor bits to be User-only
671 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
673 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
675 thread
->debug
.dbcr1
= 0;
679 static void prime_debug_regs(struct debug_reg
*debug
)
682 * We could have inherited MSR_DE from userspace, since
683 * it doesn't get cleared on exception entry. Make sure
684 * MSR_DE is clear before we enable any debug events.
686 mtmsr(mfmsr() & ~MSR_DE
);
688 mtspr(SPRN_IAC1
, debug
->iac1
);
689 mtspr(SPRN_IAC2
, debug
->iac2
);
690 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
691 mtspr(SPRN_IAC3
, debug
->iac3
);
692 mtspr(SPRN_IAC4
, debug
->iac4
);
694 mtspr(SPRN_DAC1
, debug
->dac1
);
695 mtspr(SPRN_DAC2
, debug
->dac2
);
696 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
697 mtspr(SPRN_DVC1
, debug
->dvc1
);
698 mtspr(SPRN_DVC2
, debug
->dvc2
);
700 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
701 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
703 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
707 * Unless neither the old or new thread are making use of the
708 * debug registers, set the debug registers from the values
709 * stored in the new thread.
711 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
713 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
714 || (new_debug
->dbcr0
& DBCR0_IDM
))
715 prime_debug_regs(new_debug
);
717 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
718 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
719 #ifndef CONFIG_HAVE_HW_BREAKPOINT
720 static void set_breakpoint(struct arch_hw_breakpoint
*brk
)
723 __set_breakpoint(brk
);
727 static void set_debug_reg_defaults(struct thread_struct
*thread
)
729 thread
->hw_brk
.address
= 0;
730 thread
->hw_brk
.type
= 0;
731 if (ppc_breakpoint_available())
732 set_breakpoint(&thread
->hw_brk
);
734 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
735 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
737 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
738 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
740 mtspr(SPRN_DAC1
, dabr
);
741 #ifdef CONFIG_PPC_47x
746 #elif defined(CONFIG_PPC_BOOK3S)
747 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
749 mtspr(SPRN_DABR
, dabr
);
750 if (cpu_has_feature(CPU_FTR_DABRX
))
751 mtspr(SPRN_DABRX
, dabrx
);
754 #elif defined(CONFIG_PPC_8xx)
755 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
757 unsigned long addr
= dabr
& ~HW_BRK_TYPE_DABR
;
758 unsigned long lctrl1
= 0x90000000; /* compare type: equal on E & F */
759 unsigned long lctrl2
= 0x8e000002; /* watchpoint 1 on cmp E | F */
761 if ((dabr
& HW_BRK_TYPE_RDWR
) == HW_BRK_TYPE_READ
)
763 else if ((dabr
& HW_BRK_TYPE_RDWR
) == HW_BRK_TYPE_WRITE
)
765 else if ((dabr
& HW_BRK_TYPE_RDWR
) == 0)
768 mtspr(SPRN_LCTRL2
, 0);
769 mtspr(SPRN_CMPE
, addr
);
770 mtspr(SPRN_CMPF
, addr
+ 4);
771 mtspr(SPRN_LCTRL1
, lctrl1
);
772 mtspr(SPRN_LCTRL2
, lctrl2
);
777 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
783 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
785 unsigned long dabr
, dabrx
;
787 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
788 dabrx
= ((brk
->type
>> 3) & 0x7);
791 return ppc_md
.set_dabr(dabr
, dabrx
);
793 return __set_dabr(dabr
, dabrx
);
796 int set_dawr(struct arch_hw_breakpoint
*brk
)
798 unsigned long dawr
, dawrx
, mrd
;
802 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
803 << (63 - 58); //* read/write bits */
804 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
805 << (63 - 59); //* translate */
806 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
807 >> 3; //* PRIM bits */
808 /* dawr length is stored in field MDR bits 48:53. Matches range in
809 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
811 brk->len is in bytes.
812 This aligns up to double word size, shifts and does the bias.
814 mrd
= ((brk
->len
+ 7) >> 3) - 1;
815 dawrx
|= (mrd
& 0x3f) << (63 - 53);
818 return ppc_md
.set_dawr(dawr
, dawrx
);
819 mtspr(SPRN_DAWR
, dawr
);
820 mtspr(SPRN_DAWRX
, dawrx
);
824 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
826 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
831 else if (!cpu_has_feature(CPU_FTR_ARCH_207S
))
835 // Shouldn't happen due to higher level checks
839 /* Check if we have DAWR or DABR hardware */
840 bool ppc_breakpoint_available(void)
843 return true; /* POWER8 DAWR or POWER9 forced DAWR */
844 if (cpu_has_feature(CPU_FTR_ARCH_207S
))
845 return false; /* POWER9 with DAWR disabled */
846 /* DABR: Everything but POWER8 and POWER9 */
849 EXPORT_SYMBOL_GPL(ppc_breakpoint_available
);
851 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
852 struct arch_hw_breakpoint
*b
)
854 if (a
->address
!= b
->address
)
856 if (a
->type
!= b
->type
)
858 if (a
->len
!= b
->len
)
863 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
865 static inline bool tm_enabled(struct task_struct
*tsk
)
867 return tsk
&& tsk
->thread
.regs
&& (tsk
->thread
.regs
->msr
& MSR_TM
);
870 static void tm_reclaim_thread(struct thread_struct
*thr
, uint8_t cause
)
873 * Use the current MSR TM suspended bit to track if we have
874 * checkpointed state outstanding.
875 * On signal delivery, we'd normally reclaim the checkpointed
876 * state to obtain stack pointer (see:get_tm_stackpointer()).
877 * This will then directly return to userspace without going
878 * through __switch_to(). However, if the stack frame is bad,
879 * we need to exit this thread which calls __switch_to() which
880 * will again attempt to reclaim the already saved tm state.
881 * Hence we need to check that we've not already reclaimed
883 * We do this using the current MSR, rather tracking it in
884 * some specific thread_struct bit, as it has the additional
885 * benefit of checking for a potential TM bad thing exception.
887 if (!MSR_TM_SUSPENDED(mfmsr()))
890 giveup_all(container_of(thr
, struct task_struct
, thread
));
892 tm_reclaim(thr
, cause
);
895 * If we are in a transaction and FP is off then we can't have
896 * used FP inside that transaction. Hence the checkpointed
897 * state is the same as the live state. We need to copy the
898 * live state to the checkpointed state so that when the
899 * transaction is restored, the checkpointed state is correct
900 * and the aborted transaction sees the correct state. We use
901 * ckpt_regs.msr here as that's what tm_reclaim will use to
902 * determine if it's going to write the checkpointed state or
903 * not. So either this will write the checkpointed registers,
904 * or reclaim will. Similarly for VMX.
906 if ((thr
->ckpt_regs
.msr
& MSR_FP
) == 0)
907 memcpy(&thr
->ckfp_state
, &thr
->fp_state
,
908 sizeof(struct thread_fp_state
));
909 if ((thr
->ckpt_regs
.msr
& MSR_VEC
) == 0)
910 memcpy(&thr
->ckvr_state
, &thr
->vr_state
,
911 sizeof(struct thread_vr_state
));
914 void tm_reclaim_current(uint8_t cause
)
917 tm_reclaim_thread(¤t
->thread
, cause
);
920 static inline void tm_reclaim_task(struct task_struct
*tsk
)
922 /* We have to work out if we're switching from/to a task that's in the
923 * middle of a transaction.
925 * In switching we need to maintain a 2nd register state as
926 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
927 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
930 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
932 struct thread_struct
*thr
= &tsk
->thread
;
937 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
938 goto out_and_saveregs
;
940 WARN_ON(tm_suspend_disabled
);
942 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
943 "ccr=%lx, msr=%lx, trap=%lx)\n",
944 tsk
->pid
, thr
->regs
->nip
,
945 thr
->regs
->ccr
, thr
->regs
->msr
,
948 tm_reclaim_thread(thr
, TM_CAUSE_RESCHED
);
950 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
954 /* Always save the regs here, even if a transaction's not active.
955 * This context-switches a thread's TM info SPRs. We do it here to
956 * be consistent with the restore path (in recheckpoint) which
957 * cannot happen later in _switch().
962 extern void __tm_recheckpoint(struct thread_struct
*thread
);
964 void tm_recheckpoint(struct thread_struct
*thread
)
968 if (!(thread
->regs
->msr
& MSR_TM
))
971 /* We really can't be interrupted here as the TEXASR registers can't
972 * change and later in the trecheckpoint code, we have a userspace R1.
973 * So let's hard disable over this region.
975 local_irq_save(flags
);
978 /* The TM SPRs are restored here, so that TEXASR.FS can be set
979 * before the trecheckpoint and no explosion occurs.
981 tm_restore_sprs(thread
);
983 __tm_recheckpoint(thread
);
985 local_irq_restore(flags
);
988 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
990 if (!cpu_has_feature(CPU_FTR_TM
))
993 /* Recheckpoint the registers of the thread we're about to switch to.
995 * If the task was using FP, we non-lazily reload both the original and
996 * the speculative FP register states. This is because the kernel
997 * doesn't see if/when a TM rollback occurs, so if we take an FP
998 * unavailable later, we are unable to determine which set of FP regs
999 * need to be restored.
1001 if (!tm_enabled(new))
1004 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
1005 tm_restore_sprs(&new->thread
);
1008 /* Recheckpoint to restore original checkpointed register state. */
1009 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1010 new->pid
, new->thread
.regs
->msr
);
1012 tm_recheckpoint(&new->thread
);
1015 * The checkpointed state has been restored but the live state has
1016 * not, ensure all the math functionality is turned off to trigger
1017 * restore_math() to reload.
1019 new->thread
.regs
->msr
&= ~(MSR_FP
| MSR_VEC
| MSR_VSX
);
1021 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1022 "(kernel msr 0x%lx)\n",
1026 static inline void __switch_to_tm(struct task_struct
*prev
,
1027 struct task_struct
*new)
1029 if (cpu_has_feature(CPU_FTR_TM
)) {
1030 if (tm_enabled(prev
) || tm_enabled(new))
1033 if (tm_enabled(prev
)) {
1034 prev
->thread
.load_tm
++;
1035 tm_reclaim_task(prev
);
1036 if (!MSR_TM_ACTIVE(prev
->thread
.regs
->msr
) && prev
->thread
.load_tm
== 0)
1037 prev
->thread
.regs
->msr
&= ~MSR_TM
;
1040 tm_recheckpoint_new_task(new);
1045 * This is called if we are on the way out to userspace and the
1046 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1047 * FP and/or vector state and does so if necessary.
1048 * If userspace is inside a transaction (whether active or
1049 * suspended) and FP/VMX/VSX instructions have ever been enabled
1050 * inside that transaction, then we have to keep them enabled
1051 * and keep the FP/VMX/VSX state loaded while ever the transaction
1052 * continues. The reason is that if we didn't, and subsequently
1053 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1054 * we don't know whether it's the same transaction, and thus we
1055 * don't know which of the checkpointed state and the transactional
1058 void restore_tm_state(struct pt_regs
*regs
)
1060 unsigned long msr_diff
;
1063 * This is the only moment we should clear TIF_RESTORE_TM as
1064 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1065 * again, anything else could lead to an incorrect ckpt_msr being
1066 * saved and therefore incorrect signal contexts.
1068 clear_thread_flag(TIF_RESTORE_TM
);
1069 if (!MSR_TM_ACTIVE(regs
->msr
))
1072 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
1073 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
1075 /* Ensure that restore_math() will restore */
1076 if (msr_diff
& MSR_FP
)
1077 current
->thread
.load_fp
= 1;
1078 #ifdef CONFIG_ALTIVEC
1079 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && msr_diff
& MSR_VEC
)
1080 current
->thread
.load_vec
= 1;
1084 regs
->msr
|= msr_diff
;
1088 #define tm_recheckpoint_new_task(new)
1089 #define __switch_to_tm(prev, new)
1090 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1092 static inline void save_sprs(struct thread_struct
*t
)
1094 #ifdef CONFIG_ALTIVEC
1095 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
1096 t
->vrsave
= mfspr(SPRN_VRSAVE
);
1098 #ifdef CONFIG_PPC_BOOK3S_64
1099 if (cpu_has_feature(CPU_FTR_DSCR
))
1100 t
->dscr
= mfspr(SPRN_DSCR
);
1102 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1103 t
->bescr
= mfspr(SPRN_BESCR
);
1104 t
->ebbhr
= mfspr(SPRN_EBBHR
);
1105 t
->ebbrr
= mfspr(SPRN_EBBRR
);
1107 t
->fscr
= mfspr(SPRN_FSCR
);
1110 * Note that the TAR is not available for use in the kernel.
1111 * (To provide this, the TAR should be backed up/restored on
1112 * exception entry/exit instead, and be in pt_regs. FIXME,
1113 * this should be in pt_regs anyway (for debug).)
1115 t
->tar
= mfspr(SPRN_TAR
);
1119 thread_pkey_regs_save(t
);
1122 static inline void restore_sprs(struct thread_struct
*old_thread
,
1123 struct thread_struct
*new_thread
)
1125 #ifdef CONFIG_ALTIVEC
1126 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
1127 old_thread
->vrsave
!= new_thread
->vrsave
)
1128 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
1130 #ifdef CONFIG_PPC_BOOK3S_64
1131 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1132 u64 dscr
= get_paca()->dscr_default
;
1133 if (new_thread
->dscr_inherit
)
1134 dscr
= new_thread
->dscr
;
1136 if (old_thread
->dscr
!= dscr
)
1137 mtspr(SPRN_DSCR
, dscr
);
1140 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1141 if (old_thread
->bescr
!= new_thread
->bescr
)
1142 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1143 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1144 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1145 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1146 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1148 if (old_thread
->fscr
!= new_thread
->fscr
)
1149 mtspr(SPRN_FSCR
, new_thread
->fscr
);
1151 if (old_thread
->tar
!= new_thread
->tar
)
1152 mtspr(SPRN_TAR
, new_thread
->tar
);
1155 if (cpu_has_feature(CPU_FTR_P9_TIDR
) &&
1156 old_thread
->tidr
!= new_thread
->tidr
)
1157 mtspr(SPRN_TIDR
, new_thread
->tidr
);
1160 thread_pkey_regs_restore(new_thread
, old_thread
);
1163 struct task_struct
*__switch_to(struct task_struct
*prev
,
1164 struct task_struct
*new)
1166 struct thread_struct
*new_thread
, *old_thread
;
1167 struct task_struct
*last
;
1168 #ifdef CONFIG_PPC_BOOK3S_64
1169 struct ppc64_tlb_batch
*batch
;
1172 new_thread
= &new->thread
;
1173 old_thread
= ¤t
->thread
;
1175 WARN_ON(!irqs_disabled());
1177 #ifdef CONFIG_PPC_BOOK3S_64
1178 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1179 if (batch
->active
) {
1180 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1182 __flush_tlb_pending(batch
);
1185 #endif /* CONFIG_PPC_BOOK3S_64 */
1187 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1188 switch_booke_debug_regs(&new->thread
.debug
);
1191 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1194 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1195 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1196 __set_breakpoint(&new->thread
.hw_brk
);
1197 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1201 * We need to save SPRs before treclaim/trecheckpoint as these will
1202 * change a number of them.
1204 save_sprs(&prev
->thread
);
1206 /* Save FPU, Altivec, VSX and SPE state */
1209 __switch_to_tm(prev
, new);
1211 if (!radix_enabled()) {
1213 * We can't take a PMU exception inside _switch() since there
1214 * is a window where the kernel stack SLB and the kernel stack
1215 * are out of sync. Hard disable here.
1221 * Call restore_sprs() before calling _switch(). If we move it after
1222 * _switch() then we miss out on calling it for new tasks. The reason
1223 * for this is we manually create a stack frame for new tasks that
1224 * directly returns through ret_from_fork() or
1225 * ret_from_kernel_thread(). See copy_thread() for details.
1227 restore_sprs(old_thread
, new_thread
);
1229 last
= _switch(old_thread
, new_thread
);
1231 #ifdef CONFIG_PPC_BOOK3S_64
1232 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1233 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1234 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1238 if (current
->thread
.regs
) {
1239 restore_math(current
->thread
.regs
);
1242 * The copy-paste buffer can only store into foreign real
1243 * addresses, so unprivileged processes can not see the
1244 * data or use it in any way unless they have foreign real
1245 * mappings. If the new process has the foreign real address
1246 * mappings, we must issue a cp_abort to clear any state and
1247 * prevent snooping, corruption or a covert channel.
1249 if (current
->thread
.used_vas
)
1250 asm volatile(PPC_CP_ABORT
);
1252 #endif /* CONFIG_PPC_BOOK3S_64 */
1257 #define NR_INSN_TO_PRINT 16
1259 static void show_instructions(struct pt_regs
*regs
)
1262 unsigned long pc
= regs
->nip
- (NR_INSN_TO_PRINT
* 3 / 4 * sizeof(int));
1264 printk("Instruction dump:");
1266 for (i
= 0; i
< NR_INSN_TO_PRINT
; i
++) {
1272 #if !defined(CONFIG_BOOKE)
1273 /* If executing with the IMMU off, adjust pc rather
1274 * than print XXXXXXXX.
1276 if (!(regs
->msr
& MSR_IR
))
1277 pc
= (unsigned long)phys_to_virt(pc
);
1280 if (!__kernel_text_address(pc
) ||
1281 probe_kernel_address((const void *)pc
, instr
)) {
1282 pr_cont("XXXXXXXX ");
1284 if (regs
->nip
== pc
)
1285 pr_cont("<%08x> ", instr
);
1287 pr_cont("%08x ", instr
);
1296 void show_user_instructions(struct pt_regs
*regs
)
1299 int n
= NR_INSN_TO_PRINT
;
1301 char buf
[96]; /* enough for 8 times 9 + 2 chars */
1303 pc
= regs
->nip
- (NR_INSN_TO_PRINT
* 3 / 4 * sizeof(int));
1306 * Make sure the NIP points at userspace, not kernel text/data or
1309 if (!__access_ok(pc
, NR_INSN_TO_PRINT
* sizeof(int), USER_DS
)) {
1310 pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
1311 current
->comm
, current
->pid
);
1315 seq_buf_init(&s
, buf
, sizeof(buf
));
1322 for (i
= 0; i
< 8 && n
; i
++, n
--, pc
+= sizeof(int)) {
1325 if (probe_kernel_address((const void *)pc
, instr
)) {
1326 seq_buf_printf(&s
, "XXXXXXXX ");
1329 seq_buf_printf(&s
, regs
->nip
== pc
? "<%08x> " : "%08x ", instr
);
1332 if (!seq_buf_has_overflowed(&s
))
1333 pr_info("%s[%d]: code: %s\n", current
->comm
,
1334 current
->pid
, s
.buffer
);
1343 static struct regbit msr_bits
[] = {
1344 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1366 #ifndef CONFIG_BOOKE
1373 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1377 for (; bits
->bit
; ++bits
)
1378 if (val
& bits
->bit
) {
1379 pr_cont("%s%s", s
, bits
->name
);
1384 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1385 static struct regbit msr_tm_bits
[] = {
1392 static void print_tm_bits(unsigned long val
)
1395 * This only prints something if at least one of the TM bit is set.
1396 * Inside the TM[], the output means:
1397 * E: Enabled (bit 32)
1398 * S: Suspended (bit 33)
1399 * T: Transactional (bit 34)
1401 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1403 print_bits(val
, msr_tm_bits
, "");
1408 static void print_tm_bits(unsigned long val
) {}
1411 static void print_msr_bits(unsigned long val
)
1414 print_bits(val
, msr_bits
, ",");
1420 #define REG "%016lx"
1421 #define REGS_PER_LINE 4
1422 #define LAST_VOLATILE 13
1425 #define REGS_PER_LINE 8
1426 #define LAST_VOLATILE 12
1429 void show_regs(struct pt_regs
* regs
)
1433 show_regs_print_info(KERN_DEFAULT
);
1435 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1436 regs
->nip
, regs
->link
, regs
->ctr
);
1437 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1438 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1439 printk("MSR: "REG
" ", regs
->msr
);
1440 print_msr_bits(regs
->msr
);
1441 pr_cont(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1443 if ((TRAP(regs
) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1444 pr_cont("CFAR: "REG
" ", regs
->orig_gpr3
);
1445 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1446 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1447 pr_cont("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1449 pr_cont("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1452 pr_cont("IRQMASK: %lx ", regs
->softe
);
1454 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1455 if (MSR_TM_ACTIVE(regs
->msr
))
1456 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1459 for (i
= 0; i
< 32; i
++) {
1460 if ((i
% REGS_PER_LINE
) == 0)
1461 pr_cont("\nGPR%02d: ", i
);
1462 pr_cont(REG
" ", regs
->gpr
[i
]);
1463 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1467 #ifdef CONFIG_KALLSYMS
1469 * Lookup NIP late so we have the best change of getting the
1470 * above info out without failing
1472 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1473 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1475 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1476 if (!user_mode(regs
))
1477 show_instructions(regs
);
1480 void flush_thread(void)
1482 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1483 flush_ptrace_hw_breakpoint(current
);
1484 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1485 set_debug_reg_defaults(¤t
->thread
);
1486 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1489 #ifdef CONFIG_PPC_BOOK3S_64
1490 void arch_setup_new_exec(void)
1492 if (radix_enabled())
1494 hash__setup_new_exec();
1498 int set_thread_uses_vas(void)
1500 #ifdef CONFIG_PPC_BOOK3S_64
1501 if (!cpu_has_feature(CPU_FTR_ARCH_300
))
1504 current
->thread
.used_vas
= 1;
1507 * Even a process that has no foreign real address mapping can use
1508 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1509 * to clear any pending COPY and prevent a covert channel.
1511 * __switch_to() will issue CP_ABORT on future context switches.
1513 asm volatile(PPC_CP_ABORT
);
1515 #endif /* CONFIG_PPC_BOOK3S_64 */
1521 * Assign a TIDR (thread ID) for task @t and set it in the thread
1522 * structure. For now, we only support setting TIDR for 'current' task.
1524 * Since the TID value is a truncated form of it PID, it is possible
1525 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1526 * that 2 threads share the same TID and are waiting, one of the following
1527 * cases will happen:
1529 * 1. The correct thread is running, the wrong thread is not
1530 * In this situation, the correct thread is woken and proceeds to pass it's
1533 * 2. Neither threads are running
1534 * In this situation, neither thread will be woken. When scheduled, the waiting
1535 * threads will execute either a wait, which will return immediately, followed
1536 * by a condition check, which will pass for the correct thread and fail
1537 * for the wrong thread, or they will execute the condition check immediately.
1539 * 3. The wrong thread is running, the correct thread is not
1540 * The wrong thread will be woken, but will fail it's condition check and
1541 * re-execute wait. The correct thread, when scheduled, will execute either
1542 * it's condition check (which will pass), or wait, which returns immediately
1543 * when called the first time after the thread is scheduled, followed by it's
1544 * condition check (which will pass).
1546 * 4. Both threads are running
1547 * Both threads will be woken. The wrong thread will fail it's condition check
1548 * and execute another wait, while the correct thread will pass it's condition
1551 * @t: the task to set the thread ID for
1553 int set_thread_tidr(struct task_struct
*t
)
1555 if (!cpu_has_feature(CPU_FTR_P9_TIDR
))
1564 t
->thread
.tidr
= (u16
)task_pid_nr(t
);
1565 mtspr(SPRN_TIDR
, t
->thread
.tidr
);
1569 EXPORT_SYMBOL_GPL(set_thread_tidr
);
1571 #endif /* CONFIG_PPC64 */
1574 release_thread(struct task_struct
*t
)
1579 * this gets called so that we can store coprocessor state into memory and
1580 * copy the current task into the new thread.
1582 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1584 flush_all_to_thread(src
);
1586 * Flush TM state out so we can copy it. __switch_to_tm() does this
1587 * flush but it removes the checkpointed state from the current CPU and
1588 * transitions the CPU out of TM mode. Hence we need to call
1589 * tm_recheckpoint_new_task() (on the same task) to restore the
1590 * checkpointed state back and the TM mode.
1592 * Can't pass dst because it isn't ready. Doesn't matter, passing
1593 * dst is only important for __switch_to()
1595 __switch_to_tm(src
, src
);
1599 clear_task_ebb(dst
);
1604 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1606 #ifdef CONFIG_PPC_BOOK3S_64
1607 unsigned long sp_vsid
;
1608 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1610 if (radix_enabled())
1613 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1614 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1615 << SLB_VSID_SHIFT_1T
;
1617 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1619 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1620 p
->thread
.ksp_vsid
= sp_vsid
;
1629 * Copy architecture-specific thread state
1631 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1632 unsigned long kthread_arg
, struct task_struct
*p
)
1634 struct pt_regs
*childregs
, *kregs
;
1635 extern void ret_from_fork(void);
1636 extern void ret_from_kernel_thread(void);
1638 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1639 struct thread_info
*ti
= task_thread_info(p
);
1641 klp_init_thread_info(p
);
1643 /* Copy registers */
1644 sp
-= sizeof(struct pt_regs
);
1645 childregs
= (struct pt_regs
*) sp
;
1646 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1648 memset(childregs
, 0, sizeof(struct pt_regs
));
1649 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1652 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1654 clear_tsk_thread_flag(p
, TIF_32BIT
);
1655 childregs
->softe
= IRQS_ENABLED
;
1657 childregs
->gpr
[15] = kthread_arg
;
1658 p
->thread
.regs
= NULL
; /* no user register state */
1659 ti
->flags
|= _TIF_RESTOREALL
;
1660 f
= ret_from_kernel_thread
;
1663 struct pt_regs
*regs
= current_pt_regs();
1664 CHECK_FULL_REGS(regs
);
1667 childregs
->gpr
[1] = usp
;
1668 p
->thread
.regs
= childregs
;
1669 childregs
->gpr
[3] = 0; /* Result from fork() */
1670 if (clone_flags
& CLONE_SETTLS
) {
1672 if (!is_32bit_task())
1673 childregs
->gpr
[13] = childregs
->gpr
[6];
1676 childregs
->gpr
[2] = childregs
->gpr
[6];
1681 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1682 sp
-= STACK_FRAME_OVERHEAD
;
1685 * The way this works is that at some point in the future
1686 * some task will call _switch to switch to the new task.
1687 * That will pop off the stack frame created below and start
1688 * the new task running at ret_from_fork. The new task will
1689 * do some house keeping and then return from the fork or clone
1690 * system call, using the stack frame created above.
1692 ((unsigned long *)sp
)[0] = 0;
1693 sp
-= sizeof(struct pt_regs
);
1694 kregs
= (struct pt_regs
*) sp
;
1695 sp
-= STACK_FRAME_OVERHEAD
;
1698 p
->thread
.ksp_limit
= (unsigned long)end_of_stack(p
);
1700 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1701 p
->thread
.ptrace_bps
[0] = NULL
;
1704 p
->thread
.fp_save_area
= NULL
;
1705 #ifdef CONFIG_ALTIVEC
1706 p
->thread
.vr_save_area
= NULL
;
1709 setup_ksp_vsid(p
, sp
);
1712 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1713 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1714 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1716 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1717 childregs
->ppr
= DEFAULT_PPR
;
1721 kregs
->nip
= ppc_function_entry(f
);
1725 void preload_new_slb_context(unsigned long start
, unsigned long sp
);
1728 * Set up a thread for executing a new program
1730 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1733 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1735 #ifdef CONFIG_PPC_BOOK3S_64
1736 if (!radix_enabled())
1737 preload_new_slb_context(start
, sp
);
1742 * If we exec out of a kernel thread then thread.regs will not be
1745 if (!current
->thread
.regs
) {
1746 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1747 current
->thread
.regs
= regs
- 1;
1750 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1752 * Clear any transactional state, we're exec()ing. The cause is
1753 * not important as there will never be a recheckpoint so it's not
1756 if (MSR_TM_SUSPENDED(mfmsr()))
1757 tm_reclaim_current(0);
1760 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1768 * We have just cleared all the nonvolatile GPRs, so make
1769 * FULL_REGS(regs) return true. This is necessary to allow
1770 * ptrace to examine the thread immediately after exec.
1777 regs
->msr
= MSR_USER
;
1779 if (!is_32bit_task()) {
1780 unsigned long entry
;
1782 if (is_elf2_task()) {
1783 /* Look ma, no function descriptors! */
1788 * The latest iteration of the ABI requires that when
1789 * calling a function (at its global entry point),
1790 * the caller must ensure r12 holds the entry point
1791 * address (so that the function can quickly
1792 * establish addressability).
1794 regs
->gpr
[12] = start
;
1795 /* Make sure that's restored on entry to userspace. */
1796 set_thread_flag(TIF_RESTOREALL
);
1800 /* start is a relocated pointer to the function
1801 * descriptor for the elf _start routine. The first
1802 * entry in the function descriptor is the entry
1803 * address of _start and the second entry is the TOC
1804 * value we need to use.
1806 __get_user(entry
, (unsigned long __user
*)start
);
1807 __get_user(toc
, (unsigned long __user
*)start
+1);
1809 /* Check whether the e_entry function descriptor entries
1810 * need to be relocated before we can use them.
1812 if (load_addr
!= 0) {
1819 regs
->msr
= MSR_USER64
;
1823 regs
->msr
= MSR_USER32
;
1827 current
->thread
.used_vsr
= 0;
1829 current
->thread
.load_slb
= 0;
1830 current
->thread
.load_fp
= 0;
1831 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1832 current
->thread
.fp_save_area
= NULL
;
1833 #ifdef CONFIG_ALTIVEC
1834 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1835 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1836 current
->thread
.vr_save_area
= NULL
;
1837 current
->thread
.vrsave
= 0;
1838 current
->thread
.used_vr
= 0;
1839 current
->thread
.load_vec
= 0;
1840 #endif /* CONFIG_ALTIVEC */
1842 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1843 current
->thread
.acc
= 0;
1844 current
->thread
.spefscr
= 0;
1845 current
->thread
.used_spe
= 0;
1846 #endif /* CONFIG_SPE */
1847 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1848 current
->thread
.tm_tfhar
= 0;
1849 current
->thread
.tm_texasr
= 0;
1850 current
->thread
.tm_tfiar
= 0;
1851 current
->thread
.load_tm
= 0;
1852 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1854 thread_pkey_regs_init(¤t
->thread
);
1856 EXPORT_SYMBOL(start_thread
);
1858 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1859 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1861 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1863 struct pt_regs
*regs
= tsk
->thread
.regs
;
1865 /* This is a bit hairy. If we are an SPE enabled processor
1866 * (have embedded fp) we store the IEEE exception enable flags in
1867 * fpexc_mode. fpexc_mode is also used for setting FP exception
1868 * mode (asyn, precise, disabled) for 'Classic' FP. */
1869 if (val
& PR_FP_EXC_SW_ENABLE
) {
1871 if (cpu_has_feature(CPU_FTR_SPE
)) {
1873 * When the sticky exception bits are set
1874 * directly by userspace, it must call prctl
1875 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1876 * in the existing prctl settings) or
1877 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1878 * the bits being set). <fenv.h> functions
1879 * saving and restoring the whole
1880 * floating-point environment need to do so
1881 * anyway to restore the prctl settings from
1882 * the saved environment.
1884 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1885 tsk
->thread
.fpexc_mode
= val
&
1886 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1896 /* on a CONFIG_SPE this does not hurt us. The bits that
1897 * __pack_fe01 use do not overlap with bits used for
1898 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1899 * on CONFIG_SPE implementations are reserved so writing to
1900 * them does not change anything */
1901 if (val
> PR_FP_EXC_PRECISE
)
1903 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1904 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1905 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1906 | tsk
->thread
.fpexc_mode
;
1910 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1914 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1916 if (cpu_has_feature(CPU_FTR_SPE
)) {
1918 * When the sticky exception bits are set
1919 * directly by userspace, it must call prctl
1920 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1921 * in the existing prctl settings) or
1922 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1923 * the bits being set). <fenv.h> functions
1924 * saving and restoring the whole
1925 * floating-point environment need to do so
1926 * anyway to restore the prctl settings from
1927 * the saved environment.
1929 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1930 val
= tsk
->thread
.fpexc_mode
;
1937 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1938 return put_user(val
, (unsigned int __user
*) adr
);
1941 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1943 struct pt_regs
*regs
= tsk
->thread
.regs
;
1945 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1946 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1952 if (val
== PR_ENDIAN_BIG
)
1953 regs
->msr
&= ~MSR_LE
;
1954 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1955 regs
->msr
|= MSR_LE
;
1962 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1964 struct pt_regs
*regs
= tsk
->thread
.regs
;
1967 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1968 !cpu_has_feature(CPU_FTR_REAL_LE
))
1974 if (regs
->msr
& MSR_LE
) {
1975 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1976 val
= PR_ENDIAN_LITTLE
;
1978 val
= PR_ENDIAN_PPC_LITTLE
;
1980 val
= PR_ENDIAN_BIG
;
1982 return put_user(val
, (unsigned int __user
*)adr
);
1985 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1987 tsk
->thread
.align_ctl
= val
;
1991 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1993 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1996 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1997 unsigned long nbytes
)
1999 unsigned long stack_page
;
2000 unsigned long cpu
= task_cpu(p
);
2002 stack_page
= (unsigned long)hardirq_ctx
[cpu
];
2003 if (sp
>= stack_page
&& sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
2006 stack_page
= (unsigned long)softirq_ctx
[cpu
];
2007 if (sp
>= stack_page
&& sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
2013 int validate_sp(unsigned long sp
, struct task_struct
*p
,
2014 unsigned long nbytes
)
2016 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
2018 if (sp
< THREAD_SIZE
)
2021 if (sp
>= stack_page
&& sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
2024 return valid_irq_stack(sp
, p
, nbytes
);
2027 EXPORT_SYMBOL(validate_sp
);
2029 static unsigned long __get_wchan(struct task_struct
*p
)
2031 unsigned long ip
, sp
;
2034 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
2038 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
2042 sp
= *(unsigned long *)sp
;
2043 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
) ||
2044 p
->state
== TASK_RUNNING
)
2047 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
2048 if (!in_sched_functions(ip
))
2051 } while (count
++ < 16);
2055 unsigned long get_wchan(struct task_struct
*p
)
2059 if (!try_get_task_stack(p
))
2062 ret
= __get_wchan(p
);
2069 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
2071 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
2073 unsigned long sp
, ip
, lr
, newsp
;
2076 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2077 struct ftrace_ret_stack
*ret_stack
;
2078 extern void return_to_handler(void);
2079 unsigned long rth
= (unsigned long)return_to_handler
;
2086 if (!try_get_task_stack(tsk
))
2089 sp
= (unsigned long) stack
;
2092 sp
= current_stack_pointer();
2094 sp
= tsk
->thread
.ksp
;
2098 printk("Call Trace:\n");
2100 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
2103 stack
= (unsigned long *) sp
;
2105 ip
= stack
[STACK_FRAME_LR_SAVE
];
2106 if (!firstframe
|| ip
!= lr
) {
2107 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
2108 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2109 if ((ip
== rth
) && curr_frame
>= 0) {
2110 ret_stack
= ftrace_graph_get_ret_stack(current
,
2114 (void *)ret_stack
->ret
);
2120 pr_cont(" (unreliable)");
2126 * See if this is an exception frame.
2127 * We look for the "regshere" marker in the current frame.
2129 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
2130 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
2131 struct pt_regs
*regs
= (struct pt_regs
*)
2132 (sp
+ STACK_FRAME_OVERHEAD
);
2134 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
2135 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
2140 } while (count
++ < kstack_depth_to_print
);
2142 put_task_stack(tsk
);
2146 /* Called with hard IRQs off */
2147 void notrace
__ppc64_runlatch_on(void)
2149 struct thread_info
*ti
= current_thread_info();
2151 if (cpu_has_feature(CPU_FTR_ARCH_206
)) {
2153 * Least significant bit (RUN) is the only writable bit of
2154 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2155 * earliest ISA where this is the case, but it's convenient.
2157 mtspr(SPRN_CTRLT
, CTRL_RUNLATCH
);
2162 * Some architectures (e.g., Cell) have writable fields other
2163 * than RUN, so do the read-modify-write.
2165 ctrl
= mfspr(SPRN_CTRLF
);
2166 ctrl
|= CTRL_RUNLATCH
;
2167 mtspr(SPRN_CTRLT
, ctrl
);
2170 ti
->local_flags
|= _TLF_RUNLATCH
;
2173 /* Called with hard IRQs off */
2174 void notrace
__ppc64_runlatch_off(void)
2176 struct thread_info
*ti
= current_thread_info();
2178 ti
->local_flags
&= ~_TLF_RUNLATCH
;
2180 if (cpu_has_feature(CPU_FTR_ARCH_206
)) {
2181 mtspr(SPRN_CTRLT
, 0);
2185 ctrl
= mfspr(SPRN_CTRLF
);
2186 ctrl
&= ~CTRL_RUNLATCH
;
2187 mtspr(SPRN_CTRLT
, ctrl
);
2190 #endif /* CONFIG_PPC64 */
2192 unsigned long arch_align_stack(unsigned long sp
)
2194 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
2195 sp
-= get_random_int() & ~PAGE_MASK
;
2199 static inline unsigned long brk_rnd(void)
2201 unsigned long rnd
= 0;
2203 /* 8MB for 32bit, 1GB for 64bit */
2204 if (is_32bit_task())
2205 rnd
= (get_random_long() % (1UL<<(23-PAGE_SHIFT
)));
2207 rnd
= (get_random_long() % (1UL<<(30-PAGE_SHIFT
)));
2209 return rnd
<< PAGE_SHIFT
;
2212 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
2214 unsigned long base
= mm
->brk
;
2217 #ifdef CONFIG_PPC_BOOK3S_64
2219 * If we are using 1TB segments and we are allowed to randomise
2220 * the heap, we can put it above 1TB so it is backed by a 1TB
2221 * segment. Otherwise the heap will be in the bottom 1TB
2222 * which always uses 256MB segments and this may result in a
2223 * performance penalty. We don't need to worry about radix. For
2224 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2226 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
2227 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
2230 ret
= PAGE_ALIGN(base
+ brk_rnd());