2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/sched/debug.h>
20 #include <linux/sched/task.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/kernel.h>
24 #include <linux/smp.h>
25 #include <linux/stddef.h>
26 #include <linux/unistd.h>
27 #include <linux/ptrace.h>
28 #include <linux/slab.h>
29 #include <linux/user.h>
30 #include <linux/elf.h>
31 #include <linux/prctl.h>
32 #include <linux/init_task.h>
33 #include <linux/export.h>
34 #include <linux/kallsyms.h>
35 #include <linux/mqueue.h>
36 #include <linux/hardirq.h>
37 #include <linux/utsname.h>
38 #include <linux/ftrace.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/personality.h>
41 #include <linux/random.h>
42 #include <linux/hw_breakpoint.h>
43 #include <linux/uaccess.h>
44 #include <linux/elf-randomize.h>
45 #include <linux/pkeys.h>
46 #include <linux/seq_buf.h>
48 #include <asm/pgtable.h>
50 #include <asm/processor.h>
53 #include <asm/machdep.h>
55 #include <asm/runlatch.h>
56 #include <asm/syscalls.h>
57 #include <asm/switch_to.h>
59 #include <asm/debug.h>
61 #include <asm/firmware.h>
62 #include <asm/hw_irq.h>
64 #include <asm/code-patching.h>
66 #include <asm/livepatch.h>
67 #include <asm/cpu_has_feature.h>
68 #include <asm/asm-prototypes.h>
69 #include <asm/stacktrace.h>
71 #include <linux/kprobes.h>
72 #include <linux/kdebug.h>
74 /* Transactional Memory debug */
76 #define TM_DEBUG(x...) printk(KERN_INFO x)
78 #define TM_DEBUG(x...) do { } while(0)
81 extern unsigned long _get_SP(void);
83 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
85 * Are we running in "Suspend disabled" mode? If so we have to block any
86 * sigreturn that would get us into suspended state, and we also warn in some
87 * other paths that we should never reach with suspend disabled.
89 bool tm_suspend_disabled __ro_after_init
= false;
91 static void check_if_tm_restore_required(struct task_struct
*tsk
)
94 * If we are saving the current thread's registers, and the
95 * thread is in a transactional state, set the TIF_RESTORE_TM
96 * bit so that we know to restore the registers before
97 * returning to userspace.
99 if (tsk
== current
&& tsk
->thread
.regs
&&
100 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
101 !test_thread_flag(TIF_RESTORE_TM
)) {
102 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
103 set_thread_flag(TIF_RESTORE_TM
);
107 static bool tm_active_with_fp(struct task_struct
*tsk
)
109 return MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
110 (tsk
->thread
.ckpt_regs
.msr
& MSR_FP
);
113 static bool tm_active_with_altivec(struct task_struct
*tsk
)
115 return MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
116 (tsk
->thread
.ckpt_regs
.msr
& MSR_VEC
);
119 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
120 static inline bool tm_active_with_fp(struct task_struct
*tsk
) { return false; }
121 static inline bool tm_active_with_altivec(struct task_struct
*tsk
) { return false; }
122 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
124 bool strict_msr_control
;
125 EXPORT_SYMBOL(strict_msr_control
);
127 static int __init
enable_strict_msr_control(char *str
)
129 strict_msr_control
= true;
130 pr_info("Enabling strict facility control\n");
134 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
136 unsigned long msr_check_and_set(unsigned long bits
)
138 unsigned long oldmsr
= mfmsr();
139 unsigned long newmsr
;
141 newmsr
= oldmsr
| bits
;
144 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
148 if (oldmsr
!= newmsr
)
153 EXPORT_SYMBOL_GPL(msr_check_and_set
);
155 void __msr_check_and_clear(unsigned long bits
)
157 unsigned long oldmsr
= mfmsr();
158 unsigned long newmsr
;
160 newmsr
= oldmsr
& ~bits
;
163 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
167 if (oldmsr
!= newmsr
)
170 EXPORT_SYMBOL(__msr_check_and_clear
);
172 #ifdef CONFIG_PPC_FPU
173 static void __giveup_fpu(struct task_struct
*tsk
)
178 msr
= tsk
->thread
.regs
->msr
;
179 msr
&= ~(MSR_FP
|MSR_FE0
|MSR_FE1
);
181 if (cpu_has_feature(CPU_FTR_VSX
))
184 tsk
->thread
.regs
->msr
= msr
;
187 void giveup_fpu(struct task_struct
*tsk
)
189 check_if_tm_restore_required(tsk
);
191 msr_check_and_set(MSR_FP
);
193 msr_check_and_clear(MSR_FP
);
195 EXPORT_SYMBOL(giveup_fpu
);
198 * Make sure the floating-point register state in the
199 * the thread_struct is up to date for task tsk.
201 void flush_fp_to_thread(struct task_struct
*tsk
)
203 if (tsk
->thread
.regs
) {
205 * We need to disable preemption here because if we didn't,
206 * another process could get scheduled after the regs->msr
207 * test but before we have finished saving the FP registers
208 * to the thread_struct. That process could take over the
209 * FPU, and then when we get scheduled again we would store
210 * bogus values for the remaining FP registers.
213 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
215 * This should only ever be called for current or
216 * for a stopped child process. Since we save away
217 * the FP register state on context switch,
218 * there is something wrong if a stopped child appears
219 * to still have its FP state in the CPU registers.
221 BUG_ON(tsk
!= current
);
227 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
229 void enable_kernel_fp(void)
231 unsigned long cpumsr
;
233 WARN_ON(preemptible());
235 cpumsr
= msr_check_and_set(MSR_FP
);
237 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
238 check_if_tm_restore_required(current
);
240 * If a thread has already been reclaimed then the
241 * checkpointed registers are on the CPU but have definitely
242 * been saved by the reclaim code. Don't need to and *cannot*
243 * giveup as this would save to the 'live' structure not the
244 * checkpointed structure.
246 if (!MSR_TM_ACTIVE(cpumsr
) &&
247 MSR_TM_ACTIVE(current
->thread
.regs
->msr
))
249 __giveup_fpu(current
);
252 EXPORT_SYMBOL(enable_kernel_fp
);
254 static int restore_fp(struct task_struct
*tsk
)
256 if (tsk
->thread
.load_fp
|| tm_active_with_fp(tsk
)) {
257 load_fp_state(¤t
->thread
.fp_state
);
258 current
->thread
.load_fp
++;
264 static int restore_fp(struct task_struct
*tsk
) { return 0; }
265 #endif /* CONFIG_PPC_FPU */
267 #ifdef CONFIG_ALTIVEC
268 #define loadvec(thr) ((thr).load_vec)
270 static void __giveup_altivec(struct task_struct
*tsk
)
275 msr
= tsk
->thread
.regs
->msr
;
278 if (cpu_has_feature(CPU_FTR_VSX
))
281 tsk
->thread
.regs
->msr
= msr
;
284 void giveup_altivec(struct task_struct
*tsk
)
286 check_if_tm_restore_required(tsk
);
288 msr_check_and_set(MSR_VEC
);
289 __giveup_altivec(tsk
);
290 msr_check_and_clear(MSR_VEC
);
292 EXPORT_SYMBOL(giveup_altivec
);
294 void enable_kernel_altivec(void)
296 unsigned long cpumsr
;
298 WARN_ON(preemptible());
300 cpumsr
= msr_check_and_set(MSR_VEC
);
302 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
303 check_if_tm_restore_required(current
);
305 * If a thread has already been reclaimed then the
306 * checkpointed registers are on the CPU but have definitely
307 * been saved by the reclaim code. Don't need to and *cannot*
308 * giveup as this would save to the 'live' structure not the
309 * checkpointed structure.
311 if (!MSR_TM_ACTIVE(cpumsr
) &&
312 MSR_TM_ACTIVE(current
->thread
.regs
->msr
))
314 __giveup_altivec(current
);
317 EXPORT_SYMBOL(enable_kernel_altivec
);
320 * Make sure the VMX/Altivec register state in the
321 * the thread_struct is up to date for task tsk.
323 void flush_altivec_to_thread(struct task_struct
*tsk
)
325 if (tsk
->thread
.regs
) {
327 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
328 BUG_ON(tsk
!= current
);
334 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
336 static int restore_altivec(struct task_struct
*tsk
)
338 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
339 (tsk
->thread
.load_vec
|| tm_active_with_altivec(tsk
))) {
340 load_vr_state(&tsk
->thread
.vr_state
);
341 tsk
->thread
.used_vr
= 1;
342 tsk
->thread
.load_vec
++;
349 #define loadvec(thr) 0
350 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
351 #endif /* CONFIG_ALTIVEC */
354 static void __giveup_vsx(struct task_struct
*tsk
)
356 unsigned long msr
= tsk
->thread
.regs
->msr
;
359 * We should never be ssetting MSR_VSX without also setting
362 WARN_ON((msr
& MSR_VSX
) && !((msr
& MSR_FP
) && (msr
& MSR_VEC
)));
364 /* __giveup_fpu will clear MSR_VSX */
368 __giveup_altivec(tsk
);
371 static void giveup_vsx(struct task_struct
*tsk
)
373 check_if_tm_restore_required(tsk
);
375 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
377 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
380 void enable_kernel_vsx(void)
382 unsigned long cpumsr
;
384 WARN_ON(preemptible());
386 cpumsr
= msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
388 if (current
->thread
.regs
&&
389 (current
->thread
.regs
->msr
& (MSR_VSX
|MSR_VEC
|MSR_FP
))) {
390 check_if_tm_restore_required(current
);
392 * If a thread has already been reclaimed then the
393 * checkpointed registers are on the CPU but have definitely
394 * been saved by the reclaim code. Don't need to and *cannot*
395 * giveup as this would save to the 'live' structure not the
396 * checkpointed structure.
398 if (!MSR_TM_ACTIVE(cpumsr
) &&
399 MSR_TM_ACTIVE(current
->thread
.regs
->msr
))
401 __giveup_vsx(current
);
404 EXPORT_SYMBOL(enable_kernel_vsx
);
406 void flush_vsx_to_thread(struct task_struct
*tsk
)
408 if (tsk
->thread
.regs
) {
410 if (tsk
->thread
.regs
->msr
& (MSR_VSX
|MSR_VEC
|MSR_FP
)) {
411 BUG_ON(tsk
!= current
);
417 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
419 static int restore_vsx(struct task_struct
*tsk
)
421 if (cpu_has_feature(CPU_FTR_VSX
)) {
422 tsk
->thread
.used_vsr
= 1;
429 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
430 #endif /* CONFIG_VSX */
433 void giveup_spe(struct task_struct
*tsk
)
435 check_if_tm_restore_required(tsk
);
437 msr_check_and_set(MSR_SPE
);
439 msr_check_and_clear(MSR_SPE
);
441 EXPORT_SYMBOL(giveup_spe
);
443 void enable_kernel_spe(void)
445 WARN_ON(preemptible());
447 msr_check_and_set(MSR_SPE
);
449 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
450 check_if_tm_restore_required(current
);
451 __giveup_spe(current
);
454 EXPORT_SYMBOL(enable_kernel_spe
);
456 void flush_spe_to_thread(struct task_struct
*tsk
)
458 if (tsk
->thread
.regs
) {
460 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
461 BUG_ON(tsk
!= current
);
462 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
468 #endif /* CONFIG_SPE */
470 static unsigned long msr_all_available
;
472 static int __init
init_msr_all_available(void)
474 #ifdef CONFIG_PPC_FPU
475 msr_all_available
|= MSR_FP
;
477 #ifdef CONFIG_ALTIVEC
478 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
479 msr_all_available
|= MSR_VEC
;
482 if (cpu_has_feature(CPU_FTR_VSX
))
483 msr_all_available
|= MSR_VSX
;
486 if (cpu_has_feature(CPU_FTR_SPE
))
487 msr_all_available
|= MSR_SPE
;
492 early_initcall(init_msr_all_available
);
494 void giveup_all(struct task_struct
*tsk
)
496 unsigned long usermsr
;
498 if (!tsk
->thread
.regs
)
501 usermsr
= tsk
->thread
.regs
->msr
;
503 if ((usermsr
& msr_all_available
) == 0)
506 msr_check_and_set(msr_all_available
);
507 check_if_tm_restore_required(tsk
);
509 WARN_ON((usermsr
& MSR_VSX
) && !((usermsr
& MSR_FP
) && (usermsr
& MSR_VEC
)));
511 #ifdef CONFIG_PPC_FPU
512 if (usermsr
& MSR_FP
)
515 #ifdef CONFIG_ALTIVEC
516 if (usermsr
& MSR_VEC
)
517 __giveup_altivec(tsk
);
520 if (usermsr
& MSR_SPE
)
524 msr_check_and_clear(msr_all_available
);
526 EXPORT_SYMBOL(giveup_all
);
528 void restore_math(struct pt_regs
*regs
)
532 if (!MSR_TM_ACTIVE(regs
->msr
) &&
533 !current
->thread
.load_fp
&& !loadvec(current
->thread
))
537 msr_check_and_set(msr_all_available
);
540 * Only reload if the bit is not set in the user MSR, the bit BEING set
541 * indicates that the registers are hot
543 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
544 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
546 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
549 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
550 restore_vsx(current
)) {
554 msr_check_and_clear(msr_all_available
);
559 static void save_all(struct task_struct
*tsk
)
561 unsigned long usermsr
;
563 if (!tsk
->thread
.regs
)
566 usermsr
= tsk
->thread
.regs
->msr
;
568 if ((usermsr
& msr_all_available
) == 0)
571 msr_check_and_set(msr_all_available
);
573 WARN_ON((usermsr
& MSR_VSX
) && !((usermsr
& MSR_FP
) && (usermsr
& MSR_VEC
)));
575 if (usermsr
& MSR_FP
)
578 if (usermsr
& MSR_VEC
)
581 if (usermsr
& MSR_SPE
)
584 msr_check_and_clear(msr_all_available
);
585 thread_pkey_regs_save(&tsk
->thread
);
588 void flush_all_to_thread(struct task_struct
*tsk
)
590 if (tsk
->thread
.regs
) {
592 BUG_ON(tsk
!= current
);
594 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
595 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
602 EXPORT_SYMBOL(flush_all_to_thread
);
604 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
605 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
606 unsigned long error_code
, int breakpt
)
608 current
->thread
.trap_nr
= TRAP_HWBKPT
;
609 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
610 11, SIGSEGV
) == NOTIFY_STOP
)
613 /* Deliver the signal to userspace */
614 force_sig_ptrace_errno_trap(breakpt
, /* breakpoint or watchpoint id */
615 (void __user
*)address
);
617 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
618 void do_break (struct pt_regs
*regs
, unsigned long address
,
619 unsigned long error_code
)
621 current
->thread
.trap_nr
= TRAP_HWBKPT
;
622 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
623 11, SIGSEGV
) == NOTIFY_STOP
)
626 if (debugger_break_match(regs
))
629 /* Clear the breakpoint */
630 hw_breakpoint_disable();
632 /* Deliver the signal to userspace */
633 force_sig_fault(SIGTRAP
, TRAP_HWBKPT
, (void __user
*)address
, current
);
635 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
637 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
639 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
641 * Set the debug registers back to their default "safe" values.
643 static void set_debug_reg_defaults(struct thread_struct
*thread
)
645 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
646 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
647 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
649 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
650 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
651 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
653 thread
->debug
.dbcr0
= 0;
656 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
658 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
659 DBCR1_IAC3US
| DBCR1_IAC4US
;
661 * Force Data Address Compare User/Supervisor bits to be User-only
662 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
664 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
666 thread
->debug
.dbcr1
= 0;
670 static void prime_debug_regs(struct debug_reg
*debug
)
673 * We could have inherited MSR_DE from userspace, since
674 * it doesn't get cleared on exception entry. Make sure
675 * MSR_DE is clear before we enable any debug events.
677 mtmsr(mfmsr() & ~MSR_DE
);
679 mtspr(SPRN_IAC1
, debug
->iac1
);
680 mtspr(SPRN_IAC2
, debug
->iac2
);
681 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
682 mtspr(SPRN_IAC3
, debug
->iac3
);
683 mtspr(SPRN_IAC4
, debug
->iac4
);
685 mtspr(SPRN_DAC1
, debug
->dac1
);
686 mtspr(SPRN_DAC2
, debug
->dac2
);
687 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
688 mtspr(SPRN_DVC1
, debug
->dvc1
);
689 mtspr(SPRN_DVC2
, debug
->dvc2
);
691 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
692 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
694 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
698 * Unless neither the old or new thread are making use of the
699 * debug registers, set the debug registers from the values
700 * stored in the new thread.
702 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
704 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
705 || (new_debug
->dbcr0
& DBCR0_IDM
))
706 prime_debug_regs(new_debug
);
708 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
709 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
710 #ifndef CONFIG_HAVE_HW_BREAKPOINT
711 static void set_breakpoint(struct arch_hw_breakpoint
*brk
)
714 __set_breakpoint(brk
);
718 static void set_debug_reg_defaults(struct thread_struct
*thread
)
720 thread
->hw_brk
.address
= 0;
721 thread
->hw_brk
.type
= 0;
722 if (ppc_breakpoint_available())
723 set_breakpoint(&thread
->hw_brk
);
725 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
726 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
728 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
729 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
731 mtspr(SPRN_DAC1
, dabr
);
732 #ifdef CONFIG_PPC_47x
737 #elif defined(CONFIG_PPC_BOOK3S)
738 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
740 mtspr(SPRN_DABR
, dabr
);
741 if (cpu_has_feature(CPU_FTR_DABRX
))
742 mtspr(SPRN_DABRX
, dabrx
);
745 #elif defined(CONFIG_PPC_8xx)
746 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
748 unsigned long addr
= dabr
& ~HW_BRK_TYPE_DABR
;
749 unsigned long lctrl1
= 0x90000000; /* compare type: equal on E & F */
750 unsigned long lctrl2
= 0x8e000002; /* watchpoint 1 on cmp E | F */
752 if ((dabr
& HW_BRK_TYPE_RDWR
) == HW_BRK_TYPE_READ
)
754 else if ((dabr
& HW_BRK_TYPE_RDWR
) == HW_BRK_TYPE_WRITE
)
756 else if ((dabr
& HW_BRK_TYPE_RDWR
) == 0)
759 mtspr(SPRN_LCTRL2
, 0);
760 mtspr(SPRN_CMPE
, addr
);
761 mtspr(SPRN_CMPF
, addr
+ 4);
762 mtspr(SPRN_LCTRL1
, lctrl1
);
763 mtspr(SPRN_LCTRL2
, lctrl2
);
768 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
774 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
776 unsigned long dabr
, dabrx
;
778 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
779 dabrx
= ((brk
->type
>> 3) & 0x7);
782 return ppc_md
.set_dabr(dabr
, dabrx
);
784 return __set_dabr(dabr
, dabrx
);
787 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
789 unsigned long dawr
, dawrx
, mrd
;
793 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
794 << (63 - 58); //* read/write bits */
795 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
796 << (63 - 59); //* translate */
797 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
798 >> 3; //* PRIM bits */
799 /* dawr length is stored in field MDR bits 48:53. Matches range in
800 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
802 brk->len is in bytes.
803 This aligns up to double word size, shifts and does the bias.
805 mrd
= ((brk
->len
+ 7) >> 3) - 1;
806 dawrx
|= (mrd
& 0x3f) << (63 - 53);
809 return ppc_md
.set_dawr(dawr
, dawrx
);
810 mtspr(SPRN_DAWR
, dawr
);
811 mtspr(SPRN_DAWRX
, dawrx
);
815 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
817 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
819 if (cpu_has_feature(CPU_FTR_DAWR
))
822 else if (!cpu_has_feature(CPU_FTR_ARCH_207S
))
826 // Shouldn't happen due to higher level checks
830 /* Check if we have DAWR or DABR hardware */
831 bool ppc_breakpoint_available(void)
833 if (cpu_has_feature(CPU_FTR_DAWR
))
834 return true; /* POWER8 DAWR */
835 if (cpu_has_feature(CPU_FTR_ARCH_207S
))
836 return false; /* POWER9 with DAWR disabled */
837 /* DABR: Everything but POWER8 and POWER9 */
840 EXPORT_SYMBOL_GPL(ppc_breakpoint_available
);
842 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
843 struct arch_hw_breakpoint
*b
)
845 if (a
->address
!= b
->address
)
847 if (a
->type
!= b
->type
)
849 if (a
->len
!= b
->len
)
854 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
856 static inline bool tm_enabled(struct task_struct
*tsk
)
858 return tsk
&& tsk
->thread
.regs
&& (tsk
->thread
.regs
->msr
& MSR_TM
);
861 static void tm_reclaim_thread(struct thread_struct
*thr
, uint8_t cause
)
864 * Use the current MSR TM suspended bit to track if we have
865 * checkpointed state outstanding.
866 * On signal delivery, we'd normally reclaim the checkpointed
867 * state to obtain stack pointer (see:get_tm_stackpointer()).
868 * This will then directly return to userspace without going
869 * through __switch_to(). However, if the stack frame is bad,
870 * we need to exit this thread which calls __switch_to() which
871 * will again attempt to reclaim the already saved tm state.
872 * Hence we need to check that we've not already reclaimed
874 * We do this using the current MSR, rather tracking it in
875 * some specific thread_struct bit, as it has the additional
876 * benefit of checking for a potential TM bad thing exception.
878 if (!MSR_TM_SUSPENDED(mfmsr()))
881 giveup_all(container_of(thr
, struct task_struct
, thread
));
883 tm_reclaim(thr
, cause
);
886 * If we are in a transaction and FP is off then we can't have
887 * used FP inside that transaction. Hence the checkpointed
888 * state is the same as the live state. We need to copy the
889 * live state to the checkpointed state so that when the
890 * transaction is restored, the checkpointed state is correct
891 * and the aborted transaction sees the correct state. We use
892 * ckpt_regs.msr here as that's what tm_reclaim will use to
893 * determine if it's going to write the checkpointed state or
894 * not. So either this will write the checkpointed registers,
895 * or reclaim will. Similarly for VMX.
897 if ((thr
->ckpt_regs
.msr
& MSR_FP
) == 0)
898 memcpy(&thr
->ckfp_state
, &thr
->fp_state
,
899 sizeof(struct thread_fp_state
));
900 if ((thr
->ckpt_regs
.msr
& MSR_VEC
) == 0)
901 memcpy(&thr
->ckvr_state
, &thr
->vr_state
,
902 sizeof(struct thread_vr_state
));
905 void tm_reclaim_current(uint8_t cause
)
908 tm_reclaim_thread(¤t
->thread
, cause
);
911 static inline void tm_reclaim_task(struct task_struct
*tsk
)
913 /* We have to work out if we're switching from/to a task that's in the
914 * middle of a transaction.
916 * In switching we need to maintain a 2nd register state as
917 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
918 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
921 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
923 struct thread_struct
*thr
= &tsk
->thread
;
928 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
929 goto out_and_saveregs
;
931 WARN_ON(tm_suspend_disabled
);
933 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
934 "ccr=%lx, msr=%lx, trap=%lx)\n",
935 tsk
->pid
, thr
->regs
->nip
,
936 thr
->regs
->ccr
, thr
->regs
->msr
,
939 tm_reclaim_thread(thr
, TM_CAUSE_RESCHED
);
941 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
945 /* Always save the regs here, even if a transaction's not active.
946 * This context-switches a thread's TM info SPRs. We do it here to
947 * be consistent with the restore path (in recheckpoint) which
948 * cannot happen later in _switch().
953 extern void __tm_recheckpoint(struct thread_struct
*thread
);
955 void tm_recheckpoint(struct thread_struct
*thread
)
959 if (!(thread
->regs
->msr
& MSR_TM
))
962 /* We really can't be interrupted here as the TEXASR registers can't
963 * change and later in the trecheckpoint code, we have a userspace R1.
964 * So let's hard disable over this region.
966 local_irq_save(flags
);
969 /* The TM SPRs are restored here, so that TEXASR.FS can be set
970 * before the trecheckpoint and no explosion occurs.
972 tm_restore_sprs(thread
);
974 __tm_recheckpoint(thread
);
976 local_irq_restore(flags
);
979 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
981 if (!cpu_has_feature(CPU_FTR_TM
))
984 /* Recheckpoint the registers of the thread we're about to switch to.
986 * If the task was using FP, we non-lazily reload both the original and
987 * the speculative FP register states. This is because the kernel
988 * doesn't see if/when a TM rollback occurs, so if we take an FP
989 * unavailable later, we are unable to determine which set of FP regs
990 * need to be restored.
992 if (!tm_enabled(new))
995 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
996 tm_restore_sprs(&new->thread
);
999 /* Recheckpoint to restore original checkpointed register state. */
1000 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1001 new->pid
, new->thread
.regs
->msr
);
1003 tm_recheckpoint(&new->thread
);
1006 * The checkpointed state has been restored but the live state has
1007 * not, ensure all the math functionality is turned off to trigger
1008 * restore_math() to reload.
1010 new->thread
.regs
->msr
&= ~(MSR_FP
| MSR_VEC
| MSR_VSX
);
1012 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1013 "(kernel msr 0x%lx)\n",
1017 static inline void __switch_to_tm(struct task_struct
*prev
,
1018 struct task_struct
*new)
1020 if (cpu_has_feature(CPU_FTR_TM
)) {
1021 if (tm_enabled(prev
) || tm_enabled(new))
1024 if (tm_enabled(prev
)) {
1025 prev
->thread
.load_tm
++;
1026 tm_reclaim_task(prev
);
1027 if (!MSR_TM_ACTIVE(prev
->thread
.regs
->msr
) && prev
->thread
.load_tm
== 0)
1028 prev
->thread
.regs
->msr
&= ~MSR_TM
;
1031 tm_recheckpoint_new_task(new);
1036 * This is called if we are on the way out to userspace and the
1037 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1038 * FP and/or vector state and does so if necessary.
1039 * If userspace is inside a transaction (whether active or
1040 * suspended) and FP/VMX/VSX instructions have ever been enabled
1041 * inside that transaction, then we have to keep them enabled
1042 * and keep the FP/VMX/VSX state loaded while ever the transaction
1043 * continues. The reason is that if we didn't, and subsequently
1044 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1045 * we don't know whether it's the same transaction, and thus we
1046 * don't know which of the checkpointed state and the transactional
1049 void restore_tm_state(struct pt_regs
*regs
)
1051 unsigned long msr_diff
;
1054 * This is the only moment we should clear TIF_RESTORE_TM as
1055 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1056 * again, anything else could lead to an incorrect ckpt_msr being
1057 * saved and therefore incorrect signal contexts.
1059 clear_thread_flag(TIF_RESTORE_TM
);
1060 if (!MSR_TM_ACTIVE(regs
->msr
))
1063 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
1064 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
1066 /* Ensure that restore_math() will restore */
1067 if (msr_diff
& MSR_FP
)
1068 current
->thread
.load_fp
= 1;
1069 #ifdef CONFIG_ALTIVEC
1070 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && msr_diff
& MSR_VEC
)
1071 current
->thread
.load_vec
= 1;
1075 regs
->msr
|= msr_diff
;
1079 #define tm_recheckpoint_new_task(new)
1080 #define __switch_to_tm(prev, new)
1081 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1083 static inline void save_sprs(struct thread_struct
*t
)
1085 #ifdef CONFIG_ALTIVEC
1086 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
1087 t
->vrsave
= mfspr(SPRN_VRSAVE
);
1089 #ifdef CONFIG_PPC_BOOK3S_64
1090 if (cpu_has_feature(CPU_FTR_DSCR
))
1091 t
->dscr
= mfspr(SPRN_DSCR
);
1093 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1094 t
->bescr
= mfspr(SPRN_BESCR
);
1095 t
->ebbhr
= mfspr(SPRN_EBBHR
);
1096 t
->ebbrr
= mfspr(SPRN_EBBRR
);
1098 t
->fscr
= mfspr(SPRN_FSCR
);
1101 * Note that the TAR is not available for use in the kernel.
1102 * (To provide this, the TAR should be backed up/restored on
1103 * exception entry/exit instead, and be in pt_regs. FIXME,
1104 * this should be in pt_regs anyway (for debug).)
1106 t
->tar
= mfspr(SPRN_TAR
);
1110 thread_pkey_regs_save(t
);
1113 static inline void restore_sprs(struct thread_struct
*old_thread
,
1114 struct thread_struct
*new_thread
)
1116 #ifdef CONFIG_ALTIVEC
1117 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
1118 old_thread
->vrsave
!= new_thread
->vrsave
)
1119 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
1121 #ifdef CONFIG_PPC_BOOK3S_64
1122 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1123 u64 dscr
= get_paca()->dscr_default
;
1124 if (new_thread
->dscr_inherit
)
1125 dscr
= new_thread
->dscr
;
1127 if (old_thread
->dscr
!= dscr
)
1128 mtspr(SPRN_DSCR
, dscr
);
1131 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1132 if (old_thread
->bescr
!= new_thread
->bescr
)
1133 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1134 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1135 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1136 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1137 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1139 if (old_thread
->fscr
!= new_thread
->fscr
)
1140 mtspr(SPRN_FSCR
, new_thread
->fscr
);
1142 if (old_thread
->tar
!= new_thread
->tar
)
1143 mtspr(SPRN_TAR
, new_thread
->tar
);
1146 if (cpu_has_feature(CPU_FTR_P9_TIDR
) &&
1147 old_thread
->tidr
!= new_thread
->tidr
)
1148 mtspr(SPRN_TIDR
, new_thread
->tidr
);
1151 thread_pkey_regs_restore(new_thread
, old_thread
);
1154 #ifdef CONFIG_PPC_BOOK3S_64
1156 static const u8 dummy_copy_buffer
[CP_SIZE
] __attribute__((aligned(CP_SIZE
)));
1159 struct task_struct
*__switch_to(struct task_struct
*prev
,
1160 struct task_struct
*new)
1162 struct thread_struct
*new_thread
, *old_thread
;
1163 struct task_struct
*last
;
1164 #ifdef CONFIG_PPC_BOOK3S_64
1165 struct ppc64_tlb_batch
*batch
;
1168 new_thread
= &new->thread
;
1169 old_thread
= ¤t
->thread
;
1171 WARN_ON(!irqs_disabled());
1173 #ifdef CONFIG_PPC_BOOK3S_64
1174 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1175 if (batch
->active
) {
1176 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1178 __flush_tlb_pending(batch
);
1181 #endif /* CONFIG_PPC_BOOK3S_64 */
1183 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1184 switch_booke_debug_regs(&new->thread
.debug
);
1187 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1190 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1191 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1192 __set_breakpoint(&new->thread
.hw_brk
);
1193 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1197 * We need to save SPRs before treclaim/trecheckpoint as these will
1198 * change a number of them.
1200 save_sprs(&prev
->thread
);
1202 /* Save FPU, Altivec, VSX and SPE state */
1205 __switch_to_tm(prev
, new);
1207 if (!radix_enabled()) {
1209 * We can't take a PMU exception inside _switch() since there
1210 * is a window where the kernel stack SLB and the kernel stack
1211 * are out of sync. Hard disable here.
1217 * Call restore_sprs() before calling _switch(). If we move it after
1218 * _switch() then we miss out on calling it for new tasks. The reason
1219 * for this is we manually create a stack frame for new tasks that
1220 * directly returns through ret_from_fork() or
1221 * ret_from_kernel_thread(). See copy_thread() for details.
1223 restore_sprs(old_thread
, new_thread
);
1225 last
= _switch(old_thread
, new_thread
);
1227 #ifdef CONFIG_PPC_BOOK3S_64
1228 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1229 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1230 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1234 if (current
->thread
.regs
) {
1235 restore_math(current
->thread
.regs
);
1238 * The copy-paste buffer can only store into foreign real
1239 * addresses, so unprivileged processes can not see the
1240 * data or use it in any way unless they have foreign real
1241 * mappings. If the new process has the foreign real address
1242 * mappings, we must issue a cp_abort to clear any state and
1243 * prevent snooping, corruption or a covert channel.
1245 if (current
->thread
.used_vas
)
1246 asm volatile(PPC_CP_ABORT
);
1248 #endif /* CONFIG_PPC_BOOK3S_64 */
1253 #define NR_INSN_TO_PRINT 16
1255 static void show_instructions(struct pt_regs
*regs
)
1258 unsigned long pc
= regs
->nip
- (NR_INSN_TO_PRINT
* 3 / 4 * sizeof(int));
1260 printk("Instruction dump:");
1262 for (i
= 0; i
< NR_INSN_TO_PRINT
; i
++) {
1268 #if !defined(CONFIG_BOOKE)
1269 /* If executing with the IMMU off, adjust pc rather
1270 * than print XXXXXXXX.
1272 if (!(regs
->msr
& MSR_IR
))
1273 pc
= (unsigned long)phys_to_virt(pc
);
1276 if (!__kernel_text_address(pc
) ||
1277 probe_kernel_address((const void *)pc
, instr
)) {
1278 pr_cont("XXXXXXXX ");
1280 if (regs
->nip
== pc
)
1281 pr_cont("<%08x> ", instr
);
1283 pr_cont("%08x ", instr
);
1292 void show_user_instructions(struct pt_regs
*regs
)
1295 int n
= NR_INSN_TO_PRINT
;
1297 char buf
[96]; /* enough for 8 times 9 + 2 chars */
1299 pc
= regs
->nip
- (NR_INSN_TO_PRINT
* 3 / 4 * sizeof(int));
1302 * Make sure the NIP points at userspace, not kernel text/data or
1305 if (!__access_ok(pc
, NR_INSN_TO_PRINT
* sizeof(int), USER_DS
)) {
1306 pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
1307 current
->comm
, current
->pid
);
1311 seq_buf_init(&s
, buf
, sizeof(buf
));
1318 for (i
= 0; i
< 8 && n
; i
++, n
--, pc
+= sizeof(int)) {
1321 if (probe_kernel_address((const void *)pc
, instr
)) {
1322 seq_buf_printf(&s
, "XXXXXXXX ");
1325 seq_buf_printf(&s
, regs
->nip
== pc
? "<%08x> " : "%08x ", instr
);
1328 if (!seq_buf_has_overflowed(&s
))
1329 pr_info("%s[%d]: code: %s\n", current
->comm
,
1330 current
->pid
, s
.buffer
);
1339 static struct regbit msr_bits
[] = {
1340 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1362 #ifndef CONFIG_BOOKE
1369 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1373 for (; bits
->bit
; ++bits
)
1374 if (val
& bits
->bit
) {
1375 pr_cont("%s%s", s
, bits
->name
);
1380 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1381 static struct regbit msr_tm_bits
[] = {
1388 static void print_tm_bits(unsigned long val
)
1391 * This only prints something if at least one of the TM bit is set.
1392 * Inside the TM[], the output means:
1393 * E: Enabled (bit 32)
1394 * S: Suspended (bit 33)
1395 * T: Transactional (bit 34)
1397 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1399 print_bits(val
, msr_tm_bits
, "");
1404 static void print_tm_bits(unsigned long val
) {}
1407 static void print_msr_bits(unsigned long val
)
1410 print_bits(val
, msr_bits
, ",");
1416 #define REG "%016lx"
1417 #define REGS_PER_LINE 4
1418 #define LAST_VOLATILE 13
1421 #define REGS_PER_LINE 8
1422 #define LAST_VOLATILE 12
1425 void show_regs(struct pt_regs
* regs
)
1429 show_regs_print_info(KERN_DEFAULT
);
1431 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1432 regs
->nip
, regs
->link
, regs
->ctr
);
1433 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1434 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1435 printk("MSR: "REG
" ", regs
->msr
);
1436 print_msr_bits(regs
->msr
);
1437 pr_cont(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1439 if ((TRAP(regs
) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1440 pr_cont("CFAR: "REG
" ", regs
->orig_gpr3
);
1441 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1442 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1443 pr_cont("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1445 pr_cont("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1448 pr_cont("IRQMASK: %lx ", regs
->softe
);
1450 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1451 if (MSR_TM_ACTIVE(regs
->msr
))
1452 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1455 for (i
= 0; i
< 32; i
++) {
1456 if ((i
% REGS_PER_LINE
) == 0)
1457 pr_cont("\nGPR%02d: ", i
);
1458 pr_cont(REG
" ", regs
->gpr
[i
]);
1459 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1463 #ifdef CONFIG_KALLSYMS
1465 * Lookup NIP late so we have the best change of getting the
1466 * above info out without failing
1468 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1469 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1471 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1472 if (!user_mode(regs
))
1473 show_instructions(regs
);
1476 void flush_thread(void)
1478 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1479 flush_ptrace_hw_breakpoint(current
);
1480 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1481 set_debug_reg_defaults(¤t
->thread
);
1482 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1485 #ifdef CONFIG_PPC_BOOK3S_64
1486 void arch_setup_new_exec(void)
1488 if (radix_enabled())
1490 hash__setup_new_exec();
1494 int set_thread_uses_vas(void)
1496 #ifdef CONFIG_PPC_BOOK3S_64
1497 if (!cpu_has_feature(CPU_FTR_ARCH_300
))
1500 current
->thread
.used_vas
= 1;
1503 * Even a process that has no foreign real address mapping can use
1504 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1505 * to clear any pending COPY and prevent a covert channel.
1507 * __switch_to() will issue CP_ABORT on future context switches.
1509 asm volatile(PPC_CP_ABORT
);
1511 #endif /* CONFIG_PPC_BOOK3S_64 */
1517 * Assign a TIDR (thread ID) for task @t and set it in the thread
1518 * structure. For now, we only support setting TIDR for 'current' task.
1520 * Since the TID value is a truncated form of it PID, it is possible
1521 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1522 * that 2 threads share the same TID and are waiting, one of the following
1523 * cases will happen:
1525 * 1. The correct thread is running, the wrong thread is not
1526 * In this situation, the correct thread is woken and proceeds to pass it's
1529 * 2. Neither threads are running
1530 * In this situation, neither thread will be woken. When scheduled, the waiting
1531 * threads will execute either a wait, which will return immediately, followed
1532 * by a condition check, which will pass for the correct thread and fail
1533 * for the wrong thread, or they will execute the condition check immediately.
1535 * 3. The wrong thread is running, the correct thread is not
1536 * The wrong thread will be woken, but will fail it's condition check and
1537 * re-execute wait. The correct thread, when scheduled, will execute either
1538 * it's condition check (which will pass), or wait, which returns immediately
1539 * when called the first time after the thread is scheduled, followed by it's
1540 * condition check (which will pass).
1542 * 4. Both threads are running
1543 * Both threads will be woken. The wrong thread will fail it's condition check
1544 * and execute another wait, while the correct thread will pass it's condition
1547 * @t: the task to set the thread ID for
1549 int set_thread_tidr(struct task_struct
*t
)
1551 if (!cpu_has_feature(CPU_FTR_P9_TIDR
))
1560 t
->thread
.tidr
= (u16
)task_pid_nr(t
);
1561 mtspr(SPRN_TIDR
, t
->thread
.tidr
);
1565 EXPORT_SYMBOL_GPL(set_thread_tidr
);
1567 #endif /* CONFIG_PPC64 */
1570 release_thread(struct task_struct
*t
)
1575 * this gets called so that we can store coprocessor state into memory and
1576 * copy the current task into the new thread.
1578 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1580 flush_all_to_thread(src
);
1582 * Flush TM state out so we can copy it. __switch_to_tm() does this
1583 * flush but it removes the checkpointed state from the current CPU and
1584 * transitions the CPU out of TM mode. Hence we need to call
1585 * tm_recheckpoint_new_task() (on the same task) to restore the
1586 * checkpointed state back and the TM mode.
1588 * Can't pass dst because it isn't ready. Doesn't matter, passing
1589 * dst is only important for __switch_to()
1591 __switch_to_tm(src
, src
);
1595 clear_task_ebb(dst
);
1600 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1602 #ifdef CONFIG_PPC_BOOK3S_64
1603 unsigned long sp_vsid
;
1604 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1606 if (radix_enabled())
1609 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1610 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1611 << SLB_VSID_SHIFT_1T
;
1613 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1615 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1616 p
->thread
.ksp_vsid
= sp_vsid
;
1625 * Copy architecture-specific thread state
1627 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1628 unsigned long kthread_arg
, struct task_struct
*p
)
1630 struct pt_regs
*childregs
, *kregs
;
1631 extern void ret_from_fork(void);
1632 extern void ret_from_kernel_thread(void);
1634 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1635 struct thread_info
*ti
= task_thread_info(p
);
1637 klp_init_thread_info(p
);
1639 /* Copy registers */
1640 sp
-= sizeof(struct pt_regs
);
1641 childregs
= (struct pt_regs
*) sp
;
1642 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1644 memset(childregs
, 0, sizeof(struct pt_regs
));
1645 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1648 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1650 clear_tsk_thread_flag(p
, TIF_32BIT
);
1651 childregs
->softe
= IRQS_ENABLED
;
1653 childregs
->gpr
[15] = kthread_arg
;
1654 p
->thread
.regs
= NULL
; /* no user register state */
1655 ti
->flags
|= _TIF_RESTOREALL
;
1656 f
= ret_from_kernel_thread
;
1659 struct pt_regs
*regs
= current_pt_regs();
1660 CHECK_FULL_REGS(regs
);
1663 childregs
->gpr
[1] = usp
;
1664 p
->thread
.regs
= childregs
;
1665 childregs
->gpr
[3] = 0; /* Result from fork() */
1666 if (clone_flags
& CLONE_SETTLS
) {
1668 if (!is_32bit_task())
1669 childregs
->gpr
[13] = childregs
->gpr
[6];
1672 childregs
->gpr
[2] = childregs
->gpr
[6];
1677 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1678 sp
-= STACK_FRAME_OVERHEAD
;
1681 * The way this works is that at some point in the future
1682 * some task will call _switch to switch to the new task.
1683 * That will pop off the stack frame created below and start
1684 * the new task running at ret_from_fork. The new task will
1685 * do some house keeping and then return from the fork or clone
1686 * system call, using the stack frame created above.
1688 ((unsigned long *)sp
)[0] = 0;
1689 sp
-= sizeof(struct pt_regs
);
1690 kregs
= (struct pt_regs
*) sp
;
1691 sp
-= STACK_FRAME_OVERHEAD
;
1694 p
->thread
.ksp_limit
= (unsigned long)end_of_stack(p
);
1696 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1697 p
->thread
.ptrace_bps
[0] = NULL
;
1700 p
->thread
.fp_save_area
= NULL
;
1701 #ifdef CONFIG_ALTIVEC
1702 p
->thread
.vr_save_area
= NULL
;
1705 setup_ksp_vsid(p
, sp
);
1708 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1709 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1710 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1712 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1713 childregs
->ppr
= DEFAULT_PPR
;
1717 kregs
->nip
= ppc_function_entry(f
);
1721 void preload_new_slb_context(unsigned long start
, unsigned long sp
);
1724 * Set up a thread for executing a new program
1726 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1729 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1731 #ifdef CONFIG_PPC_BOOK3S_64
1732 preload_new_slb_context(start
, sp
);
1737 * If we exec out of a kernel thread then thread.regs will not be
1740 if (!current
->thread
.regs
) {
1741 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1742 current
->thread
.regs
= regs
- 1;
1745 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1747 * Clear any transactional state, we're exec()ing. The cause is
1748 * not important as there will never be a recheckpoint so it's not
1751 if (MSR_TM_SUSPENDED(mfmsr()))
1752 tm_reclaim_current(0);
1755 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1763 * We have just cleared all the nonvolatile GPRs, so make
1764 * FULL_REGS(regs) return true. This is necessary to allow
1765 * ptrace to examine the thread immediately after exec.
1772 regs
->msr
= MSR_USER
;
1774 if (!is_32bit_task()) {
1775 unsigned long entry
;
1777 if (is_elf2_task()) {
1778 /* Look ma, no function descriptors! */
1783 * The latest iteration of the ABI requires that when
1784 * calling a function (at its global entry point),
1785 * the caller must ensure r12 holds the entry point
1786 * address (so that the function can quickly
1787 * establish addressability).
1789 regs
->gpr
[12] = start
;
1790 /* Make sure that's restored on entry to userspace. */
1791 set_thread_flag(TIF_RESTOREALL
);
1795 /* start is a relocated pointer to the function
1796 * descriptor for the elf _start routine. The first
1797 * entry in the function descriptor is the entry
1798 * address of _start and the second entry is the TOC
1799 * value we need to use.
1801 __get_user(entry
, (unsigned long __user
*)start
);
1802 __get_user(toc
, (unsigned long __user
*)start
+1);
1804 /* Check whether the e_entry function descriptor entries
1805 * need to be relocated before we can use them.
1807 if (load_addr
!= 0) {
1814 regs
->msr
= MSR_USER64
;
1818 regs
->msr
= MSR_USER32
;
1822 current
->thread
.used_vsr
= 0;
1824 current
->thread
.load_slb
= 0;
1825 current
->thread
.load_fp
= 0;
1826 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1827 current
->thread
.fp_save_area
= NULL
;
1828 #ifdef CONFIG_ALTIVEC
1829 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1830 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1831 current
->thread
.vr_save_area
= NULL
;
1832 current
->thread
.vrsave
= 0;
1833 current
->thread
.used_vr
= 0;
1834 current
->thread
.load_vec
= 0;
1835 #endif /* CONFIG_ALTIVEC */
1837 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1838 current
->thread
.acc
= 0;
1839 current
->thread
.spefscr
= 0;
1840 current
->thread
.used_spe
= 0;
1841 #endif /* CONFIG_SPE */
1842 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1843 current
->thread
.tm_tfhar
= 0;
1844 current
->thread
.tm_texasr
= 0;
1845 current
->thread
.tm_tfiar
= 0;
1846 current
->thread
.load_tm
= 0;
1847 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1849 thread_pkey_regs_init(¤t
->thread
);
1851 EXPORT_SYMBOL(start_thread
);
1853 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1854 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1856 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1858 struct pt_regs
*regs
= tsk
->thread
.regs
;
1860 /* This is a bit hairy. If we are an SPE enabled processor
1861 * (have embedded fp) we store the IEEE exception enable flags in
1862 * fpexc_mode. fpexc_mode is also used for setting FP exception
1863 * mode (asyn, precise, disabled) for 'Classic' FP. */
1864 if (val
& PR_FP_EXC_SW_ENABLE
) {
1866 if (cpu_has_feature(CPU_FTR_SPE
)) {
1868 * When the sticky exception bits are set
1869 * directly by userspace, it must call prctl
1870 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1871 * in the existing prctl settings) or
1872 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1873 * the bits being set). <fenv.h> functions
1874 * saving and restoring the whole
1875 * floating-point environment need to do so
1876 * anyway to restore the prctl settings from
1877 * the saved environment.
1879 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1880 tsk
->thread
.fpexc_mode
= val
&
1881 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1891 /* on a CONFIG_SPE this does not hurt us. The bits that
1892 * __pack_fe01 use do not overlap with bits used for
1893 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1894 * on CONFIG_SPE implementations are reserved so writing to
1895 * them does not change anything */
1896 if (val
> PR_FP_EXC_PRECISE
)
1898 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1899 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1900 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1901 | tsk
->thread
.fpexc_mode
;
1905 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1909 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1911 if (cpu_has_feature(CPU_FTR_SPE
)) {
1913 * When the sticky exception bits are set
1914 * directly by userspace, it must call prctl
1915 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1916 * in the existing prctl settings) or
1917 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1918 * the bits being set). <fenv.h> functions
1919 * saving and restoring the whole
1920 * floating-point environment need to do so
1921 * anyway to restore the prctl settings from
1922 * the saved environment.
1924 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1925 val
= tsk
->thread
.fpexc_mode
;
1932 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1933 return put_user(val
, (unsigned int __user
*) adr
);
1936 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1938 struct pt_regs
*regs
= tsk
->thread
.regs
;
1940 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1941 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1947 if (val
== PR_ENDIAN_BIG
)
1948 regs
->msr
&= ~MSR_LE
;
1949 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1950 regs
->msr
|= MSR_LE
;
1957 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1959 struct pt_regs
*regs
= tsk
->thread
.regs
;
1962 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1963 !cpu_has_feature(CPU_FTR_REAL_LE
))
1969 if (regs
->msr
& MSR_LE
) {
1970 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1971 val
= PR_ENDIAN_LITTLE
;
1973 val
= PR_ENDIAN_PPC_LITTLE
;
1975 val
= PR_ENDIAN_BIG
;
1977 return put_user(val
, (unsigned int __user
*)adr
);
1980 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1982 tsk
->thread
.align_ctl
= val
;
1986 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1988 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1991 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1992 unsigned long nbytes
)
1994 unsigned long stack_page
;
1995 unsigned long cpu
= task_cpu(p
);
1997 stack_page
= (unsigned long)hardirq_ctx
[cpu
];
1998 if (sp
>= stack_page
&& sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
2001 stack_page
= (unsigned long)softirq_ctx
[cpu
];
2002 if (sp
>= stack_page
&& sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
2008 int validate_sp(unsigned long sp
, struct task_struct
*p
,
2009 unsigned long nbytes
)
2011 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
2013 if (sp
< THREAD_SIZE
)
2016 if (sp
>= stack_page
&& sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
2019 return valid_irq_stack(sp
, p
, nbytes
);
2022 EXPORT_SYMBOL(validate_sp
);
2024 static unsigned long __get_wchan(struct task_struct
*p
)
2026 unsigned long ip
, sp
;
2029 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
2033 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
2037 sp
= *(unsigned long *)sp
;
2038 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
) ||
2039 p
->state
== TASK_RUNNING
)
2042 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
2043 if (!in_sched_functions(ip
))
2046 } while (count
++ < 16);
2050 unsigned long get_wchan(struct task_struct
*p
)
2054 if (!try_get_task_stack(p
))
2057 ret
= __get_wchan(p
);
2064 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
2066 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
2068 unsigned long sp
, ip
, lr
, newsp
;
2071 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2072 struct ftrace_ret_stack
*ret_stack
;
2073 extern void return_to_handler(void);
2074 unsigned long rth
= (unsigned long)return_to_handler
;
2081 if (!try_get_task_stack(tsk
))
2084 sp
= (unsigned long) stack
;
2087 sp
= current_stack_pointer();
2089 sp
= tsk
->thread
.ksp
;
2093 printk("Call Trace:\n");
2095 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
2098 stack
= (unsigned long *) sp
;
2100 ip
= stack
[STACK_FRAME_LR_SAVE
];
2101 if (!firstframe
|| ip
!= lr
) {
2102 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
2103 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2104 if ((ip
== rth
) && curr_frame
>= 0) {
2105 ret_stack
= ftrace_graph_get_ret_stack(current
,
2109 (void *)ret_stack
->ret
);
2115 pr_cont(" (unreliable)");
2121 * See if this is an exception frame.
2122 * We look for the "regshere" marker in the current frame.
2124 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
2125 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
2126 struct pt_regs
*regs
= (struct pt_regs
*)
2127 (sp
+ STACK_FRAME_OVERHEAD
);
2129 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
2130 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
2135 } while (count
++ < kstack_depth_to_print
);
2137 put_task_stack(tsk
);
2141 /* Called with hard IRQs off */
2142 void notrace
__ppc64_runlatch_on(void)
2144 struct thread_info
*ti
= current_thread_info();
2146 if (cpu_has_feature(CPU_FTR_ARCH_206
)) {
2148 * Least significant bit (RUN) is the only writable bit of
2149 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2150 * earliest ISA where this is the case, but it's convenient.
2152 mtspr(SPRN_CTRLT
, CTRL_RUNLATCH
);
2157 * Some architectures (e.g., Cell) have writable fields other
2158 * than RUN, so do the read-modify-write.
2160 ctrl
= mfspr(SPRN_CTRLF
);
2161 ctrl
|= CTRL_RUNLATCH
;
2162 mtspr(SPRN_CTRLT
, ctrl
);
2165 ti
->local_flags
|= _TLF_RUNLATCH
;
2168 /* Called with hard IRQs off */
2169 void notrace
__ppc64_runlatch_off(void)
2171 struct thread_info
*ti
= current_thread_info();
2173 ti
->local_flags
&= ~_TLF_RUNLATCH
;
2175 if (cpu_has_feature(CPU_FTR_ARCH_206
)) {
2176 mtspr(SPRN_CTRLT
, 0);
2180 ctrl
= mfspr(SPRN_CTRLF
);
2181 ctrl
&= ~CTRL_RUNLATCH
;
2182 mtspr(SPRN_CTRLT
, ctrl
);
2185 #endif /* CONFIG_PPC64 */
2187 unsigned long arch_align_stack(unsigned long sp
)
2189 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
2190 sp
-= get_random_int() & ~PAGE_MASK
;
2194 static inline unsigned long brk_rnd(void)
2196 unsigned long rnd
= 0;
2198 /* 8MB for 32bit, 1GB for 64bit */
2199 if (is_32bit_task())
2200 rnd
= (get_random_long() % (1UL<<(23-PAGE_SHIFT
)));
2202 rnd
= (get_random_long() % (1UL<<(30-PAGE_SHIFT
)));
2204 return rnd
<< PAGE_SHIFT
;
2207 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
2209 unsigned long base
= mm
->brk
;
2212 #ifdef CONFIG_PPC_BOOK3S_64
2214 * If we are using 1TB segments and we are allowed to randomise
2215 * the heap, we can put it above 1TB so it is backed by a 1TB
2216 * segment. Otherwise the heap will be in the bottom 1TB
2217 * which always uses 256MB segments and this may result in a
2218 * performance penalty. We don't need to worry about radix. For
2219 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2221 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
2222 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
2225 ret
= PAGE_ALIGN(base
+ brk_rnd());