2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/prctl.h>
29 #include <linux/init_task.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/mqueue.h>
33 #include <linux/hardirq.h>
34 #include <linux/utsname.h>
35 #include <linux/ftrace.h>
36 #include <linux/kernel_stat.h>
37 #include <linux/personality.h>
38 #include <linux/random.h>
39 #include <linux/hw_breakpoint.h>
40 #include <linux/uaccess.h>
41 #include <linux/elf-randomize.h>
43 #include <asm/pgtable.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
58 #include <asm/code-patching.h>
60 #include <asm/livepatch.h>
61 #include <asm/cpu_has_feature.h>
62 #include <asm/asm-prototypes.h>
64 #include <linux/kprobes.h>
65 #include <linux/kdebug.h>
67 /* Transactional Memory debug */
69 #define TM_DEBUG(x...) printk(KERN_INFO x)
71 #define TM_DEBUG(x...) do { } while(0)
74 extern unsigned long _get_SP(void);
76 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
77 static void check_if_tm_restore_required(struct task_struct
*tsk
)
80 * If we are saving the current thread's registers, and the
81 * thread is in a transactional state, set the TIF_RESTORE_TM
82 * bit so that we know to restore the registers before
83 * returning to userspace.
85 if (tsk
== current
&& tsk
->thread
.regs
&&
86 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
87 !test_thread_flag(TIF_RESTORE_TM
)) {
88 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
89 set_thread_flag(TIF_RESTORE_TM
);
93 static inline bool msr_tm_active(unsigned long msr
)
95 return MSR_TM_ACTIVE(msr
);
98 static inline bool msr_tm_active(unsigned long msr
) { return false; }
99 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
100 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
102 bool strict_msr_control
;
103 EXPORT_SYMBOL(strict_msr_control
);
105 static int __init
enable_strict_msr_control(char *str
)
107 strict_msr_control
= true;
108 pr_info("Enabling strict facility control\n");
112 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
114 unsigned long msr_check_and_set(unsigned long bits
)
116 unsigned long oldmsr
= mfmsr();
117 unsigned long newmsr
;
119 newmsr
= oldmsr
| bits
;
122 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
126 if (oldmsr
!= newmsr
)
132 void __msr_check_and_clear(unsigned long bits
)
134 unsigned long oldmsr
= mfmsr();
135 unsigned long newmsr
;
137 newmsr
= oldmsr
& ~bits
;
140 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
144 if (oldmsr
!= newmsr
)
147 EXPORT_SYMBOL(__msr_check_and_clear
);
149 #ifdef CONFIG_PPC_FPU
150 void __giveup_fpu(struct task_struct
*tsk
)
155 msr
= tsk
->thread
.regs
->msr
;
158 if (cpu_has_feature(CPU_FTR_VSX
))
161 tsk
->thread
.regs
->msr
= msr
;
164 void giveup_fpu(struct task_struct
*tsk
)
166 check_if_tm_restore_required(tsk
);
168 msr_check_and_set(MSR_FP
);
170 msr_check_and_clear(MSR_FP
);
172 EXPORT_SYMBOL(giveup_fpu
);
175 * Make sure the floating-point register state in the
176 * the thread_struct is up to date for task tsk.
178 void flush_fp_to_thread(struct task_struct
*tsk
)
180 if (tsk
->thread
.regs
) {
182 * We need to disable preemption here because if we didn't,
183 * another process could get scheduled after the regs->msr
184 * test but before we have finished saving the FP registers
185 * to the thread_struct. That process could take over the
186 * FPU, and then when we get scheduled again we would store
187 * bogus values for the remaining FP registers.
190 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
192 * This should only ever be called for current or
193 * for a stopped child process. Since we save away
194 * the FP register state on context switch,
195 * there is something wrong if a stopped child appears
196 * to still have its FP state in the CPU registers.
198 BUG_ON(tsk
!= current
);
204 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
206 void enable_kernel_fp(void)
208 unsigned long cpumsr
;
210 WARN_ON(preemptible());
212 cpumsr
= msr_check_and_set(MSR_FP
);
214 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
215 check_if_tm_restore_required(current
);
217 * If a thread has already been reclaimed then the
218 * checkpointed registers are on the CPU but have definitely
219 * been saved by the reclaim code. Don't need to and *cannot*
220 * giveup as this would save to the 'live' structure not the
221 * checkpointed structure.
223 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
225 __giveup_fpu(current
);
228 EXPORT_SYMBOL(enable_kernel_fp
);
230 static int restore_fp(struct task_struct
*tsk
) {
231 if (tsk
->thread
.load_fp
|| msr_tm_active(tsk
->thread
.regs
->msr
)) {
232 load_fp_state(¤t
->thread
.fp_state
);
233 current
->thread
.load_fp
++;
239 static int restore_fp(struct task_struct
*tsk
) { return 0; }
240 #endif /* CONFIG_PPC_FPU */
242 #ifdef CONFIG_ALTIVEC
243 #define loadvec(thr) ((thr).load_vec)
245 static void __giveup_altivec(struct task_struct
*tsk
)
250 msr
= tsk
->thread
.regs
->msr
;
253 if (cpu_has_feature(CPU_FTR_VSX
))
256 tsk
->thread
.regs
->msr
= msr
;
259 void giveup_altivec(struct task_struct
*tsk
)
261 check_if_tm_restore_required(tsk
);
263 msr_check_and_set(MSR_VEC
);
264 __giveup_altivec(tsk
);
265 msr_check_and_clear(MSR_VEC
);
267 EXPORT_SYMBOL(giveup_altivec
);
269 void enable_kernel_altivec(void)
271 unsigned long cpumsr
;
273 WARN_ON(preemptible());
275 cpumsr
= msr_check_and_set(MSR_VEC
);
277 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
278 check_if_tm_restore_required(current
);
280 * If a thread has already been reclaimed then the
281 * checkpointed registers are on the CPU but have definitely
282 * been saved by the reclaim code. Don't need to and *cannot*
283 * giveup as this would save to the 'live' structure not the
284 * checkpointed structure.
286 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
288 __giveup_altivec(current
);
291 EXPORT_SYMBOL(enable_kernel_altivec
);
294 * Make sure the VMX/Altivec register state in the
295 * the thread_struct is up to date for task tsk.
297 void flush_altivec_to_thread(struct task_struct
*tsk
)
299 if (tsk
->thread
.regs
) {
301 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
302 BUG_ON(tsk
!= current
);
308 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
310 static int restore_altivec(struct task_struct
*tsk
)
312 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
313 (tsk
->thread
.load_vec
|| msr_tm_active(tsk
->thread
.regs
->msr
))) {
314 load_vr_state(&tsk
->thread
.vr_state
);
315 tsk
->thread
.used_vr
= 1;
316 tsk
->thread
.load_vec
++;
323 #define loadvec(thr) 0
324 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
325 #endif /* CONFIG_ALTIVEC */
328 static void __giveup_vsx(struct task_struct
*tsk
)
330 if (tsk
->thread
.regs
->msr
& MSR_FP
)
332 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
333 __giveup_altivec(tsk
);
334 tsk
->thread
.regs
->msr
&= ~MSR_VSX
;
337 static void giveup_vsx(struct task_struct
*tsk
)
339 check_if_tm_restore_required(tsk
);
341 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
343 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
346 static void save_vsx(struct task_struct
*tsk
)
348 if (tsk
->thread
.regs
->msr
& MSR_FP
)
350 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
354 void enable_kernel_vsx(void)
356 unsigned long cpumsr
;
358 WARN_ON(preemptible());
360 cpumsr
= msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
362 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VSX
)) {
363 check_if_tm_restore_required(current
);
365 * If a thread has already been reclaimed then the
366 * checkpointed registers are on the CPU but have definitely
367 * been saved by the reclaim code. Don't need to and *cannot*
368 * giveup as this would save to the 'live' structure not the
369 * checkpointed structure.
371 if(!msr_tm_active(cpumsr
) && msr_tm_active(current
->thread
.regs
->msr
))
373 if (current
->thread
.regs
->msr
& MSR_FP
)
374 __giveup_fpu(current
);
375 if (current
->thread
.regs
->msr
& MSR_VEC
)
376 __giveup_altivec(current
);
377 __giveup_vsx(current
);
380 EXPORT_SYMBOL(enable_kernel_vsx
);
382 void flush_vsx_to_thread(struct task_struct
*tsk
)
384 if (tsk
->thread
.regs
) {
386 if (tsk
->thread
.regs
->msr
& MSR_VSX
) {
387 BUG_ON(tsk
!= current
);
393 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
395 static int restore_vsx(struct task_struct
*tsk
)
397 if (cpu_has_feature(CPU_FTR_VSX
)) {
398 tsk
->thread
.used_vsr
= 1;
405 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
406 static inline void save_vsx(struct task_struct
*tsk
) { }
407 #endif /* CONFIG_VSX */
410 void giveup_spe(struct task_struct
*tsk
)
412 check_if_tm_restore_required(tsk
);
414 msr_check_and_set(MSR_SPE
);
416 msr_check_and_clear(MSR_SPE
);
418 EXPORT_SYMBOL(giveup_spe
);
420 void enable_kernel_spe(void)
422 WARN_ON(preemptible());
424 msr_check_and_set(MSR_SPE
);
426 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
427 check_if_tm_restore_required(current
);
428 __giveup_spe(current
);
431 EXPORT_SYMBOL(enable_kernel_spe
);
433 void flush_spe_to_thread(struct task_struct
*tsk
)
435 if (tsk
->thread
.regs
) {
437 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
438 BUG_ON(tsk
!= current
);
439 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
445 #endif /* CONFIG_SPE */
447 static unsigned long msr_all_available
;
449 static int __init
init_msr_all_available(void)
451 #ifdef CONFIG_PPC_FPU
452 msr_all_available
|= MSR_FP
;
454 #ifdef CONFIG_ALTIVEC
455 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
456 msr_all_available
|= MSR_VEC
;
459 if (cpu_has_feature(CPU_FTR_VSX
))
460 msr_all_available
|= MSR_VSX
;
463 if (cpu_has_feature(CPU_FTR_SPE
))
464 msr_all_available
|= MSR_SPE
;
469 early_initcall(init_msr_all_available
);
471 void giveup_all(struct task_struct
*tsk
)
473 unsigned long usermsr
;
475 if (!tsk
->thread
.regs
)
478 usermsr
= tsk
->thread
.regs
->msr
;
480 if ((usermsr
& msr_all_available
) == 0)
483 msr_check_and_set(msr_all_available
);
484 check_if_tm_restore_required(tsk
);
486 #ifdef CONFIG_PPC_FPU
487 if (usermsr
& MSR_FP
)
490 #ifdef CONFIG_ALTIVEC
491 if (usermsr
& MSR_VEC
)
492 __giveup_altivec(tsk
);
495 if (usermsr
& MSR_VSX
)
499 if (usermsr
& MSR_SPE
)
503 msr_check_and_clear(msr_all_available
);
505 EXPORT_SYMBOL(giveup_all
);
507 void restore_math(struct pt_regs
*regs
)
511 if (!msr_tm_active(regs
->msr
) &&
512 !current
->thread
.load_fp
&& !loadvec(current
->thread
))
516 msr_check_and_set(msr_all_available
);
519 * Only reload if the bit is not set in the user MSR, the bit BEING set
520 * indicates that the registers are hot
522 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
523 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
525 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
528 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
529 restore_vsx(current
)) {
533 msr_check_and_clear(msr_all_available
);
538 void save_all(struct task_struct
*tsk
)
540 unsigned long usermsr
;
542 if (!tsk
->thread
.regs
)
545 usermsr
= tsk
->thread
.regs
->msr
;
547 if ((usermsr
& msr_all_available
) == 0)
550 msr_check_and_set(msr_all_available
);
553 * Saving the way the register space is in hardware, save_vsx boils
554 * down to a save_fpu() and save_altivec()
556 if (usermsr
& MSR_VSX
) {
559 if (usermsr
& MSR_FP
)
562 if (usermsr
& MSR_VEC
)
566 if (usermsr
& MSR_SPE
)
569 msr_check_and_clear(msr_all_available
);
572 void flush_all_to_thread(struct task_struct
*tsk
)
574 if (tsk
->thread
.regs
) {
576 BUG_ON(tsk
!= current
);
580 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
581 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
587 EXPORT_SYMBOL(flush_all_to_thread
);
589 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
590 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
591 unsigned long error_code
, int signal_code
, int breakpt
)
595 current
->thread
.trap_nr
= signal_code
;
596 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
597 11, SIGSEGV
) == NOTIFY_STOP
)
600 /* Deliver the signal to userspace */
601 info
.si_signo
= SIGTRAP
;
602 info
.si_errno
= breakpt
; /* breakpoint or watchpoint id */
603 info
.si_code
= signal_code
;
604 info
.si_addr
= (void __user
*)address
;
605 force_sig_info(SIGTRAP
, &info
, current
);
607 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
608 void do_break (struct pt_regs
*regs
, unsigned long address
,
609 unsigned long error_code
)
613 current
->thread
.trap_nr
= TRAP_HWBKPT
;
614 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
615 11, SIGSEGV
) == NOTIFY_STOP
)
618 if (debugger_break_match(regs
))
621 /* Clear the breakpoint */
622 hw_breakpoint_disable();
624 /* Deliver the signal to userspace */
625 info
.si_signo
= SIGTRAP
;
627 info
.si_code
= TRAP_HWBKPT
;
628 info
.si_addr
= (void __user
*)address
;
629 force_sig_info(SIGTRAP
, &info
, current
);
631 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
633 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
635 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
637 * Set the debug registers back to their default "safe" values.
639 static void set_debug_reg_defaults(struct thread_struct
*thread
)
641 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
642 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
643 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
645 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
646 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
647 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
649 thread
->debug
.dbcr0
= 0;
652 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
654 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
655 DBCR1_IAC3US
| DBCR1_IAC4US
;
657 * Force Data Address Compare User/Supervisor bits to be User-only
658 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
660 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
662 thread
->debug
.dbcr1
= 0;
666 static void prime_debug_regs(struct debug_reg
*debug
)
669 * We could have inherited MSR_DE from userspace, since
670 * it doesn't get cleared on exception entry. Make sure
671 * MSR_DE is clear before we enable any debug events.
673 mtmsr(mfmsr() & ~MSR_DE
);
675 mtspr(SPRN_IAC1
, debug
->iac1
);
676 mtspr(SPRN_IAC2
, debug
->iac2
);
677 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
678 mtspr(SPRN_IAC3
, debug
->iac3
);
679 mtspr(SPRN_IAC4
, debug
->iac4
);
681 mtspr(SPRN_DAC1
, debug
->dac1
);
682 mtspr(SPRN_DAC2
, debug
->dac2
);
683 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
684 mtspr(SPRN_DVC1
, debug
->dvc1
);
685 mtspr(SPRN_DVC2
, debug
->dvc2
);
687 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
688 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
690 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
694 * Unless neither the old or new thread are making use of the
695 * debug registers, set the debug registers from the values
696 * stored in the new thread.
698 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
700 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
701 || (new_debug
->dbcr0
& DBCR0_IDM
))
702 prime_debug_regs(new_debug
);
704 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
705 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
706 #ifndef CONFIG_HAVE_HW_BREAKPOINT
707 static void set_debug_reg_defaults(struct thread_struct
*thread
)
709 thread
->hw_brk
.address
= 0;
710 thread
->hw_brk
.type
= 0;
711 set_breakpoint(&thread
->hw_brk
);
713 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
714 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
716 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
717 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
719 mtspr(SPRN_DAC1
, dabr
);
720 #ifdef CONFIG_PPC_47x
725 #elif defined(CONFIG_PPC_BOOK3S)
726 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
728 mtspr(SPRN_DABR
, dabr
);
729 if (cpu_has_feature(CPU_FTR_DABRX
))
730 mtspr(SPRN_DABRX
, dabrx
);
734 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
740 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
742 unsigned long dabr
, dabrx
;
744 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
745 dabrx
= ((brk
->type
>> 3) & 0x7);
748 return ppc_md
.set_dabr(dabr
, dabrx
);
750 return __set_dabr(dabr
, dabrx
);
753 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
755 unsigned long dawr
, dawrx
, mrd
;
759 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
760 << (63 - 58); //* read/write bits */
761 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
762 << (63 - 59); //* translate */
763 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
764 >> 3; //* PRIM bits */
765 /* dawr length is stored in field MDR bits 48:53. Matches range in
766 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
768 brk->len is in bytes.
769 This aligns up to double word size, shifts and does the bias.
771 mrd
= ((brk
->len
+ 7) >> 3) - 1;
772 dawrx
|= (mrd
& 0x3f) << (63 - 53);
775 return ppc_md
.set_dawr(dawr
, dawrx
);
776 mtspr(SPRN_DAWR
, dawr
);
777 mtspr(SPRN_DAWRX
, dawrx
);
781 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
783 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
785 if (cpu_has_feature(CPU_FTR_DAWR
))
791 void set_breakpoint(struct arch_hw_breakpoint
*brk
)
794 __set_breakpoint(brk
);
799 DEFINE_PER_CPU(struct cpu_usage
, cpu_usage_array
);
802 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
803 struct arch_hw_breakpoint
*b
)
805 if (a
->address
!= b
->address
)
807 if (a
->type
!= b
->type
)
809 if (a
->len
!= b
->len
)
814 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
816 static inline bool tm_enabled(struct task_struct
*tsk
)
818 return tsk
&& tsk
->thread
.regs
&& (tsk
->thread
.regs
->msr
& MSR_TM
);
821 static void tm_reclaim_thread(struct thread_struct
*thr
,
822 struct thread_info
*ti
, uint8_t cause
)
825 * Use the current MSR TM suspended bit to track if we have
826 * checkpointed state outstanding.
827 * On signal delivery, we'd normally reclaim the checkpointed
828 * state to obtain stack pointer (see:get_tm_stackpointer()).
829 * This will then directly return to userspace without going
830 * through __switch_to(). However, if the stack frame is bad,
831 * we need to exit this thread which calls __switch_to() which
832 * will again attempt to reclaim the already saved tm state.
833 * Hence we need to check that we've not already reclaimed
835 * We do this using the current MSR, rather tracking it in
836 * some specific thread_struct bit, as it has the additional
837 * benefit of checking for a potential TM bad thing exception.
839 if (!MSR_TM_SUSPENDED(mfmsr()))
842 giveup_all(container_of(thr
, struct task_struct
, thread
));
844 tm_reclaim(thr
, thr
->ckpt_regs
.msr
, cause
);
847 void tm_reclaim_current(uint8_t cause
)
850 tm_reclaim_thread(¤t
->thread
, current_thread_info(), cause
);
853 static inline void tm_reclaim_task(struct task_struct
*tsk
)
855 /* We have to work out if we're switching from/to a task that's in the
856 * middle of a transaction.
858 * In switching we need to maintain a 2nd register state as
859 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
860 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
863 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
865 struct thread_struct
*thr
= &tsk
->thread
;
870 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
871 goto out_and_saveregs
;
873 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
874 "ccr=%lx, msr=%lx, trap=%lx)\n",
875 tsk
->pid
, thr
->regs
->nip
,
876 thr
->regs
->ccr
, thr
->regs
->msr
,
879 tm_reclaim_thread(thr
, task_thread_info(tsk
), TM_CAUSE_RESCHED
);
881 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
885 /* Always save the regs here, even if a transaction's not active.
886 * This context-switches a thread's TM info SPRs. We do it here to
887 * be consistent with the restore path (in recheckpoint) which
888 * cannot happen later in _switch().
893 extern void __tm_recheckpoint(struct thread_struct
*thread
,
894 unsigned long orig_msr
);
896 void tm_recheckpoint(struct thread_struct
*thread
,
897 unsigned long orig_msr
)
901 if (!(thread
->regs
->msr
& MSR_TM
))
904 /* We really can't be interrupted here as the TEXASR registers can't
905 * change and later in the trecheckpoint code, we have a userspace R1.
906 * So let's hard disable over this region.
908 local_irq_save(flags
);
911 /* The TM SPRs are restored here, so that TEXASR.FS can be set
912 * before the trecheckpoint and no explosion occurs.
914 tm_restore_sprs(thread
);
916 __tm_recheckpoint(thread
, orig_msr
);
918 local_irq_restore(flags
);
921 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
925 if (!cpu_has_feature(CPU_FTR_TM
))
928 /* Recheckpoint the registers of the thread we're about to switch to.
930 * If the task was using FP, we non-lazily reload both the original and
931 * the speculative FP register states. This is because the kernel
932 * doesn't see if/when a TM rollback occurs, so if we take an FP
933 * unavailable later, we are unable to determine which set of FP regs
934 * need to be restored.
936 if (!tm_enabled(new))
939 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
940 tm_restore_sprs(&new->thread
);
943 msr
= new->thread
.ckpt_regs
.msr
;
944 /* Recheckpoint to restore original checkpointed register state. */
945 TM_DEBUG("*** tm_recheckpoint of pid %d "
946 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
947 new->pid
, new->thread
.regs
->msr
, msr
);
949 tm_recheckpoint(&new->thread
, msr
);
952 * The checkpointed state has been restored but the live state has
953 * not, ensure all the math functionality is turned off to trigger
954 * restore_math() to reload.
956 new->thread
.regs
->msr
&= ~(MSR_FP
| MSR_VEC
| MSR_VSX
);
958 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
959 "(kernel msr 0x%lx)\n",
963 static inline void __switch_to_tm(struct task_struct
*prev
,
964 struct task_struct
*new)
966 if (cpu_has_feature(CPU_FTR_TM
)) {
967 if (tm_enabled(prev
) || tm_enabled(new))
970 if (tm_enabled(prev
)) {
971 prev
->thread
.load_tm
++;
972 tm_reclaim_task(prev
);
973 if (!MSR_TM_ACTIVE(prev
->thread
.regs
->msr
) && prev
->thread
.load_tm
== 0)
974 prev
->thread
.regs
->msr
&= ~MSR_TM
;
977 tm_recheckpoint_new_task(new);
982 * This is called if we are on the way out to userspace and the
983 * TIF_RESTORE_TM flag is set. It checks if we need to reload
984 * FP and/or vector state and does so if necessary.
985 * If userspace is inside a transaction (whether active or
986 * suspended) and FP/VMX/VSX instructions have ever been enabled
987 * inside that transaction, then we have to keep them enabled
988 * and keep the FP/VMX/VSX state loaded while ever the transaction
989 * continues. The reason is that if we didn't, and subsequently
990 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
991 * we don't know whether it's the same transaction, and thus we
992 * don't know which of the checkpointed state and the transactional
995 void restore_tm_state(struct pt_regs
*regs
)
997 unsigned long msr_diff
;
1000 * This is the only moment we should clear TIF_RESTORE_TM as
1001 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1002 * again, anything else could lead to an incorrect ckpt_msr being
1003 * saved and therefore incorrect signal contexts.
1005 clear_thread_flag(TIF_RESTORE_TM
);
1006 if (!MSR_TM_ACTIVE(regs
->msr
))
1009 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
1010 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
1012 /* Ensure that restore_math() will restore */
1013 if (msr_diff
& MSR_FP
)
1014 current
->thread
.load_fp
= 1;
1015 #ifdef CONFIG_ALTIVEC
1016 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && msr_diff
& MSR_VEC
)
1017 current
->thread
.load_vec
= 1;
1021 regs
->msr
|= msr_diff
;
1025 #define tm_recheckpoint_new_task(new)
1026 #define __switch_to_tm(prev, new)
1027 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1029 static inline void save_sprs(struct thread_struct
*t
)
1031 #ifdef CONFIG_ALTIVEC
1032 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
1033 t
->vrsave
= mfspr(SPRN_VRSAVE
);
1035 #ifdef CONFIG_PPC_BOOK3S_64
1036 if (cpu_has_feature(CPU_FTR_DSCR
))
1037 t
->dscr
= mfspr(SPRN_DSCR
);
1039 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1040 t
->bescr
= mfspr(SPRN_BESCR
);
1041 t
->ebbhr
= mfspr(SPRN_EBBHR
);
1042 t
->ebbrr
= mfspr(SPRN_EBBRR
);
1044 t
->fscr
= mfspr(SPRN_FSCR
);
1047 * Note that the TAR is not available for use in the kernel.
1048 * (To provide this, the TAR should be backed up/restored on
1049 * exception entry/exit instead, and be in pt_regs. FIXME,
1050 * this should be in pt_regs anyway (for debug).)
1052 t
->tar
= mfspr(SPRN_TAR
);
1057 static inline void restore_sprs(struct thread_struct
*old_thread
,
1058 struct thread_struct
*new_thread
)
1060 #ifdef CONFIG_ALTIVEC
1061 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
1062 old_thread
->vrsave
!= new_thread
->vrsave
)
1063 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
1065 #ifdef CONFIG_PPC_BOOK3S_64
1066 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1067 u64 dscr
= get_paca()->dscr_default
;
1068 if (new_thread
->dscr_inherit
)
1069 dscr
= new_thread
->dscr
;
1071 if (old_thread
->dscr
!= dscr
)
1072 mtspr(SPRN_DSCR
, dscr
);
1075 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1076 if (old_thread
->bescr
!= new_thread
->bescr
)
1077 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1078 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1079 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1080 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1081 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1083 if (old_thread
->fscr
!= new_thread
->fscr
)
1084 mtspr(SPRN_FSCR
, new_thread
->fscr
);
1086 if (old_thread
->tar
!= new_thread
->tar
)
1087 mtspr(SPRN_TAR
, new_thread
->tar
);
1092 struct task_struct
*__switch_to(struct task_struct
*prev
,
1093 struct task_struct
*new)
1095 struct thread_struct
*new_thread
, *old_thread
;
1096 struct task_struct
*last
;
1097 #ifdef CONFIG_PPC_BOOK3S_64
1098 struct ppc64_tlb_batch
*batch
;
1101 new_thread
= &new->thread
;
1102 old_thread
= ¤t
->thread
;
1104 WARN_ON(!irqs_disabled());
1108 * Collect processor utilization data per process
1110 if (firmware_has_feature(FW_FEATURE_SPLPAR
)) {
1111 struct cpu_usage
*cu
= this_cpu_ptr(&cpu_usage_array
);
1112 long unsigned start_tb
, current_tb
;
1113 start_tb
= old_thread
->start_tb
;
1114 cu
->current_tb
= current_tb
= mfspr(SPRN_PURR
);
1115 old_thread
->accum_tb
+= (current_tb
- start_tb
);
1116 new_thread
->start_tb
= current_tb
;
1118 #endif /* CONFIG_PPC64 */
1120 #ifdef CONFIG_PPC_STD_MMU_64
1121 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1122 if (batch
->active
) {
1123 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1125 __flush_tlb_pending(batch
);
1128 #endif /* CONFIG_PPC_STD_MMU_64 */
1130 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1131 switch_booke_debug_regs(&new->thread
.debug
);
1134 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1137 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1138 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1139 __set_breakpoint(&new->thread
.hw_brk
);
1140 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1144 * We need to save SPRs before treclaim/trecheckpoint as these will
1145 * change a number of them.
1147 save_sprs(&prev
->thread
);
1149 /* Save FPU, Altivec, VSX and SPE state */
1152 __switch_to_tm(prev
, new);
1155 * We can't take a PMU exception inside _switch() since there is a
1156 * window where the kernel stack SLB and the kernel stack are out
1157 * of sync. Hard disable here.
1162 * Call restore_sprs() before calling _switch(). If we move it after
1163 * _switch() then we miss out on calling it for new tasks. The reason
1164 * for this is we manually create a stack frame for new tasks that
1165 * directly returns through ret_from_fork() or
1166 * ret_from_kernel_thread(). See copy_thread() for details.
1168 restore_sprs(old_thread
, new_thread
);
1170 last
= _switch(old_thread
, new_thread
);
1172 #ifdef CONFIG_PPC_STD_MMU_64
1173 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1174 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1175 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1179 if (current_thread_info()->task
->thread
.regs
)
1180 restore_math(current_thread_info()->task
->thread
.regs
);
1181 #endif /* CONFIG_PPC_STD_MMU_64 */
1186 static int instructions_to_print
= 16;
1188 static void show_instructions(struct pt_regs
*regs
)
1191 unsigned long pc
= regs
->nip
- (instructions_to_print
* 3 / 4 *
1194 printk("Instruction dump:");
1196 for (i
= 0; i
< instructions_to_print
; i
++) {
1202 #if !defined(CONFIG_BOOKE)
1203 /* If executing with the IMMU off, adjust pc rather
1204 * than print XXXXXXXX.
1206 if (!(regs
->msr
& MSR_IR
))
1207 pc
= (unsigned long)phys_to_virt(pc
);
1210 if (!__kernel_text_address(pc
) ||
1211 probe_kernel_address((unsigned int __user
*)pc
, instr
)) {
1212 pr_cont("XXXXXXXX ");
1214 if (regs
->nip
== pc
)
1215 pr_cont("<%08x> ", instr
);
1217 pr_cont("%08x ", instr
);
1231 static struct regbit msr_bits
[] = {
1232 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1254 #ifndef CONFIG_BOOKE
1261 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1265 for (; bits
->bit
; ++bits
)
1266 if (val
& bits
->bit
) {
1267 pr_cont("%s%s", s
, bits
->name
);
1272 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1273 static struct regbit msr_tm_bits
[] = {
1280 static void print_tm_bits(unsigned long val
)
1283 * This only prints something if at least one of the TM bit is set.
1284 * Inside the TM[], the output means:
1285 * E: Enabled (bit 32)
1286 * S: Suspended (bit 33)
1287 * T: Transactional (bit 34)
1289 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1291 print_bits(val
, msr_tm_bits
, "");
1296 static void print_tm_bits(unsigned long val
) {}
1299 static void print_msr_bits(unsigned long val
)
1302 print_bits(val
, msr_bits
, ",");
1308 #define REG "%016lx"
1309 #define REGS_PER_LINE 4
1310 #define LAST_VOLATILE 13
1313 #define REGS_PER_LINE 8
1314 #define LAST_VOLATILE 12
1317 void show_regs(struct pt_regs
* regs
)
1321 show_regs_print_info(KERN_DEFAULT
);
1323 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1324 regs
->nip
, regs
->link
, regs
->ctr
);
1325 printk("REGS: %p TRAP: %04lx %s (%s)\n",
1326 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1327 printk("MSR: "REG
" ", regs
->msr
);
1328 print_msr_bits(regs
->msr
);
1329 printk(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1331 if ((regs
->trap
!= 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1332 pr_cont("CFAR: "REG
" ", regs
->orig_gpr3
);
1333 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1334 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1335 pr_cont("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1337 pr_cont("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1340 pr_cont("SOFTE: %ld ", regs
->softe
);
1342 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1343 if (MSR_TM_ACTIVE(regs
->msr
))
1344 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1347 for (i
= 0; i
< 32; i
++) {
1348 if ((i
% REGS_PER_LINE
) == 0)
1349 pr_cont("\nGPR%02d: ", i
);
1350 pr_cont(REG
" ", regs
->gpr
[i
]);
1351 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1355 #ifdef CONFIG_KALLSYMS
1357 * Lookup NIP late so we have the best change of getting the
1358 * above info out without failing
1360 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1361 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1363 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1364 if (!user_mode(regs
))
1365 show_instructions(regs
);
1368 void flush_thread(void)
1370 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1371 flush_ptrace_hw_breakpoint(current
);
1372 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1373 set_debug_reg_defaults(¤t
->thread
);
1374 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1378 release_thread(struct task_struct
*t
)
1383 * this gets called so that we can store coprocessor state into memory and
1384 * copy the current task into the new thread.
1386 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1388 flush_all_to_thread(src
);
1390 * Flush TM state out so we can copy it. __switch_to_tm() does this
1391 * flush but it removes the checkpointed state from the current CPU and
1392 * transitions the CPU out of TM mode. Hence we need to call
1393 * tm_recheckpoint_new_task() (on the same task) to restore the
1394 * checkpointed state back and the TM mode.
1396 * Can't pass dst because it isn't ready. Doesn't matter, passing
1397 * dst is only important for __switch_to()
1399 __switch_to_tm(src
, src
);
1403 clear_task_ebb(dst
);
1408 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1410 #ifdef CONFIG_PPC_STD_MMU_64
1411 unsigned long sp_vsid
;
1412 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1414 if (radix_enabled())
1417 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1418 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1419 << SLB_VSID_SHIFT_1T
;
1421 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1423 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1424 p
->thread
.ksp_vsid
= sp_vsid
;
1433 * Copy architecture-specific thread state
1435 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1436 unsigned long kthread_arg
, struct task_struct
*p
)
1438 struct pt_regs
*childregs
, *kregs
;
1439 extern void ret_from_fork(void);
1440 extern void ret_from_kernel_thread(void);
1442 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1443 struct thread_info
*ti
= task_thread_info(p
);
1445 klp_init_thread_info(ti
);
1447 /* Copy registers */
1448 sp
-= sizeof(struct pt_regs
);
1449 childregs
= (struct pt_regs
*) sp
;
1450 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1452 memset(childregs
, 0, sizeof(struct pt_regs
));
1453 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1456 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1458 clear_tsk_thread_flag(p
, TIF_32BIT
);
1459 childregs
->softe
= 1;
1461 childregs
->gpr
[15] = kthread_arg
;
1462 p
->thread
.regs
= NULL
; /* no user register state */
1463 ti
->flags
|= _TIF_RESTOREALL
;
1464 f
= ret_from_kernel_thread
;
1467 struct pt_regs
*regs
= current_pt_regs();
1468 CHECK_FULL_REGS(regs
);
1471 childregs
->gpr
[1] = usp
;
1472 p
->thread
.regs
= childregs
;
1473 childregs
->gpr
[3] = 0; /* Result from fork() */
1474 if (clone_flags
& CLONE_SETTLS
) {
1476 if (!is_32bit_task())
1477 childregs
->gpr
[13] = childregs
->gpr
[6];
1480 childregs
->gpr
[2] = childregs
->gpr
[6];
1485 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1486 sp
-= STACK_FRAME_OVERHEAD
;
1489 * The way this works is that at some point in the future
1490 * some task will call _switch to switch to the new task.
1491 * That will pop off the stack frame created below and start
1492 * the new task running at ret_from_fork. The new task will
1493 * do some house keeping and then return from the fork or clone
1494 * system call, using the stack frame created above.
1496 ((unsigned long *)sp
)[0] = 0;
1497 sp
-= sizeof(struct pt_regs
);
1498 kregs
= (struct pt_regs
*) sp
;
1499 sp
-= STACK_FRAME_OVERHEAD
;
1502 p
->thread
.ksp_limit
= (unsigned long)task_stack_page(p
) +
1503 _ALIGN_UP(sizeof(struct thread_info
), 16);
1505 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1506 p
->thread
.ptrace_bps
[0] = NULL
;
1509 p
->thread
.fp_save_area
= NULL
;
1510 #ifdef CONFIG_ALTIVEC
1511 p
->thread
.vr_save_area
= NULL
;
1514 setup_ksp_vsid(p
, sp
);
1517 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1518 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1519 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1521 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1522 p
->thread
.ppr
= INIT_PPR
;
1524 kregs
->nip
= ppc_function_entry(f
);
1529 * Set up a thread for executing a new program
1531 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1534 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1538 * If we exec out of a kernel thread then thread.regs will not be
1541 if (!current
->thread
.regs
) {
1542 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1543 current
->thread
.regs
= regs
- 1;
1546 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1548 * Clear any transactional state, we're exec()ing. The cause is
1549 * not important as there will never be a recheckpoint so it's not
1552 if (MSR_TM_SUSPENDED(mfmsr()))
1553 tm_reclaim_current(0);
1556 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1564 * We have just cleared all the nonvolatile GPRs, so make
1565 * FULL_REGS(regs) return true. This is necessary to allow
1566 * ptrace to examine the thread immediately after exec.
1573 regs
->msr
= MSR_USER
;
1575 if (!is_32bit_task()) {
1576 unsigned long entry
;
1578 if (is_elf2_task()) {
1579 /* Look ma, no function descriptors! */
1584 * The latest iteration of the ABI requires that when
1585 * calling a function (at its global entry point),
1586 * the caller must ensure r12 holds the entry point
1587 * address (so that the function can quickly
1588 * establish addressability).
1590 regs
->gpr
[12] = start
;
1591 /* Make sure that's restored on entry to userspace. */
1592 set_thread_flag(TIF_RESTOREALL
);
1596 /* start is a relocated pointer to the function
1597 * descriptor for the elf _start routine. The first
1598 * entry in the function descriptor is the entry
1599 * address of _start and the second entry is the TOC
1600 * value we need to use.
1602 __get_user(entry
, (unsigned long __user
*)start
);
1603 __get_user(toc
, (unsigned long __user
*)start
+1);
1605 /* Check whether the e_entry function descriptor entries
1606 * need to be relocated before we can use them.
1608 if (load_addr
!= 0) {
1615 regs
->msr
= MSR_USER64
;
1619 regs
->msr
= MSR_USER32
;
1623 current
->thread
.used_vsr
= 0;
1625 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1626 current
->thread
.fp_save_area
= NULL
;
1627 #ifdef CONFIG_ALTIVEC
1628 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1629 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1630 current
->thread
.vr_save_area
= NULL
;
1631 current
->thread
.vrsave
= 0;
1632 current
->thread
.used_vr
= 0;
1633 #endif /* CONFIG_ALTIVEC */
1635 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1636 current
->thread
.acc
= 0;
1637 current
->thread
.spefscr
= 0;
1638 current
->thread
.used_spe
= 0;
1639 #endif /* CONFIG_SPE */
1640 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1641 current
->thread
.tm_tfhar
= 0;
1642 current
->thread
.tm_texasr
= 0;
1643 current
->thread
.tm_tfiar
= 0;
1644 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1646 EXPORT_SYMBOL(start_thread
);
1648 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1649 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1651 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1653 struct pt_regs
*regs
= tsk
->thread
.regs
;
1655 /* This is a bit hairy. If we are an SPE enabled processor
1656 * (have embedded fp) we store the IEEE exception enable flags in
1657 * fpexc_mode. fpexc_mode is also used for setting FP exception
1658 * mode (asyn, precise, disabled) for 'Classic' FP. */
1659 if (val
& PR_FP_EXC_SW_ENABLE
) {
1661 if (cpu_has_feature(CPU_FTR_SPE
)) {
1663 * When the sticky exception bits are set
1664 * directly by userspace, it must call prctl
1665 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1666 * in the existing prctl settings) or
1667 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1668 * the bits being set). <fenv.h> functions
1669 * saving and restoring the whole
1670 * floating-point environment need to do so
1671 * anyway to restore the prctl settings from
1672 * the saved environment.
1674 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1675 tsk
->thread
.fpexc_mode
= val
&
1676 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1686 /* on a CONFIG_SPE this does not hurt us. The bits that
1687 * __pack_fe01 use do not overlap with bits used for
1688 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1689 * on CONFIG_SPE implementations are reserved so writing to
1690 * them does not change anything */
1691 if (val
> PR_FP_EXC_PRECISE
)
1693 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1694 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1695 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1696 | tsk
->thread
.fpexc_mode
;
1700 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1704 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1706 if (cpu_has_feature(CPU_FTR_SPE
)) {
1708 * When the sticky exception bits are set
1709 * directly by userspace, it must call prctl
1710 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1711 * in the existing prctl settings) or
1712 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1713 * the bits being set). <fenv.h> functions
1714 * saving and restoring the whole
1715 * floating-point environment need to do so
1716 * anyway to restore the prctl settings from
1717 * the saved environment.
1719 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1720 val
= tsk
->thread
.fpexc_mode
;
1727 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1728 return put_user(val
, (unsigned int __user
*) adr
);
1731 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1733 struct pt_regs
*regs
= tsk
->thread
.regs
;
1735 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1736 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1742 if (val
== PR_ENDIAN_BIG
)
1743 regs
->msr
&= ~MSR_LE
;
1744 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1745 regs
->msr
|= MSR_LE
;
1752 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1754 struct pt_regs
*regs
= tsk
->thread
.regs
;
1757 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1758 !cpu_has_feature(CPU_FTR_REAL_LE
))
1764 if (regs
->msr
& MSR_LE
) {
1765 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1766 val
= PR_ENDIAN_LITTLE
;
1768 val
= PR_ENDIAN_PPC_LITTLE
;
1770 val
= PR_ENDIAN_BIG
;
1772 return put_user(val
, (unsigned int __user
*)adr
);
1775 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1777 tsk
->thread
.align_ctl
= val
;
1781 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1783 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1786 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1787 unsigned long nbytes
)
1789 unsigned long stack_page
;
1790 unsigned long cpu
= task_cpu(p
);
1793 * Avoid crashing if the stack has overflowed and corrupted
1794 * task_cpu(p), which is in the thread_info struct.
1796 if (cpu
< NR_CPUS
&& cpu_possible(cpu
)) {
1797 stack_page
= (unsigned long) hardirq_ctx
[cpu
];
1798 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1799 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1802 stack_page
= (unsigned long) softirq_ctx
[cpu
];
1803 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1804 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1810 int validate_sp(unsigned long sp
, struct task_struct
*p
,
1811 unsigned long nbytes
)
1813 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
1815 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1816 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1819 return valid_irq_stack(sp
, p
, nbytes
);
1822 EXPORT_SYMBOL(validate_sp
);
1824 unsigned long get_wchan(struct task_struct
*p
)
1826 unsigned long ip
, sp
;
1829 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
1833 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1837 sp
= *(unsigned long *)sp
;
1838 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1841 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
1842 if (!in_sched_functions(ip
))
1845 } while (count
++ < 16);
1849 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
1851 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
1853 unsigned long sp
, ip
, lr
, newsp
;
1856 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1857 int curr_frame
= current
->curr_ret_stack
;
1858 extern void return_to_handler(void);
1859 unsigned long rth
= (unsigned long)return_to_handler
;
1862 sp
= (unsigned long) stack
;
1867 sp
= current_stack_pointer();
1869 sp
= tsk
->thread
.ksp
;
1873 printk("Call Trace:\n");
1875 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
1878 stack
= (unsigned long *) sp
;
1880 ip
= stack
[STACK_FRAME_LR_SAVE
];
1881 if (!firstframe
|| ip
!= lr
) {
1882 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
1883 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1884 if ((ip
== rth
) && curr_frame
>= 0) {
1886 (void *)current
->ret_stack
[curr_frame
].ret
);
1891 pr_cont(" (unreliable)");
1897 * See if this is an exception frame.
1898 * We look for the "regshere" marker in the current frame.
1900 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
1901 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
1902 struct pt_regs
*regs
= (struct pt_regs
*)
1903 (sp
+ STACK_FRAME_OVERHEAD
);
1905 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
1906 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
1911 } while (count
++ < kstack_depth_to_print
);
1915 /* Called with hard IRQs off */
1916 void notrace
__ppc64_runlatch_on(void)
1918 struct thread_info
*ti
= current_thread_info();
1921 ctrl
= mfspr(SPRN_CTRLF
);
1922 ctrl
|= CTRL_RUNLATCH
;
1923 mtspr(SPRN_CTRLT
, ctrl
);
1925 ti
->local_flags
|= _TLF_RUNLATCH
;
1928 /* Called with hard IRQs off */
1929 void notrace
__ppc64_runlatch_off(void)
1931 struct thread_info
*ti
= current_thread_info();
1934 ti
->local_flags
&= ~_TLF_RUNLATCH
;
1936 ctrl
= mfspr(SPRN_CTRLF
);
1937 ctrl
&= ~CTRL_RUNLATCH
;
1938 mtspr(SPRN_CTRLT
, ctrl
);
1940 #endif /* CONFIG_PPC64 */
1942 unsigned long arch_align_stack(unsigned long sp
)
1944 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
1945 sp
-= get_random_int() & ~PAGE_MASK
;
1949 static inline unsigned long brk_rnd(void)
1951 unsigned long rnd
= 0;
1953 /* 8MB for 32bit, 1GB for 64bit */
1954 if (is_32bit_task())
1955 rnd
= (get_random_long() % (1UL<<(23-PAGE_SHIFT
)));
1957 rnd
= (get_random_long() % (1UL<<(30-PAGE_SHIFT
)));
1959 return rnd
<< PAGE_SHIFT
;
1962 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
1964 unsigned long base
= mm
->brk
;
1967 #ifdef CONFIG_PPC_STD_MMU_64
1969 * If we are using 1TB segments and we are allowed to randomise
1970 * the heap, we can put it above 1TB so it is backed by a 1TB
1971 * segment. Otherwise the heap will be in the bottom 1TB
1972 * which always uses 256MB segments and this may result in a
1973 * performance penalty. We don't need to worry about radix. For
1974 * radix, mmu_highuser_ssize remains unchanged from 256MB.
1976 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
1977 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
1980 ret
= PAGE_ALIGN(base
+ brk_rnd());