2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/sched/debug.h>
20 #include <linux/sched/task.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/kernel.h>
24 #include <linux/smp.h>
25 #include <linux/stddef.h>
26 #include <linux/unistd.h>
27 #include <linux/ptrace.h>
28 #include <linux/slab.h>
29 #include <linux/user.h>
30 #include <linux/elf.h>
31 #include <linux/prctl.h>
32 #include <linux/init_task.h>
33 #include <linux/export.h>
34 #include <linux/kallsyms.h>
35 #include <linux/mqueue.h>
36 #include <linux/hardirq.h>
37 #include <linux/utsname.h>
38 #include <linux/ftrace.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/personality.h>
41 #include <linux/random.h>
42 #include <linux/hw_breakpoint.h>
43 #include <linux/uaccess.h>
44 #include <linux/elf-randomize.h>
45 #include <linux/pkeys.h>
46 #include <linux/seq_buf.h>
48 #include <asm/pgtable.h>
50 #include <asm/processor.h>
53 #include <asm/machdep.h>
55 #include <asm/runlatch.h>
56 #include <asm/syscalls.h>
57 #include <asm/switch_to.h>
59 #include <asm/debug.h>
61 #include <asm/firmware.h>
62 #include <asm/hw_irq.h>
64 #include <asm/code-patching.h>
66 #include <asm/livepatch.h>
67 #include <asm/cpu_has_feature.h>
68 #include <asm/asm-prototypes.h>
69 #include <asm/stacktrace.h>
70 #include <asm/hw_breakpoint.h>
72 #include <linux/kprobes.h>
73 #include <linux/kdebug.h>
75 /* Transactional Memory debug */
77 #define TM_DEBUG(x...) printk(KERN_INFO x)
79 #define TM_DEBUG(x...) do { } while(0)
82 extern unsigned long _get_SP(void);
84 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
86 * Are we running in "Suspend disabled" mode? If so we have to block any
87 * sigreturn that would get us into suspended state, and we also warn in some
88 * other paths that we should never reach with suspend disabled.
90 bool tm_suspend_disabled __ro_after_init
= false;
92 static void check_if_tm_restore_required(struct task_struct
*tsk
)
95 * If we are saving the current thread's registers, and the
96 * thread is in a transactional state, set the TIF_RESTORE_TM
97 * bit so that we know to restore the registers before
98 * returning to userspace.
100 if (tsk
== current
&& tsk
->thread
.regs
&&
101 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
102 !test_thread_flag(TIF_RESTORE_TM
)) {
103 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
104 set_thread_flag(TIF_RESTORE_TM
);
108 static bool tm_active_with_fp(struct task_struct
*tsk
)
110 return MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
111 (tsk
->thread
.ckpt_regs
.msr
& MSR_FP
);
114 static bool tm_active_with_altivec(struct task_struct
*tsk
)
116 return MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
117 (tsk
->thread
.ckpt_regs
.msr
& MSR_VEC
);
120 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
121 static inline bool tm_active_with_fp(struct task_struct
*tsk
) { return false; }
122 static inline bool tm_active_with_altivec(struct task_struct
*tsk
) { return false; }
123 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
125 bool strict_msr_control
;
126 EXPORT_SYMBOL(strict_msr_control
);
128 static int __init
enable_strict_msr_control(char *str
)
130 strict_msr_control
= true;
131 pr_info("Enabling strict facility control\n");
135 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
137 unsigned long msr_check_and_set(unsigned long bits
)
139 unsigned long oldmsr
= mfmsr();
140 unsigned long newmsr
;
142 newmsr
= oldmsr
| bits
;
145 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
149 if (oldmsr
!= newmsr
)
154 EXPORT_SYMBOL_GPL(msr_check_and_set
);
156 void __msr_check_and_clear(unsigned long bits
)
158 unsigned long oldmsr
= mfmsr();
159 unsigned long newmsr
;
161 newmsr
= oldmsr
& ~bits
;
164 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
168 if (oldmsr
!= newmsr
)
171 EXPORT_SYMBOL(__msr_check_and_clear
);
173 #ifdef CONFIG_PPC_FPU
174 static void __giveup_fpu(struct task_struct
*tsk
)
179 msr
= tsk
->thread
.regs
->msr
;
180 msr
&= ~(MSR_FP
|MSR_FE0
|MSR_FE1
);
182 if (cpu_has_feature(CPU_FTR_VSX
))
185 tsk
->thread
.regs
->msr
= msr
;
188 void giveup_fpu(struct task_struct
*tsk
)
190 check_if_tm_restore_required(tsk
);
192 msr_check_and_set(MSR_FP
);
194 msr_check_and_clear(MSR_FP
);
196 EXPORT_SYMBOL(giveup_fpu
);
199 * Make sure the floating-point register state in the
200 * the thread_struct is up to date for task tsk.
202 void flush_fp_to_thread(struct task_struct
*tsk
)
204 if (tsk
->thread
.regs
) {
206 * We need to disable preemption here because if we didn't,
207 * another process could get scheduled after the regs->msr
208 * test but before we have finished saving the FP registers
209 * to the thread_struct. That process could take over the
210 * FPU, and then when we get scheduled again we would store
211 * bogus values for the remaining FP registers.
214 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
216 * This should only ever be called for current or
217 * for a stopped child process. Since we save away
218 * the FP register state on context switch,
219 * there is something wrong if a stopped child appears
220 * to still have its FP state in the CPU registers.
222 BUG_ON(tsk
!= current
);
228 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
230 void enable_kernel_fp(void)
232 unsigned long cpumsr
;
234 WARN_ON(preemptible());
236 cpumsr
= msr_check_and_set(MSR_FP
);
238 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
239 check_if_tm_restore_required(current
);
241 * If a thread has already been reclaimed then the
242 * checkpointed registers are on the CPU but have definitely
243 * been saved by the reclaim code. Don't need to and *cannot*
244 * giveup as this would save to the 'live' structure not the
245 * checkpointed structure.
247 if (!MSR_TM_ACTIVE(cpumsr
) &&
248 MSR_TM_ACTIVE(current
->thread
.regs
->msr
))
250 __giveup_fpu(current
);
253 EXPORT_SYMBOL(enable_kernel_fp
);
255 static int restore_fp(struct task_struct
*tsk
)
257 if (tsk
->thread
.load_fp
|| tm_active_with_fp(tsk
)) {
258 load_fp_state(¤t
->thread
.fp_state
);
259 current
->thread
.load_fp
++;
265 static int restore_fp(struct task_struct
*tsk
) { return 0; }
266 #endif /* CONFIG_PPC_FPU */
268 #ifdef CONFIG_ALTIVEC
269 #define loadvec(thr) ((thr).load_vec)
271 static void __giveup_altivec(struct task_struct
*tsk
)
276 msr
= tsk
->thread
.regs
->msr
;
279 if (cpu_has_feature(CPU_FTR_VSX
))
282 tsk
->thread
.regs
->msr
= msr
;
285 void giveup_altivec(struct task_struct
*tsk
)
287 check_if_tm_restore_required(tsk
);
289 msr_check_and_set(MSR_VEC
);
290 __giveup_altivec(tsk
);
291 msr_check_and_clear(MSR_VEC
);
293 EXPORT_SYMBOL(giveup_altivec
);
295 void enable_kernel_altivec(void)
297 unsigned long cpumsr
;
299 WARN_ON(preemptible());
301 cpumsr
= msr_check_and_set(MSR_VEC
);
303 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
304 check_if_tm_restore_required(current
);
306 * If a thread has already been reclaimed then the
307 * checkpointed registers are on the CPU but have definitely
308 * been saved by the reclaim code. Don't need to and *cannot*
309 * giveup as this would save to the 'live' structure not the
310 * checkpointed structure.
312 if (!MSR_TM_ACTIVE(cpumsr
) &&
313 MSR_TM_ACTIVE(current
->thread
.regs
->msr
))
315 __giveup_altivec(current
);
318 EXPORT_SYMBOL(enable_kernel_altivec
);
321 * Make sure the VMX/Altivec register state in the
322 * the thread_struct is up to date for task tsk.
324 void flush_altivec_to_thread(struct task_struct
*tsk
)
326 if (tsk
->thread
.regs
) {
328 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
329 BUG_ON(tsk
!= current
);
335 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
337 static int restore_altivec(struct task_struct
*tsk
)
339 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
340 (tsk
->thread
.load_vec
|| tm_active_with_altivec(tsk
))) {
341 load_vr_state(&tsk
->thread
.vr_state
);
342 tsk
->thread
.used_vr
= 1;
343 tsk
->thread
.load_vec
++;
350 #define loadvec(thr) 0
351 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
352 #endif /* CONFIG_ALTIVEC */
355 static void __giveup_vsx(struct task_struct
*tsk
)
357 unsigned long msr
= tsk
->thread
.regs
->msr
;
360 * We should never be ssetting MSR_VSX without also setting
363 WARN_ON((msr
& MSR_VSX
) && !((msr
& MSR_FP
) && (msr
& MSR_VEC
)));
365 /* __giveup_fpu will clear MSR_VSX */
369 __giveup_altivec(tsk
);
372 static void giveup_vsx(struct task_struct
*tsk
)
374 check_if_tm_restore_required(tsk
);
376 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
378 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
381 void enable_kernel_vsx(void)
383 unsigned long cpumsr
;
385 WARN_ON(preemptible());
387 cpumsr
= msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
389 if (current
->thread
.regs
&&
390 (current
->thread
.regs
->msr
& (MSR_VSX
|MSR_VEC
|MSR_FP
))) {
391 check_if_tm_restore_required(current
);
393 * If a thread has already been reclaimed then the
394 * checkpointed registers are on the CPU but have definitely
395 * been saved by the reclaim code. Don't need to and *cannot*
396 * giveup as this would save to the 'live' structure not the
397 * checkpointed structure.
399 if (!MSR_TM_ACTIVE(cpumsr
) &&
400 MSR_TM_ACTIVE(current
->thread
.regs
->msr
))
402 __giveup_vsx(current
);
405 EXPORT_SYMBOL(enable_kernel_vsx
);
407 void flush_vsx_to_thread(struct task_struct
*tsk
)
409 if (tsk
->thread
.regs
) {
411 if (tsk
->thread
.regs
->msr
& (MSR_VSX
|MSR_VEC
|MSR_FP
)) {
412 BUG_ON(tsk
!= current
);
418 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
420 static int restore_vsx(struct task_struct
*tsk
)
422 if (cpu_has_feature(CPU_FTR_VSX
)) {
423 tsk
->thread
.used_vsr
= 1;
430 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
431 #endif /* CONFIG_VSX */
434 void giveup_spe(struct task_struct
*tsk
)
436 check_if_tm_restore_required(tsk
);
438 msr_check_and_set(MSR_SPE
);
440 msr_check_and_clear(MSR_SPE
);
442 EXPORT_SYMBOL(giveup_spe
);
444 void enable_kernel_spe(void)
446 WARN_ON(preemptible());
448 msr_check_and_set(MSR_SPE
);
450 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
451 check_if_tm_restore_required(current
);
452 __giveup_spe(current
);
455 EXPORT_SYMBOL(enable_kernel_spe
);
457 void flush_spe_to_thread(struct task_struct
*tsk
)
459 if (tsk
->thread
.regs
) {
461 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
462 BUG_ON(tsk
!= current
);
463 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
469 #endif /* CONFIG_SPE */
471 static unsigned long msr_all_available
;
473 static int __init
init_msr_all_available(void)
475 #ifdef CONFIG_PPC_FPU
476 msr_all_available
|= MSR_FP
;
478 #ifdef CONFIG_ALTIVEC
479 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
480 msr_all_available
|= MSR_VEC
;
483 if (cpu_has_feature(CPU_FTR_VSX
))
484 msr_all_available
|= MSR_VSX
;
487 if (cpu_has_feature(CPU_FTR_SPE
))
488 msr_all_available
|= MSR_SPE
;
493 early_initcall(init_msr_all_available
);
495 void giveup_all(struct task_struct
*tsk
)
497 unsigned long usermsr
;
499 if (!tsk
->thread
.regs
)
502 usermsr
= tsk
->thread
.regs
->msr
;
504 if ((usermsr
& msr_all_available
) == 0)
507 msr_check_and_set(msr_all_available
);
508 check_if_tm_restore_required(tsk
);
510 WARN_ON((usermsr
& MSR_VSX
) && !((usermsr
& MSR_FP
) && (usermsr
& MSR_VEC
)));
512 #ifdef CONFIG_PPC_FPU
513 if (usermsr
& MSR_FP
)
516 #ifdef CONFIG_ALTIVEC
517 if (usermsr
& MSR_VEC
)
518 __giveup_altivec(tsk
);
521 if (usermsr
& MSR_SPE
)
525 msr_check_and_clear(msr_all_available
);
527 EXPORT_SYMBOL(giveup_all
);
529 void restore_math(struct pt_regs
*regs
)
533 if (!MSR_TM_ACTIVE(regs
->msr
) &&
534 !current
->thread
.load_fp
&& !loadvec(current
->thread
))
538 msr_check_and_set(msr_all_available
);
541 * Only reload if the bit is not set in the user MSR, the bit BEING set
542 * indicates that the registers are hot
544 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
545 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
547 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
550 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
551 restore_vsx(current
)) {
555 msr_check_and_clear(msr_all_available
);
560 static void save_all(struct task_struct
*tsk
)
562 unsigned long usermsr
;
564 if (!tsk
->thread
.regs
)
567 usermsr
= tsk
->thread
.regs
->msr
;
569 if ((usermsr
& msr_all_available
) == 0)
572 msr_check_and_set(msr_all_available
);
574 WARN_ON((usermsr
& MSR_VSX
) && !((usermsr
& MSR_FP
) && (usermsr
& MSR_VEC
)));
576 if (usermsr
& MSR_FP
)
579 if (usermsr
& MSR_VEC
)
582 if (usermsr
& MSR_SPE
)
585 msr_check_and_clear(msr_all_available
);
586 thread_pkey_regs_save(&tsk
->thread
);
589 void flush_all_to_thread(struct task_struct
*tsk
)
591 if (tsk
->thread
.regs
) {
593 BUG_ON(tsk
!= current
);
595 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
596 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
603 EXPORT_SYMBOL(flush_all_to_thread
);
605 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
606 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
607 unsigned long error_code
, int breakpt
)
609 current
->thread
.trap_nr
= TRAP_HWBKPT
;
610 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
611 11, SIGSEGV
) == NOTIFY_STOP
)
614 /* Deliver the signal to userspace */
615 force_sig_ptrace_errno_trap(breakpt
, /* breakpoint or watchpoint id */
616 (void __user
*)address
);
618 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
619 void do_break (struct pt_regs
*regs
, unsigned long address
,
620 unsigned long error_code
)
622 current
->thread
.trap_nr
= TRAP_HWBKPT
;
623 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
624 11, SIGSEGV
) == NOTIFY_STOP
)
627 if (debugger_break_match(regs
))
630 /* Clear the breakpoint */
631 hw_breakpoint_disable();
633 /* Deliver the signal to userspace */
634 force_sig_fault(SIGTRAP
, TRAP_HWBKPT
, (void __user
*)address
, current
);
636 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
638 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
640 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
642 * Set the debug registers back to their default "safe" values.
644 static void set_debug_reg_defaults(struct thread_struct
*thread
)
646 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
647 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
648 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
650 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
651 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
652 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
654 thread
->debug
.dbcr0
= 0;
657 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
659 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
660 DBCR1_IAC3US
| DBCR1_IAC4US
;
662 * Force Data Address Compare User/Supervisor bits to be User-only
663 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
665 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
667 thread
->debug
.dbcr1
= 0;
671 static void prime_debug_regs(struct debug_reg
*debug
)
674 * We could have inherited MSR_DE from userspace, since
675 * it doesn't get cleared on exception entry. Make sure
676 * MSR_DE is clear before we enable any debug events.
678 mtmsr(mfmsr() & ~MSR_DE
);
680 mtspr(SPRN_IAC1
, debug
->iac1
);
681 mtspr(SPRN_IAC2
, debug
->iac2
);
682 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
683 mtspr(SPRN_IAC3
, debug
->iac3
);
684 mtspr(SPRN_IAC4
, debug
->iac4
);
686 mtspr(SPRN_DAC1
, debug
->dac1
);
687 mtspr(SPRN_DAC2
, debug
->dac2
);
688 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
689 mtspr(SPRN_DVC1
, debug
->dvc1
);
690 mtspr(SPRN_DVC2
, debug
->dvc2
);
692 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
693 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
695 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
699 * Unless neither the old or new thread are making use of the
700 * debug registers, set the debug registers from the values
701 * stored in the new thread.
703 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
705 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
706 || (new_debug
->dbcr0
& DBCR0_IDM
))
707 prime_debug_regs(new_debug
);
709 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
710 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
711 #ifndef CONFIG_HAVE_HW_BREAKPOINT
712 static void set_breakpoint(struct arch_hw_breakpoint
*brk
)
715 __set_breakpoint(brk
);
719 static void set_debug_reg_defaults(struct thread_struct
*thread
)
721 thread
->hw_brk
.address
= 0;
722 thread
->hw_brk
.type
= 0;
723 if (ppc_breakpoint_available())
724 set_breakpoint(&thread
->hw_brk
);
726 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
727 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
729 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
730 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
732 mtspr(SPRN_DAC1
, dabr
);
733 #ifdef CONFIG_PPC_47x
738 #elif defined(CONFIG_PPC_BOOK3S)
739 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
741 mtspr(SPRN_DABR
, dabr
);
742 if (cpu_has_feature(CPU_FTR_DABRX
))
743 mtspr(SPRN_DABRX
, dabrx
);
746 #elif defined(CONFIG_PPC_8xx)
747 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
749 unsigned long addr
= dabr
& ~HW_BRK_TYPE_DABR
;
750 unsigned long lctrl1
= 0x90000000; /* compare type: equal on E & F */
751 unsigned long lctrl2
= 0x8e000002; /* watchpoint 1 on cmp E | F */
753 if ((dabr
& HW_BRK_TYPE_RDWR
) == HW_BRK_TYPE_READ
)
755 else if ((dabr
& HW_BRK_TYPE_RDWR
) == HW_BRK_TYPE_WRITE
)
757 else if ((dabr
& HW_BRK_TYPE_RDWR
) == 0)
760 mtspr(SPRN_LCTRL2
, 0);
761 mtspr(SPRN_CMPE
, addr
);
762 mtspr(SPRN_CMPF
, addr
+ 4);
763 mtspr(SPRN_LCTRL1
, lctrl1
);
764 mtspr(SPRN_LCTRL2
, lctrl2
);
769 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
775 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
777 unsigned long dabr
, dabrx
;
779 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
780 dabrx
= ((brk
->type
>> 3) & 0x7);
783 return ppc_md
.set_dabr(dabr
, dabrx
);
785 return __set_dabr(dabr
, dabrx
);
788 int set_dawr(struct arch_hw_breakpoint
*brk
)
790 unsigned long dawr
, dawrx
, mrd
;
794 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
795 << (63 - 58); //* read/write bits */
796 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
797 << (63 - 59); //* translate */
798 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
799 >> 3; //* PRIM bits */
800 /* dawr length is stored in field MDR bits 48:53. Matches range in
801 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
803 brk->len is in bytes.
804 This aligns up to double word size, shifts and does the bias.
806 mrd
= ((brk
->len
+ 7) >> 3) - 1;
807 dawrx
|= (mrd
& 0x3f) << (63 - 53);
810 return ppc_md
.set_dawr(dawr
, dawrx
);
811 mtspr(SPRN_DAWR
, dawr
);
812 mtspr(SPRN_DAWRX
, dawrx
);
816 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
818 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
823 else if (!cpu_has_feature(CPU_FTR_ARCH_207S
))
827 // Shouldn't happen due to higher level checks
831 /* Check if we have DAWR or DABR hardware */
832 bool ppc_breakpoint_available(void)
835 return true; /* POWER8 DAWR or POWER9 forced DAWR */
836 if (cpu_has_feature(CPU_FTR_ARCH_207S
))
837 return false; /* POWER9 with DAWR disabled */
838 /* DABR: Everything but POWER8 and POWER9 */
841 EXPORT_SYMBOL_GPL(ppc_breakpoint_available
);
843 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
844 struct arch_hw_breakpoint
*b
)
846 if (a
->address
!= b
->address
)
848 if (a
->type
!= b
->type
)
850 if (a
->len
!= b
->len
)
855 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
857 static inline bool tm_enabled(struct task_struct
*tsk
)
859 return tsk
&& tsk
->thread
.regs
&& (tsk
->thread
.regs
->msr
& MSR_TM
);
862 static void tm_reclaim_thread(struct thread_struct
*thr
, uint8_t cause
)
865 * Use the current MSR TM suspended bit to track if we have
866 * checkpointed state outstanding.
867 * On signal delivery, we'd normally reclaim the checkpointed
868 * state to obtain stack pointer (see:get_tm_stackpointer()).
869 * This will then directly return to userspace without going
870 * through __switch_to(). However, if the stack frame is bad,
871 * we need to exit this thread which calls __switch_to() which
872 * will again attempt to reclaim the already saved tm state.
873 * Hence we need to check that we've not already reclaimed
875 * We do this using the current MSR, rather tracking it in
876 * some specific thread_struct bit, as it has the additional
877 * benefit of checking for a potential TM bad thing exception.
879 if (!MSR_TM_SUSPENDED(mfmsr()))
882 giveup_all(container_of(thr
, struct task_struct
, thread
));
884 tm_reclaim(thr
, cause
);
887 * If we are in a transaction and FP is off then we can't have
888 * used FP inside that transaction. Hence the checkpointed
889 * state is the same as the live state. We need to copy the
890 * live state to the checkpointed state so that when the
891 * transaction is restored, the checkpointed state is correct
892 * and the aborted transaction sees the correct state. We use
893 * ckpt_regs.msr here as that's what tm_reclaim will use to
894 * determine if it's going to write the checkpointed state or
895 * not. So either this will write the checkpointed registers,
896 * or reclaim will. Similarly for VMX.
898 if ((thr
->ckpt_regs
.msr
& MSR_FP
) == 0)
899 memcpy(&thr
->ckfp_state
, &thr
->fp_state
,
900 sizeof(struct thread_fp_state
));
901 if ((thr
->ckpt_regs
.msr
& MSR_VEC
) == 0)
902 memcpy(&thr
->ckvr_state
, &thr
->vr_state
,
903 sizeof(struct thread_vr_state
));
906 void tm_reclaim_current(uint8_t cause
)
909 tm_reclaim_thread(¤t
->thread
, cause
);
912 static inline void tm_reclaim_task(struct task_struct
*tsk
)
914 /* We have to work out if we're switching from/to a task that's in the
915 * middle of a transaction.
917 * In switching we need to maintain a 2nd register state as
918 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
919 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
922 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
924 struct thread_struct
*thr
= &tsk
->thread
;
929 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
930 goto out_and_saveregs
;
932 WARN_ON(tm_suspend_disabled
);
934 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
935 "ccr=%lx, msr=%lx, trap=%lx)\n",
936 tsk
->pid
, thr
->regs
->nip
,
937 thr
->regs
->ccr
, thr
->regs
->msr
,
940 tm_reclaim_thread(thr
, TM_CAUSE_RESCHED
);
942 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
946 /* Always save the regs here, even if a transaction's not active.
947 * This context-switches a thread's TM info SPRs. We do it here to
948 * be consistent with the restore path (in recheckpoint) which
949 * cannot happen later in _switch().
954 extern void __tm_recheckpoint(struct thread_struct
*thread
);
956 void tm_recheckpoint(struct thread_struct
*thread
)
960 if (!(thread
->regs
->msr
& MSR_TM
))
963 /* We really can't be interrupted here as the TEXASR registers can't
964 * change and later in the trecheckpoint code, we have a userspace R1.
965 * So let's hard disable over this region.
967 local_irq_save(flags
);
970 /* The TM SPRs are restored here, so that TEXASR.FS can be set
971 * before the trecheckpoint and no explosion occurs.
973 tm_restore_sprs(thread
);
975 __tm_recheckpoint(thread
);
977 local_irq_restore(flags
);
980 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
982 if (!cpu_has_feature(CPU_FTR_TM
))
985 /* Recheckpoint the registers of the thread we're about to switch to.
987 * If the task was using FP, we non-lazily reload both the original and
988 * the speculative FP register states. This is because the kernel
989 * doesn't see if/when a TM rollback occurs, so if we take an FP
990 * unavailable later, we are unable to determine which set of FP regs
991 * need to be restored.
993 if (!tm_enabled(new))
996 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
997 tm_restore_sprs(&new->thread
);
1000 /* Recheckpoint to restore original checkpointed register state. */
1001 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1002 new->pid
, new->thread
.regs
->msr
);
1004 tm_recheckpoint(&new->thread
);
1007 * The checkpointed state has been restored but the live state has
1008 * not, ensure all the math functionality is turned off to trigger
1009 * restore_math() to reload.
1011 new->thread
.regs
->msr
&= ~(MSR_FP
| MSR_VEC
| MSR_VSX
);
1013 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1014 "(kernel msr 0x%lx)\n",
1018 static inline void __switch_to_tm(struct task_struct
*prev
,
1019 struct task_struct
*new)
1021 if (cpu_has_feature(CPU_FTR_TM
)) {
1022 if (tm_enabled(prev
) || tm_enabled(new))
1025 if (tm_enabled(prev
)) {
1026 prev
->thread
.load_tm
++;
1027 tm_reclaim_task(prev
);
1028 if (!MSR_TM_ACTIVE(prev
->thread
.regs
->msr
) && prev
->thread
.load_tm
== 0)
1029 prev
->thread
.regs
->msr
&= ~MSR_TM
;
1032 tm_recheckpoint_new_task(new);
1037 * This is called if we are on the way out to userspace and the
1038 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1039 * FP and/or vector state and does so if necessary.
1040 * If userspace is inside a transaction (whether active or
1041 * suspended) and FP/VMX/VSX instructions have ever been enabled
1042 * inside that transaction, then we have to keep them enabled
1043 * and keep the FP/VMX/VSX state loaded while ever the transaction
1044 * continues. The reason is that if we didn't, and subsequently
1045 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1046 * we don't know whether it's the same transaction, and thus we
1047 * don't know which of the checkpointed state and the transactional
1050 void restore_tm_state(struct pt_regs
*regs
)
1052 unsigned long msr_diff
;
1055 * This is the only moment we should clear TIF_RESTORE_TM as
1056 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1057 * again, anything else could lead to an incorrect ckpt_msr being
1058 * saved and therefore incorrect signal contexts.
1060 clear_thread_flag(TIF_RESTORE_TM
);
1061 if (!MSR_TM_ACTIVE(regs
->msr
))
1064 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
1065 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
1067 /* Ensure that restore_math() will restore */
1068 if (msr_diff
& MSR_FP
)
1069 current
->thread
.load_fp
= 1;
1070 #ifdef CONFIG_ALTIVEC
1071 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && msr_diff
& MSR_VEC
)
1072 current
->thread
.load_vec
= 1;
1076 regs
->msr
|= msr_diff
;
1080 #define tm_recheckpoint_new_task(new)
1081 #define __switch_to_tm(prev, new)
1082 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1084 static inline void save_sprs(struct thread_struct
*t
)
1086 #ifdef CONFIG_ALTIVEC
1087 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
1088 t
->vrsave
= mfspr(SPRN_VRSAVE
);
1090 #ifdef CONFIG_PPC_BOOK3S_64
1091 if (cpu_has_feature(CPU_FTR_DSCR
))
1092 t
->dscr
= mfspr(SPRN_DSCR
);
1094 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1095 t
->bescr
= mfspr(SPRN_BESCR
);
1096 t
->ebbhr
= mfspr(SPRN_EBBHR
);
1097 t
->ebbrr
= mfspr(SPRN_EBBRR
);
1099 t
->fscr
= mfspr(SPRN_FSCR
);
1102 * Note that the TAR is not available for use in the kernel.
1103 * (To provide this, the TAR should be backed up/restored on
1104 * exception entry/exit instead, and be in pt_regs. FIXME,
1105 * this should be in pt_regs anyway (for debug).)
1107 t
->tar
= mfspr(SPRN_TAR
);
1111 thread_pkey_regs_save(t
);
1114 static inline void restore_sprs(struct thread_struct
*old_thread
,
1115 struct thread_struct
*new_thread
)
1117 #ifdef CONFIG_ALTIVEC
1118 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
1119 old_thread
->vrsave
!= new_thread
->vrsave
)
1120 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
1122 #ifdef CONFIG_PPC_BOOK3S_64
1123 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1124 u64 dscr
= get_paca()->dscr_default
;
1125 if (new_thread
->dscr_inherit
)
1126 dscr
= new_thread
->dscr
;
1128 if (old_thread
->dscr
!= dscr
)
1129 mtspr(SPRN_DSCR
, dscr
);
1132 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1133 if (old_thread
->bescr
!= new_thread
->bescr
)
1134 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1135 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1136 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1137 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1138 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1140 if (old_thread
->fscr
!= new_thread
->fscr
)
1141 mtspr(SPRN_FSCR
, new_thread
->fscr
);
1143 if (old_thread
->tar
!= new_thread
->tar
)
1144 mtspr(SPRN_TAR
, new_thread
->tar
);
1147 if (cpu_has_feature(CPU_FTR_P9_TIDR
) &&
1148 old_thread
->tidr
!= new_thread
->tidr
)
1149 mtspr(SPRN_TIDR
, new_thread
->tidr
);
1152 thread_pkey_regs_restore(new_thread
, old_thread
);
1155 #ifdef CONFIG_PPC_BOOK3S_64
1157 static const u8 dummy_copy_buffer
[CP_SIZE
] __attribute__((aligned(CP_SIZE
)));
1160 struct task_struct
*__switch_to(struct task_struct
*prev
,
1161 struct task_struct
*new)
1163 struct thread_struct
*new_thread
, *old_thread
;
1164 struct task_struct
*last
;
1165 #ifdef CONFIG_PPC_BOOK3S_64
1166 struct ppc64_tlb_batch
*batch
;
1169 new_thread
= &new->thread
;
1170 old_thread
= ¤t
->thread
;
1172 WARN_ON(!irqs_disabled());
1174 #ifdef CONFIG_PPC_BOOK3S_64
1175 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1176 if (batch
->active
) {
1177 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1179 __flush_tlb_pending(batch
);
1182 #endif /* CONFIG_PPC_BOOK3S_64 */
1184 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1185 switch_booke_debug_regs(&new->thread
.debug
);
1188 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1191 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1192 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1193 __set_breakpoint(&new->thread
.hw_brk
);
1194 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1198 * We need to save SPRs before treclaim/trecheckpoint as these will
1199 * change a number of them.
1201 save_sprs(&prev
->thread
);
1203 /* Save FPU, Altivec, VSX and SPE state */
1206 __switch_to_tm(prev
, new);
1208 if (!radix_enabled()) {
1210 * We can't take a PMU exception inside _switch() since there
1211 * is a window where the kernel stack SLB and the kernel stack
1212 * are out of sync. Hard disable here.
1218 * Call restore_sprs() before calling _switch(). If we move it after
1219 * _switch() then we miss out on calling it for new tasks. The reason
1220 * for this is we manually create a stack frame for new tasks that
1221 * directly returns through ret_from_fork() or
1222 * ret_from_kernel_thread(). See copy_thread() for details.
1224 restore_sprs(old_thread
, new_thread
);
1226 last
= _switch(old_thread
, new_thread
);
1228 #ifdef CONFIG_PPC_BOOK3S_64
1229 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1230 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1231 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1235 if (current
->thread
.regs
) {
1236 restore_math(current
->thread
.regs
);
1239 * The copy-paste buffer can only store into foreign real
1240 * addresses, so unprivileged processes can not see the
1241 * data or use it in any way unless they have foreign real
1242 * mappings. If the new process has the foreign real address
1243 * mappings, we must issue a cp_abort to clear any state and
1244 * prevent snooping, corruption or a covert channel.
1246 if (current
->thread
.used_vas
)
1247 asm volatile(PPC_CP_ABORT
);
1249 #endif /* CONFIG_PPC_BOOK3S_64 */
1254 #define NR_INSN_TO_PRINT 16
1256 static void show_instructions(struct pt_regs
*regs
)
1259 unsigned long pc
= regs
->nip
- (NR_INSN_TO_PRINT
* 3 / 4 * sizeof(int));
1261 printk("Instruction dump:");
1263 for (i
= 0; i
< NR_INSN_TO_PRINT
; i
++) {
1269 #if !defined(CONFIG_BOOKE)
1270 /* If executing with the IMMU off, adjust pc rather
1271 * than print XXXXXXXX.
1273 if (!(regs
->msr
& MSR_IR
))
1274 pc
= (unsigned long)phys_to_virt(pc
);
1277 if (!__kernel_text_address(pc
) ||
1278 probe_kernel_address((const void *)pc
, instr
)) {
1279 pr_cont("XXXXXXXX ");
1281 if (regs
->nip
== pc
)
1282 pr_cont("<%08x> ", instr
);
1284 pr_cont("%08x ", instr
);
1293 void show_user_instructions(struct pt_regs
*regs
)
1296 int n
= NR_INSN_TO_PRINT
;
1298 char buf
[96]; /* enough for 8 times 9 + 2 chars */
1300 pc
= regs
->nip
- (NR_INSN_TO_PRINT
* 3 / 4 * sizeof(int));
1303 * Make sure the NIP points at userspace, not kernel text/data or
1306 if (!__access_ok(pc
, NR_INSN_TO_PRINT
* sizeof(int), USER_DS
)) {
1307 pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
1308 current
->comm
, current
->pid
);
1312 seq_buf_init(&s
, buf
, sizeof(buf
));
1319 for (i
= 0; i
< 8 && n
; i
++, n
--, pc
+= sizeof(int)) {
1322 if (probe_kernel_address((const void *)pc
, instr
)) {
1323 seq_buf_printf(&s
, "XXXXXXXX ");
1326 seq_buf_printf(&s
, regs
->nip
== pc
? "<%08x> " : "%08x ", instr
);
1329 if (!seq_buf_has_overflowed(&s
))
1330 pr_info("%s[%d]: code: %s\n", current
->comm
,
1331 current
->pid
, s
.buffer
);
1340 static struct regbit msr_bits
[] = {
1341 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1363 #ifndef CONFIG_BOOKE
1370 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1374 for (; bits
->bit
; ++bits
)
1375 if (val
& bits
->bit
) {
1376 pr_cont("%s%s", s
, bits
->name
);
1381 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1382 static struct regbit msr_tm_bits
[] = {
1389 static void print_tm_bits(unsigned long val
)
1392 * This only prints something if at least one of the TM bit is set.
1393 * Inside the TM[], the output means:
1394 * E: Enabled (bit 32)
1395 * S: Suspended (bit 33)
1396 * T: Transactional (bit 34)
1398 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1400 print_bits(val
, msr_tm_bits
, "");
1405 static void print_tm_bits(unsigned long val
) {}
1408 static void print_msr_bits(unsigned long val
)
1411 print_bits(val
, msr_bits
, ",");
1417 #define REG "%016lx"
1418 #define REGS_PER_LINE 4
1419 #define LAST_VOLATILE 13
1422 #define REGS_PER_LINE 8
1423 #define LAST_VOLATILE 12
1426 void show_regs(struct pt_regs
* regs
)
1430 show_regs_print_info(KERN_DEFAULT
);
1432 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1433 regs
->nip
, regs
->link
, regs
->ctr
);
1434 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1435 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1436 printk("MSR: "REG
" ", regs
->msr
);
1437 print_msr_bits(regs
->msr
);
1438 pr_cont(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1440 if ((TRAP(regs
) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1441 pr_cont("CFAR: "REG
" ", regs
->orig_gpr3
);
1442 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1443 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1444 pr_cont("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1446 pr_cont("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1449 pr_cont("IRQMASK: %lx ", regs
->softe
);
1451 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1452 if (MSR_TM_ACTIVE(regs
->msr
))
1453 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1456 for (i
= 0; i
< 32; i
++) {
1457 if ((i
% REGS_PER_LINE
) == 0)
1458 pr_cont("\nGPR%02d: ", i
);
1459 pr_cont(REG
" ", regs
->gpr
[i
]);
1460 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1464 #ifdef CONFIG_KALLSYMS
1466 * Lookup NIP late so we have the best change of getting the
1467 * above info out without failing
1469 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1470 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1472 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1473 if (!user_mode(regs
))
1474 show_instructions(regs
);
1477 void flush_thread(void)
1479 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1480 flush_ptrace_hw_breakpoint(current
);
1481 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1482 set_debug_reg_defaults(¤t
->thread
);
1483 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1486 #ifdef CONFIG_PPC_BOOK3S_64
1487 void arch_setup_new_exec(void)
1489 if (radix_enabled())
1491 hash__setup_new_exec();
1495 int set_thread_uses_vas(void)
1497 #ifdef CONFIG_PPC_BOOK3S_64
1498 if (!cpu_has_feature(CPU_FTR_ARCH_300
))
1501 current
->thread
.used_vas
= 1;
1504 * Even a process that has no foreign real address mapping can use
1505 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1506 * to clear any pending COPY and prevent a covert channel.
1508 * __switch_to() will issue CP_ABORT on future context switches.
1510 asm volatile(PPC_CP_ABORT
);
1512 #endif /* CONFIG_PPC_BOOK3S_64 */
1518 * Assign a TIDR (thread ID) for task @t and set it in the thread
1519 * structure. For now, we only support setting TIDR for 'current' task.
1521 * Since the TID value is a truncated form of it PID, it is possible
1522 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1523 * that 2 threads share the same TID and are waiting, one of the following
1524 * cases will happen:
1526 * 1. The correct thread is running, the wrong thread is not
1527 * In this situation, the correct thread is woken and proceeds to pass it's
1530 * 2. Neither threads are running
1531 * In this situation, neither thread will be woken. When scheduled, the waiting
1532 * threads will execute either a wait, which will return immediately, followed
1533 * by a condition check, which will pass for the correct thread and fail
1534 * for the wrong thread, or they will execute the condition check immediately.
1536 * 3. The wrong thread is running, the correct thread is not
1537 * The wrong thread will be woken, but will fail it's condition check and
1538 * re-execute wait. The correct thread, when scheduled, will execute either
1539 * it's condition check (which will pass), or wait, which returns immediately
1540 * when called the first time after the thread is scheduled, followed by it's
1541 * condition check (which will pass).
1543 * 4. Both threads are running
1544 * Both threads will be woken. The wrong thread will fail it's condition check
1545 * and execute another wait, while the correct thread will pass it's condition
1548 * @t: the task to set the thread ID for
1550 int set_thread_tidr(struct task_struct
*t
)
1552 if (!cpu_has_feature(CPU_FTR_P9_TIDR
))
1561 t
->thread
.tidr
= (u16
)task_pid_nr(t
);
1562 mtspr(SPRN_TIDR
, t
->thread
.tidr
);
1566 EXPORT_SYMBOL_GPL(set_thread_tidr
);
1568 #endif /* CONFIG_PPC64 */
1571 release_thread(struct task_struct
*t
)
1576 * this gets called so that we can store coprocessor state into memory and
1577 * copy the current task into the new thread.
1579 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1581 flush_all_to_thread(src
);
1583 * Flush TM state out so we can copy it. __switch_to_tm() does this
1584 * flush but it removes the checkpointed state from the current CPU and
1585 * transitions the CPU out of TM mode. Hence we need to call
1586 * tm_recheckpoint_new_task() (on the same task) to restore the
1587 * checkpointed state back and the TM mode.
1589 * Can't pass dst because it isn't ready. Doesn't matter, passing
1590 * dst is only important for __switch_to()
1592 __switch_to_tm(src
, src
);
1596 clear_task_ebb(dst
);
1601 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1603 #ifdef CONFIG_PPC_BOOK3S_64
1604 unsigned long sp_vsid
;
1605 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1607 if (radix_enabled())
1610 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1611 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1612 << SLB_VSID_SHIFT_1T
;
1614 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1616 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1617 p
->thread
.ksp_vsid
= sp_vsid
;
1626 * Copy architecture-specific thread state
1628 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1629 unsigned long kthread_arg
, struct task_struct
*p
)
1631 struct pt_regs
*childregs
, *kregs
;
1632 extern void ret_from_fork(void);
1633 extern void ret_from_kernel_thread(void);
1635 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1636 struct thread_info
*ti
= task_thread_info(p
);
1638 klp_init_thread_info(p
);
1640 /* Copy registers */
1641 sp
-= sizeof(struct pt_regs
);
1642 childregs
= (struct pt_regs
*) sp
;
1643 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1645 memset(childregs
, 0, sizeof(struct pt_regs
));
1646 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1649 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1651 clear_tsk_thread_flag(p
, TIF_32BIT
);
1652 childregs
->softe
= IRQS_ENABLED
;
1654 childregs
->gpr
[15] = kthread_arg
;
1655 p
->thread
.regs
= NULL
; /* no user register state */
1656 ti
->flags
|= _TIF_RESTOREALL
;
1657 f
= ret_from_kernel_thread
;
1660 struct pt_regs
*regs
= current_pt_regs();
1661 CHECK_FULL_REGS(regs
);
1664 childregs
->gpr
[1] = usp
;
1665 p
->thread
.regs
= childregs
;
1666 childregs
->gpr
[3] = 0; /* Result from fork() */
1667 if (clone_flags
& CLONE_SETTLS
) {
1669 if (!is_32bit_task())
1670 childregs
->gpr
[13] = childregs
->gpr
[6];
1673 childregs
->gpr
[2] = childregs
->gpr
[6];
1678 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1679 sp
-= STACK_FRAME_OVERHEAD
;
1682 * The way this works is that at some point in the future
1683 * some task will call _switch to switch to the new task.
1684 * That will pop off the stack frame created below and start
1685 * the new task running at ret_from_fork. The new task will
1686 * do some house keeping and then return from the fork or clone
1687 * system call, using the stack frame created above.
1689 ((unsigned long *)sp
)[0] = 0;
1690 sp
-= sizeof(struct pt_regs
);
1691 kregs
= (struct pt_regs
*) sp
;
1692 sp
-= STACK_FRAME_OVERHEAD
;
1695 p
->thread
.ksp_limit
= (unsigned long)end_of_stack(p
);
1697 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1698 p
->thread
.ptrace_bps
[0] = NULL
;
1701 p
->thread
.fp_save_area
= NULL
;
1702 #ifdef CONFIG_ALTIVEC
1703 p
->thread
.vr_save_area
= NULL
;
1706 setup_ksp_vsid(p
, sp
);
1709 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1710 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1711 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1713 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1714 childregs
->ppr
= DEFAULT_PPR
;
1718 kregs
->nip
= ppc_function_entry(f
);
1722 void preload_new_slb_context(unsigned long start
, unsigned long sp
);
1725 * Set up a thread for executing a new program
1727 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1730 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1732 #ifdef CONFIG_PPC_BOOK3S_64
1733 preload_new_slb_context(start
, sp
);
1738 * If we exec out of a kernel thread then thread.regs will not be
1741 if (!current
->thread
.regs
) {
1742 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1743 current
->thread
.regs
= regs
- 1;
1746 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1748 * Clear any transactional state, we're exec()ing. The cause is
1749 * not important as there will never be a recheckpoint so it's not
1752 if (MSR_TM_SUSPENDED(mfmsr()))
1753 tm_reclaim_current(0);
1756 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1764 * We have just cleared all the nonvolatile GPRs, so make
1765 * FULL_REGS(regs) return true. This is necessary to allow
1766 * ptrace to examine the thread immediately after exec.
1773 regs
->msr
= MSR_USER
;
1775 if (!is_32bit_task()) {
1776 unsigned long entry
;
1778 if (is_elf2_task()) {
1779 /* Look ma, no function descriptors! */
1784 * The latest iteration of the ABI requires that when
1785 * calling a function (at its global entry point),
1786 * the caller must ensure r12 holds the entry point
1787 * address (so that the function can quickly
1788 * establish addressability).
1790 regs
->gpr
[12] = start
;
1791 /* Make sure that's restored on entry to userspace. */
1792 set_thread_flag(TIF_RESTOREALL
);
1796 /* start is a relocated pointer to the function
1797 * descriptor for the elf _start routine. The first
1798 * entry in the function descriptor is the entry
1799 * address of _start and the second entry is the TOC
1800 * value we need to use.
1802 __get_user(entry
, (unsigned long __user
*)start
);
1803 __get_user(toc
, (unsigned long __user
*)start
+1);
1805 /* Check whether the e_entry function descriptor entries
1806 * need to be relocated before we can use them.
1808 if (load_addr
!= 0) {
1815 regs
->msr
= MSR_USER64
;
1819 regs
->msr
= MSR_USER32
;
1823 current
->thread
.used_vsr
= 0;
1825 current
->thread
.load_slb
= 0;
1826 current
->thread
.load_fp
= 0;
1827 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1828 current
->thread
.fp_save_area
= NULL
;
1829 #ifdef CONFIG_ALTIVEC
1830 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1831 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1832 current
->thread
.vr_save_area
= NULL
;
1833 current
->thread
.vrsave
= 0;
1834 current
->thread
.used_vr
= 0;
1835 current
->thread
.load_vec
= 0;
1836 #endif /* CONFIG_ALTIVEC */
1838 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1839 current
->thread
.acc
= 0;
1840 current
->thread
.spefscr
= 0;
1841 current
->thread
.used_spe
= 0;
1842 #endif /* CONFIG_SPE */
1843 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1844 current
->thread
.tm_tfhar
= 0;
1845 current
->thread
.tm_texasr
= 0;
1846 current
->thread
.tm_tfiar
= 0;
1847 current
->thread
.load_tm
= 0;
1848 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1850 thread_pkey_regs_init(¤t
->thread
);
1852 EXPORT_SYMBOL(start_thread
);
1854 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1855 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1857 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1859 struct pt_regs
*regs
= tsk
->thread
.regs
;
1861 /* This is a bit hairy. If we are an SPE enabled processor
1862 * (have embedded fp) we store the IEEE exception enable flags in
1863 * fpexc_mode. fpexc_mode is also used for setting FP exception
1864 * mode (asyn, precise, disabled) for 'Classic' FP. */
1865 if (val
& PR_FP_EXC_SW_ENABLE
) {
1867 if (cpu_has_feature(CPU_FTR_SPE
)) {
1869 * When the sticky exception bits are set
1870 * directly by userspace, it must call prctl
1871 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1872 * in the existing prctl settings) or
1873 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1874 * the bits being set). <fenv.h> functions
1875 * saving and restoring the whole
1876 * floating-point environment need to do so
1877 * anyway to restore the prctl settings from
1878 * the saved environment.
1880 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1881 tsk
->thread
.fpexc_mode
= val
&
1882 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1892 /* on a CONFIG_SPE this does not hurt us. The bits that
1893 * __pack_fe01 use do not overlap with bits used for
1894 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1895 * on CONFIG_SPE implementations are reserved so writing to
1896 * them does not change anything */
1897 if (val
> PR_FP_EXC_PRECISE
)
1899 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1900 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1901 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1902 | tsk
->thread
.fpexc_mode
;
1906 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1910 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1912 if (cpu_has_feature(CPU_FTR_SPE
)) {
1914 * When the sticky exception bits are set
1915 * directly by userspace, it must call prctl
1916 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1917 * in the existing prctl settings) or
1918 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1919 * the bits being set). <fenv.h> functions
1920 * saving and restoring the whole
1921 * floating-point environment need to do so
1922 * anyway to restore the prctl settings from
1923 * the saved environment.
1925 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1926 val
= tsk
->thread
.fpexc_mode
;
1933 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1934 return put_user(val
, (unsigned int __user
*) adr
);
1937 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1939 struct pt_regs
*regs
= tsk
->thread
.regs
;
1941 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1942 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1948 if (val
== PR_ENDIAN_BIG
)
1949 regs
->msr
&= ~MSR_LE
;
1950 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1951 regs
->msr
|= MSR_LE
;
1958 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1960 struct pt_regs
*regs
= tsk
->thread
.regs
;
1963 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1964 !cpu_has_feature(CPU_FTR_REAL_LE
))
1970 if (regs
->msr
& MSR_LE
) {
1971 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1972 val
= PR_ENDIAN_LITTLE
;
1974 val
= PR_ENDIAN_PPC_LITTLE
;
1976 val
= PR_ENDIAN_BIG
;
1978 return put_user(val
, (unsigned int __user
*)adr
);
1981 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1983 tsk
->thread
.align_ctl
= val
;
1987 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1989 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1992 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1993 unsigned long nbytes
)
1995 unsigned long stack_page
;
1996 unsigned long cpu
= task_cpu(p
);
1998 stack_page
= (unsigned long)hardirq_ctx
[cpu
];
1999 if (sp
>= stack_page
&& sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
2002 stack_page
= (unsigned long)softirq_ctx
[cpu
];
2003 if (sp
>= stack_page
&& sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
2009 int validate_sp(unsigned long sp
, struct task_struct
*p
,
2010 unsigned long nbytes
)
2012 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
2014 if (sp
< THREAD_SIZE
)
2017 if (sp
>= stack_page
&& sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
2020 return valid_irq_stack(sp
, p
, nbytes
);
2023 EXPORT_SYMBOL(validate_sp
);
2025 static unsigned long __get_wchan(struct task_struct
*p
)
2027 unsigned long ip
, sp
;
2030 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
2034 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
2038 sp
= *(unsigned long *)sp
;
2039 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
) ||
2040 p
->state
== TASK_RUNNING
)
2043 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
2044 if (!in_sched_functions(ip
))
2047 } while (count
++ < 16);
2051 unsigned long get_wchan(struct task_struct
*p
)
2055 if (!try_get_task_stack(p
))
2058 ret
= __get_wchan(p
);
2065 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
2067 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
2069 unsigned long sp
, ip
, lr
, newsp
;
2072 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2073 struct ftrace_ret_stack
*ret_stack
;
2074 extern void return_to_handler(void);
2075 unsigned long rth
= (unsigned long)return_to_handler
;
2082 if (!try_get_task_stack(tsk
))
2085 sp
= (unsigned long) stack
;
2088 sp
= current_stack_pointer();
2090 sp
= tsk
->thread
.ksp
;
2094 printk("Call Trace:\n");
2096 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
2099 stack
= (unsigned long *) sp
;
2101 ip
= stack
[STACK_FRAME_LR_SAVE
];
2102 if (!firstframe
|| ip
!= lr
) {
2103 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
2104 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2105 if ((ip
== rth
) && curr_frame
>= 0) {
2106 ret_stack
= ftrace_graph_get_ret_stack(current
,
2110 (void *)ret_stack
->ret
);
2116 pr_cont(" (unreliable)");
2122 * See if this is an exception frame.
2123 * We look for the "regshere" marker in the current frame.
2125 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
2126 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
2127 struct pt_regs
*regs
= (struct pt_regs
*)
2128 (sp
+ STACK_FRAME_OVERHEAD
);
2130 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
2131 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
2136 } while (count
++ < kstack_depth_to_print
);
2138 put_task_stack(tsk
);
2142 /* Called with hard IRQs off */
2143 void notrace
__ppc64_runlatch_on(void)
2145 struct thread_info
*ti
= current_thread_info();
2147 if (cpu_has_feature(CPU_FTR_ARCH_206
)) {
2149 * Least significant bit (RUN) is the only writable bit of
2150 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2151 * earliest ISA where this is the case, but it's convenient.
2153 mtspr(SPRN_CTRLT
, CTRL_RUNLATCH
);
2158 * Some architectures (e.g., Cell) have writable fields other
2159 * than RUN, so do the read-modify-write.
2161 ctrl
= mfspr(SPRN_CTRLF
);
2162 ctrl
|= CTRL_RUNLATCH
;
2163 mtspr(SPRN_CTRLT
, ctrl
);
2166 ti
->local_flags
|= _TLF_RUNLATCH
;
2169 /* Called with hard IRQs off */
2170 void notrace
__ppc64_runlatch_off(void)
2172 struct thread_info
*ti
= current_thread_info();
2174 ti
->local_flags
&= ~_TLF_RUNLATCH
;
2176 if (cpu_has_feature(CPU_FTR_ARCH_206
)) {
2177 mtspr(SPRN_CTRLT
, 0);
2181 ctrl
= mfspr(SPRN_CTRLF
);
2182 ctrl
&= ~CTRL_RUNLATCH
;
2183 mtspr(SPRN_CTRLT
, ctrl
);
2186 #endif /* CONFIG_PPC64 */
2188 unsigned long arch_align_stack(unsigned long sp
)
2190 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
2191 sp
-= get_random_int() & ~PAGE_MASK
;
2195 static inline unsigned long brk_rnd(void)
2197 unsigned long rnd
= 0;
2199 /* 8MB for 32bit, 1GB for 64bit */
2200 if (is_32bit_task())
2201 rnd
= (get_random_long() % (1UL<<(23-PAGE_SHIFT
)));
2203 rnd
= (get_random_long() % (1UL<<(30-PAGE_SHIFT
)));
2205 return rnd
<< PAGE_SHIFT
;
2208 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
2210 unsigned long base
= mm
->brk
;
2213 #ifdef CONFIG_PPC_BOOK3S_64
2215 * If we are using 1TB segments and we are allowed to randomise
2216 * the heap, we can put it above 1TB so it is backed by a 1TB
2217 * segment. Otherwise the heap will be in the bottom 1TB
2218 * which always uses 256MB segments and this may result in a
2219 * performance penalty. We don't need to worry about radix. For
2220 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2222 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
2223 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
2226 ret
= PAGE_ALIGN(base
+ brk_rnd());