2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/prctl.h>
29 #include <linux/init_task.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/mqueue.h>
33 #include <linux/hardirq.h>
34 #include <linux/utsname.h>
35 #include <linux/ftrace.h>
36 #include <linux/kernel_stat.h>
37 #include <linux/personality.h>
38 #include <linux/random.h>
39 #include <linux/hw_breakpoint.h>
40 #include <linux/uaccess.h>
42 #include <asm/pgtable.h>
44 #include <asm/processor.h>
47 #include <asm/machdep.h>
49 #include <asm/runlatch.h>
50 #include <asm/syscalls.h>
51 #include <asm/switch_to.h>
53 #include <asm/debug.h>
55 #include <asm/firmware.h>
57 #include <asm/code-patching.h>
58 #include <linux/kprobes.h>
59 #include <linux/kdebug.h>
61 /* Transactional Memory debug */
63 #define TM_DEBUG(x...) printk(KERN_INFO x)
65 #define TM_DEBUG(x...) do { } while(0)
68 extern unsigned long _get_SP(void);
70 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
71 static void check_if_tm_restore_required(struct task_struct
*tsk
)
74 * If we are saving the current thread's registers, and the
75 * thread is in a transactional state, set the TIF_RESTORE_TM
76 * bit so that we know to restore the registers before
77 * returning to userspace.
79 if (tsk
== current
&& tsk
->thread
.regs
&&
80 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
81 !test_thread_flag(TIF_RESTORE_TM
)) {
82 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
83 set_thread_flag(TIF_RESTORE_TM
);
87 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
88 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
90 bool strict_msr_control
;
91 EXPORT_SYMBOL(strict_msr_control
);
93 static int __init
enable_strict_msr_control(char *str
)
95 strict_msr_control
= true;
96 pr_info("Enabling strict facility control\n");
100 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
102 void msr_check_and_set(unsigned long bits
)
104 unsigned long oldmsr
= mfmsr();
105 unsigned long newmsr
;
107 newmsr
= oldmsr
| bits
;
110 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
114 if (oldmsr
!= newmsr
)
118 void __msr_check_and_clear(unsigned long bits
)
120 unsigned long oldmsr
= mfmsr();
121 unsigned long newmsr
;
123 newmsr
= oldmsr
& ~bits
;
126 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
130 if (oldmsr
!= newmsr
)
133 EXPORT_SYMBOL(__msr_check_and_clear
);
135 #ifdef CONFIG_PPC_FPU
136 void giveup_fpu(struct task_struct
*tsk
)
138 check_if_tm_restore_required(tsk
);
140 msr_check_and_set(MSR_FP
);
142 msr_check_and_clear(MSR_FP
);
144 EXPORT_SYMBOL(giveup_fpu
);
147 * Make sure the floating-point register state in the
148 * the thread_struct is up to date for task tsk.
150 void flush_fp_to_thread(struct task_struct
*tsk
)
152 if (tsk
->thread
.regs
) {
154 * We need to disable preemption here because if we didn't,
155 * another process could get scheduled after the regs->msr
156 * test but before we have finished saving the FP registers
157 * to the thread_struct. That process could take over the
158 * FPU, and then when we get scheduled again we would store
159 * bogus values for the remaining FP registers.
162 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
164 * This should only ever be called for current or
165 * for a stopped child process. Since we save away
166 * the FP register state on context switch,
167 * there is something wrong if a stopped child appears
168 * to still have its FP state in the CPU registers.
170 BUG_ON(tsk
!= current
);
176 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
178 void enable_kernel_fp(void)
180 WARN_ON(preemptible());
182 msr_check_and_set(MSR_FP
);
184 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
185 check_if_tm_restore_required(current
);
186 __giveup_fpu(current
);
189 EXPORT_SYMBOL(enable_kernel_fp
);
191 static int restore_fp(struct task_struct
*tsk
) {
192 if (tsk
->thread
.load_fp
) {
193 load_fp_state(¤t
->thread
.fp_state
);
194 current
->thread
.load_fp
++;
200 static int restore_fp(struct task_struct
*tsk
) { return 0; }
201 #endif /* CONFIG_PPC_FPU */
203 #ifdef CONFIG_ALTIVEC
204 #define loadvec(thr) ((thr).load_vec)
206 void giveup_altivec(struct task_struct
*tsk
)
208 check_if_tm_restore_required(tsk
);
210 msr_check_and_set(MSR_VEC
);
211 __giveup_altivec(tsk
);
212 msr_check_and_clear(MSR_VEC
);
214 EXPORT_SYMBOL(giveup_altivec
);
216 void enable_kernel_altivec(void)
218 WARN_ON(preemptible());
220 msr_check_and_set(MSR_VEC
);
222 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
223 check_if_tm_restore_required(current
);
224 __giveup_altivec(current
);
227 EXPORT_SYMBOL(enable_kernel_altivec
);
230 * Make sure the VMX/Altivec register state in the
231 * the thread_struct is up to date for task tsk.
233 void flush_altivec_to_thread(struct task_struct
*tsk
)
235 if (tsk
->thread
.regs
) {
237 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
238 BUG_ON(tsk
!= current
);
244 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
246 static int restore_altivec(struct task_struct
*tsk
)
248 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && tsk
->thread
.load_vec
) {
249 load_vr_state(&tsk
->thread
.vr_state
);
250 tsk
->thread
.used_vr
= 1;
251 tsk
->thread
.load_vec
++;
258 #define loadvec(thr) 0
259 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
260 #endif /* CONFIG_ALTIVEC */
263 void giveup_vsx(struct task_struct
*tsk
)
265 check_if_tm_restore_required(tsk
);
267 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
268 if (tsk
->thread
.regs
->msr
& MSR_FP
)
270 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
271 __giveup_altivec(tsk
);
273 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
275 EXPORT_SYMBOL(giveup_vsx
);
277 void enable_kernel_vsx(void)
279 WARN_ON(preemptible());
281 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
283 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VSX
)) {
284 check_if_tm_restore_required(current
);
285 if (current
->thread
.regs
->msr
& MSR_FP
)
286 __giveup_fpu(current
);
287 if (current
->thread
.regs
->msr
& MSR_VEC
)
288 __giveup_altivec(current
);
289 __giveup_vsx(current
);
292 EXPORT_SYMBOL(enable_kernel_vsx
);
294 void flush_vsx_to_thread(struct task_struct
*tsk
)
296 if (tsk
->thread
.regs
) {
298 if (tsk
->thread
.regs
->msr
& MSR_VSX
) {
299 BUG_ON(tsk
!= current
);
305 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
307 static int restore_vsx(struct task_struct
*tsk
)
309 if (cpu_has_feature(CPU_FTR_VSX
)) {
310 tsk
->thread
.used_vsr
= 1;
317 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
318 #endif /* CONFIG_VSX */
321 void giveup_spe(struct task_struct
*tsk
)
323 check_if_tm_restore_required(tsk
);
325 msr_check_and_set(MSR_SPE
);
327 msr_check_and_clear(MSR_SPE
);
329 EXPORT_SYMBOL(giveup_spe
);
331 void enable_kernel_spe(void)
333 WARN_ON(preemptible());
335 msr_check_and_set(MSR_SPE
);
337 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
338 check_if_tm_restore_required(current
);
339 __giveup_spe(current
);
342 EXPORT_SYMBOL(enable_kernel_spe
);
344 void flush_spe_to_thread(struct task_struct
*tsk
)
346 if (tsk
->thread
.regs
) {
348 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
349 BUG_ON(tsk
!= current
);
350 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
356 #endif /* CONFIG_SPE */
358 static unsigned long msr_all_available
;
360 static int __init
init_msr_all_available(void)
362 #ifdef CONFIG_PPC_FPU
363 msr_all_available
|= MSR_FP
;
365 #ifdef CONFIG_ALTIVEC
366 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
367 msr_all_available
|= MSR_VEC
;
370 if (cpu_has_feature(CPU_FTR_VSX
))
371 msr_all_available
|= MSR_VSX
;
374 if (cpu_has_feature(CPU_FTR_SPE
))
375 msr_all_available
|= MSR_SPE
;
380 early_initcall(init_msr_all_available
);
382 void giveup_all(struct task_struct
*tsk
)
384 unsigned long usermsr
;
386 if (!tsk
->thread
.regs
)
389 usermsr
= tsk
->thread
.regs
->msr
;
391 if ((usermsr
& msr_all_available
) == 0)
394 msr_check_and_set(msr_all_available
);
396 #ifdef CONFIG_PPC_FPU
397 if (usermsr
& MSR_FP
)
400 #ifdef CONFIG_ALTIVEC
401 if (usermsr
& MSR_VEC
)
402 __giveup_altivec(tsk
);
405 if (usermsr
& MSR_VSX
)
409 if (usermsr
& MSR_SPE
)
413 msr_check_and_clear(msr_all_available
);
415 EXPORT_SYMBOL(giveup_all
);
417 void restore_math(struct pt_regs
*regs
)
421 if (!current
->thread
.load_fp
&& !loadvec(current
->thread
))
425 msr_check_and_set(msr_all_available
);
428 * Only reload if the bit is not set in the user MSR, the bit BEING set
429 * indicates that the registers are hot
431 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
432 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
434 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
437 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
438 restore_vsx(current
)) {
442 msr_check_and_clear(msr_all_available
);
447 void save_all(struct task_struct
*tsk
)
449 unsigned long usermsr
;
451 if (!tsk
->thread
.regs
)
454 usermsr
= tsk
->thread
.regs
->msr
;
456 if ((usermsr
& msr_all_available
) == 0)
459 msr_check_and_set(msr_all_available
);
461 if (usermsr
& MSR_FP
)
464 if (usermsr
& MSR_VEC
)
465 __giveup_altivec(tsk
);
467 if (usermsr
& MSR_VSX
)
470 if (usermsr
& MSR_SPE
)
473 msr_check_and_clear(msr_all_available
);
476 void flush_all_to_thread(struct task_struct
*tsk
)
478 if (tsk
->thread
.regs
) {
480 BUG_ON(tsk
!= current
);
484 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
485 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
491 EXPORT_SYMBOL(flush_all_to_thread
);
493 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
494 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
495 unsigned long error_code
, int signal_code
, int breakpt
)
499 current
->thread
.trap_nr
= signal_code
;
500 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
501 11, SIGSEGV
) == NOTIFY_STOP
)
504 /* Deliver the signal to userspace */
505 info
.si_signo
= SIGTRAP
;
506 info
.si_errno
= breakpt
; /* breakpoint or watchpoint id */
507 info
.si_code
= signal_code
;
508 info
.si_addr
= (void __user
*)address
;
509 force_sig_info(SIGTRAP
, &info
, current
);
511 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
512 void do_break (struct pt_regs
*regs
, unsigned long address
,
513 unsigned long error_code
)
517 current
->thread
.trap_nr
= TRAP_HWBKPT
;
518 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
519 11, SIGSEGV
) == NOTIFY_STOP
)
522 if (debugger_break_match(regs
))
525 /* Clear the breakpoint */
526 hw_breakpoint_disable();
528 /* Deliver the signal to userspace */
529 info
.si_signo
= SIGTRAP
;
531 info
.si_code
= TRAP_HWBKPT
;
532 info
.si_addr
= (void __user
*)address
;
533 force_sig_info(SIGTRAP
, &info
, current
);
535 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
537 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
539 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
541 * Set the debug registers back to their default "safe" values.
543 static void set_debug_reg_defaults(struct thread_struct
*thread
)
545 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
546 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
547 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
549 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
550 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
551 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
553 thread
->debug
.dbcr0
= 0;
556 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
558 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
559 DBCR1_IAC3US
| DBCR1_IAC4US
;
561 * Force Data Address Compare User/Supervisor bits to be User-only
562 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
564 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
566 thread
->debug
.dbcr1
= 0;
570 static void prime_debug_regs(struct debug_reg
*debug
)
573 * We could have inherited MSR_DE from userspace, since
574 * it doesn't get cleared on exception entry. Make sure
575 * MSR_DE is clear before we enable any debug events.
577 mtmsr(mfmsr() & ~MSR_DE
);
579 mtspr(SPRN_IAC1
, debug
->iac1
);
580 mtspr(SPRN_IAC2
, debug
->iac2
);
581 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
582 mtspr(SPRN_IAC3
, debug
->iac3
);
583 mtspr(SPRN_IAC4
, debug
->iac4
);
585 mtspr(SPRN_DAC1
, debug
->dac1
);
586 mtspr(SPRN_DAC2
, debug
->dac2
);
587 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
588 mtspr(SPRN_DVC1
, debug
->dvc1
);
589 mtspr(SPRN_DVC2
, debug
->dvc2
);
591 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
592 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
594 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
598 * Unless neither the old or new thread are making use of the
599 * debug registers, set the debug registers from the values
600 * stored in the new thread.
602 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
604 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
605 || (new_debug
->dbcr0
& DBCR0_IDM
))
606 prime_debug_regs(new_debug
);
608 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
609 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
610 #ifndef CONFIG_HAVE_HW_BREAKPOINT
611 static void set_debug_reg_defaults(struct thread_struct
*thread
)
613 thread
->hw_brk
.address
= 0;
614 thread
->hw_brk
.type
= 0;
615 set_breakpoint(&thread
->hw_brk
);
617 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
618 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
620 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
621 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
623 mtspr(SPRN_DAC1
, dabr
);
624 #ifdef CONFIG_PPC_47x
629 #elif defined(CONFIG_PPC_BOOK3S)
630 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
632 mtspr(SPRN_DABR
, dabr
);
633 if (cpu_has_feature(CPU_FTR_DABRX
))
634 mtspr(SPRN_DABRX
, dabrx
);
638 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
644 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
646 unsigned long dabr
, dabrx
;
648 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
649 dabrx
= ((brk
->type
>> 3) & 0x7);
652 return ppc_md
.set_dabr(dabr
, dabrx
);
654 return __set_dabr(dabr
, dabrx
);
657 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
659 unsigned long dawr
, dawrx
, mrd
;
663 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
664 << (63 - 58); //* read/write bits */
665 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
666 << (63 - 59); //* translate */
667 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
668 >> 3; //* PRIM bits */
669 /* dawr length is stored in field MDR bits 48:53. Matches range in
670 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
672 brk->len is in bytes.
673 This aligns up to double word size, shifts and does the bias.
675 mrd
= ((brk
->len
+ 7) >> 3) - 1;
676 dawrx
|= (mrd
& 0x3f) << (63 - 53);
679 return ppc_md
.set_dawr(dawr
, dawrx
);
680 mtspr(SPRN_DAWR
, dawr
);
681 mtspr(SPRN_DAWRX
, dawrx
);
685 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
687 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
689 if (cpu_has_feature(CPU_FTR_DAWR
))
695 void set_breakpoint(struct arch_hw_breakpoint
*brk
)
698 __set_breakpoint(brk
);
703 DEFINE_PER_CPU(struct cpu_usage
, cpu_usage_array
);
706 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
707 struct arch_hw_breakpoint
*b
)
709 if (a
->address
!= b
->address
)
711 if (a
->type
!= b
->type
)
713 if (a
->len
!= b
->len
)
718 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
719 static void tm_reclaim_thread(struct thread_struct
*thr
,
720 struct thread_info
*ti
, uint8_t cause
)
722 unsigned long msr_diff
= 0;
725 * If FP/VSX registers have been already saved to the
726 * thread_struct, move them to the transact_fp array.
727 * We clear the TIF_RESTORE_TM bit since after the reclaim
728 * the thread will no longer be transactional.
730 if (test_ti_thread_flag(ti
, TIF_RESTORE_TM
)) {
731 msr_diff
= thr
->ckpt_regs
.msr
& ~thr
->regs
->msr
;
732 if (msr_diff
& MSR_FP
)
733 memcpy(&thr
->transact_fp
, &thr
->fp_state
,
734 sizeof(struct thread_fp_state
));
735 if (msr_diff
& MSR_VEC
)
736 memcpy(&thr
->transact_vr
, &thr
->vr_state
,
737 sizeof(struct thread_vr_state
));
738 clear_ti_thread_flag(ti
, TIF_RESTORE_TM
);
739 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
| MSR_FE0
| MSR_FE1
;
743 * Use the current MSR TM suspended bit to track if we have
744 * checkpointed state outstanding.
745 * On signal delivery, we'd normally reclaim the checkpointed
746 * state to obtain stack pointer (see:get_tm_stackpointer()).
747 * This will then directly return to userspace without going
748 * through __switch_to(). However, if the stack frame is bad,
749 * we need to exit this thread which calls __switch_to() which
750 * will again attempt to reclaim the already saved tm state.
751 * Hence we need to check that we've not already reclaimed
753 * We do this using the current MSR, rather tracking it in
754 * some specific thread_struct bit, as it has the additional
755 * benifit of checking for a potential TM bad thing exception.
757 if (!MSR_TM_SUSPENDED(mfmsr()))
760 tm_reclaim(thr
, thr
->regs
->msr
, cause
);
762 /* Having done the reclaim, we now have the checkpointed
763 * FP/VSX values in the registers. These might be valid
764 * even if we have previously called enable_kernel_fp() or
765 * flush_fp_to_thread(), so update thr->regs->msr to
766 * indicate their current validity.
768 thr
->regs
->msr
|= msr_diff
;
771 void tm_reclaim_current(uint8_t cause
)
774 tm_reclaim_thread(¤t
->thread
, current_thread_info(), cause
);
777 static inline void tm_reclaim_task(struct task_struct
*tsk
)
779 /* We have to work out if we're switching from/to a task that's in the
780 * middle of a transaction.
782 * In switching we need to maintain a 2nd register state as
783 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
784 * checkpointed (tbegin) state in ckpt_regs and saves the transactional
785 * (current) FPRs into oldtask->thread.transact_fpr[].
787 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
789 struct thread_struct
*thr
= &tsk
->thread
;
794 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
795 goto out_and_saveregs
;
797 /* Stash the original thread MSR, as giveup_fpu et al will
798 * modify it. We hold onto it to see whether the task used
799 * FP & vector regs. If the TIF_RESTORE_TM flag is set,
800 * ckpt_regs.msr is already set.
802 if (!test_ti_thread_flag(task_thread_info(tsk
), TIF_RESTORE_TM
))
803 thr
->ckpt_regs
.msr
= thr
->regs
->msr
;
805 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
806 "ccr=%lx, msr=%lx, trap=%lx)\n",
807 tsk
->pid
, thr
->regs
->nip
,
808 thr
->regs
->ccr
, thr
->regs
->msr
,
811 tm_reclaim_thread(thr
, task_thread_info(tsk
), TM_CAUSE_RESCHED
);
813 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
817 /* Always save the regs here, even if a transaction's not active.
818 * This context-switches a thread's TM info SPRs. We do it here to
819 * be consistent with the restore path (in recheckpoint) which
820 * cannot happen later in _switch().
825 extern void __tm_recheckpoint(struct thread_struct
*thread
,
826 unsigned long orig_msr
);
828 void tm_recheckpoint(struct thread_struct
*thread
,
829 unsigned long orig_msr
)
833 /* We really can't be interrupted here as the TEXASR registers can't
834 * change and later in the trecheckpoint code, we have a userspace R1.
835 * So let's hard disable over this region.
837 local_irq_save(flags
);
840 /* The TM SPRs are restored here, so that TEXASR.FS can be set
841 * before the trecheckpoint and no explosion occurs.
843 tm_restore_sprs(thread
);
845 __tm_recheckpoint(thread
, orig_msr
);
847 local_irq_restore(flags
);
850 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
854 if (!cpu_has_feature(CPU_FTR_TM
))
857 /* Recheckpoint the registers of the thread we're about to switch to.
859 * If the task was using FP, we non-lazily reload both the original and
860 * the speculative FP register states. This is because the kernel
861 * doesn't see if/when a TM rollback occurs, so if we take an FP
862 * unavoidable later, we are unable to determine which set of FP regs
863 * need to be restored.
865 if (!new->thread
.regs
)
868 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
869 tm_restore_sprs(&new->thread
);
872 msr
= new->thread
.ckpt_regs
.msr
;
873 /* Recheckpoint to restore original checkpointed register state. */
874 TM_DEBUG("*** tm_recheckpoint of pid %d "
875 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
876 new->pid
, new->thread
.regs
->msr
, msr
);
878 /* This loads the checkpointed FP/VEC state, if used */
879 tm_recheckpoint(&new->thread
, msr
);
881 /* This loads the speculative FP/VEC state, if used */
883 do_load_up_transact_fpu(&new->thread
);
884 new->thread
.regs
->msr
|=
885 (MSR_FP
| new->thread
.fpexc_mode
);
887 #ifdef CONFIG_ALTIVEC
889 do_load_up_transact_altivec(&new->thread
);
890 new->thread
.regs
->msr
|= MSR_VEC
;
893 /* We may as well turn on VSX too since all the state is restored now */
895 new->thread
.regs
->msr
|= MSR_VSX
;
897 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
898 "(kernel msr 0x%lx)\n",
902 static inline void __switch_to_tm(struct task_struct
*prev
)
904 if (cpu_has_feature(CPU_FTR_TM
)) {
906 tm_reclaim_task(prev
);
911 * This is called if we are on the way out to userspace and the
912 * TIF_RESTORE_TM flag is set. It checks if we need to reload
913 * FP and/or vector state and does so if necessary.
914 * If userspace is inside a transaction (whether active or
915 * suspended) and FP/VMX/VSX instructions have ever been enabled
916 * inside that transaction, then we have to keep them enabled
917 * and keep the FP/VMX/VSX state loaded while ever the transaction
918 * continues. The reason is that if we didn't, and subsequently
919 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
920 * we don't know whether it's the same transaction, and thus we
921 * don't know which of the checkpointed state and the transactional
924 void restore_tm_state(struct pt_regs
*regs
)
926 unsigned long msr_diff
;
928 clear_thread_flag(TIF_RESTORE_TM
);
929 if (!MSR_TM_ACTIVE(regs
->msr
))
932 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
933 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
937 regs
->msr
|= msr_diff
;
941 #define tm_recheckpoint_new_task(new)
942 #define __switch_to_tm(prev)
943 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
945 static inline void save_sprs(struct thread_struct
*t
)
947 #ifdef CONFIG_ALTIVEC
948 if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC
)))
949 t
->vrsave
= mfspr(SPRN_VRSAVE
);
951 #ifdef CONFIG_PPC_BOOK3S_64
952 if (cpu_has_feature(CPU_FTR_DSCR
))
953 t
->dscr
= mfspr(SPRN_DSCR
);
955 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
956 t
->bescr
= mfspr(SPRN_BESCR
);
957 t
->ebbhr
= mfspr(SPRN_EBBHR
);
958 t
->ebbrr
= mfspr(SPRN_EBBRR
);
960 t
->fscr
= mfspr(SPRN_FSCR
);
963 * Note that the TAR is not available for use in the kernel.
964 * (To provide this, the TAR should be backed up/restored on
965 * exception entry/exit instead, and be in pt_regs. FIXME,
966 * this should be in pt_regs anyway (for debug).)
968 t
->tar
= mfspr(SPRN_TAR
);
973 static inline void restore_sprs(struct thread_struct
*old_thread
,
974 struct thread_struct
*new_thread
)
976 #ifdef CONFIG_ALTIVEC
977 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
978 old_thread
->vrsave
!= new_thread
->vrsave
)
979 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
981 #ifdef CONFIG_PPC_BOOK3S_64
982 if (cpu_has_feature(CPU_FTR_DSCR
)) {
983 u64 dscr
= get_paca()->dscr_default
;
984 u64 fscr
= old_thread
->fscr
& ~FSCR_DSCR
;
986 if (new_thread
->dscr_inherit
) {
987 dscr
= new_thread
->dscr
;
991 if (old_thread
->dscr
!= dscr
)
992 mtspr(SPRN_DSCR
, dscr
);
994 if (old_thread
->fscr
!= fscr
)
995 mtspr(SPRN_FSCR
, fscr
);
998 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
999 if (old_thread
->bescr
!= new_thread
->bescr
)
1000 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1001 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1002 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1003 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1004 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1006 if (old_thread
->tar
!= new_thread
->tar
)
1007 mtspr(SPRN_TAR
, new_thread
->tar
);
1012 struct task_struct
*__switch_to(struct task_struct
*prev
,
1013 struct task_struct
*new)
1015 struct thread_struct
*new_thread
, *old_thread
;
1016 struct task_struct
*last
;
1017 #ifdef CONFIG_PPC_BOOK3S_64
1018 struct ppc64_tlb_batch
*batch
;
1021 new_thread
= &new->thread
;
1022 old_thread
= ¤t
->thread
;
1024 WARN_ON(!irqs_disabled());
1028 * Collect processor utilization data per process
1030 if (firmware_has_feature(FW_FEATURE_SPLPAR
)) {
1031 struct cpu_usage
*cu
= this_cpu_ptr(&cpu_usage_array
);
1032 long unsigned start_tb
, current_tb
;
1033 start_tb
= old_thread
->start_tb
;
1034 cu
->current_tb
= current_tb
= mfspr(SPRN_PURR
);
1035 old_thread
->accum_tb
+= (current_tb
- start_tb
);
1036 new_thread
->start_tb
= current_tb
;
1038 #endif /* CONFIG_PPC64 */
1040 #ifdef CONFIG_PPC_BOOK3S_64
1041 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1042 if (batch
->active
) {
1043 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1045 __flush_tlb_pending(batch
);
1048 #endif /* CONFIG_PPC_BOOK3S_64 */
1050 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1051 switch_booke_debug_regs(&new->thread
.debug
);
1054 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1057 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1058 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1059 __set_breakpoint(&new->thread
.hw_brk
);
1060 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1064 * We need to save SPRs before treclaim/trecheckpoint as these will
1065 * change a number of them.
1067 save_sprs(&prev
->thread
);
1069 __switch_to_tm(prev
);
1071 /* Save FPU, Altivec, VSX and SPE state */
1075 * We can't take a PMU exception inside _switch() since there is a
1076 * window where the kernel stack SLB and the kernel stack are out
1077 * of sync. Hard disable here.
1081 tm_recheckpoint_new_task(new);
1084 * Call restore_sprs() before calling _switch(). If we move it after
1085 * _switch() then we miss out on calling it for new tasks. The reason
1086 * for this is we manually create a stack frame for new tasks that
1087 * directly returns through ret_from_fork() or
1088 * ret_from_kernel_thread(). See copy_thread() for details.
1090 restore_sprs(old_thread
, new_thread
);
1092 last
= _switch(old_thread
, new_thread
);
1094 #ifdef CONFIG_PPC_BOOK3S_64
1095 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1096 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1097 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1101 if (current_thread_info()->task
->thread
.regs
)
1102 restore_math(current_thread_info()->task
->thread
.regs
);
1104 #endif /* CONFIG_PPC_BOOK3S_64 */
1109 static int instructions_to_print
= 16;
1111 static void show_instructions(struct pt_regs
*regs
)
1114 unsigned long pc
= regs
->nip
- (instructions_to_print
* 3 / 4 *
1117 printk("Instruction dump:");
1119 for (i
= 0; i
< instructions_to_print
; i
++) {
1125 #if !defined(CONFIG_BOOKE)
1126 /* If executing with the IMMU off, adjust pc rather
1127 * than print XXXXXXXX.
1129 if (!(regs
->msr
& MSR_IR
))
1130 pc
= (unsigned long)phys_to_virt(pc
);
1133 if (!__kernel_text_address(pc
) ||
1134 probe_kernel_address((unsigned int __user
*)pc
, instr
)) {
1135 printk(KERN_CONT
"XXXXXXXX ");
1137 if (regs
->nip
== pc
)
1138 printk(KERN_CONT
"<%08x> ", instr
);
1140 printk(KERN_CONT
"%08x ", instr
);
1154 static struct regbit msr_bits
[] = {
1155 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1177 #ifndef CONFIG_BOOKE
1184 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1188 for (; bits
->bit
; ++bits
)
1189 if (val
& bits
->bit
) {
1190 printk("%s%s", s
, bits
->name
);
1195 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1196 static struct regbit msr_tm_bits
[] = {
1203 static void print_tm_bits(unsigned long val
)
1206 * This only prints something if at least one of the TM bit is set.
1207 * Inside the TM[], the output means:
1208 * E: Enabled (bit 32)
1209 * S: Suspended (bit 33)
1210 * T: Transactional (bit 34)
1212 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1214 print_bits(val
, msr_tm_bits
, "");
1219 static void print_tm_bits(unsigned long val
) {}
1222 static void print_msr_bits(unsigned long val
)
1225 print_bits(val
, msr_bits
, ",");
1231 #define REG "%016lx"
1232 #define REGS_PER_LINE 4
1233 #define LAST_VOLATILE 13
1236 #define REGS_PER_LINE 8
1237 #define LAST_VOLATILE 12
1240 void show_regs(struct pt_regs
* regs
)
1244 show_regs_print_info(KERN_DEFAULT
);
1246 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1247 regs
->nip
, regs
->link
, regs
->ctr
);
1248 printk("REGS: %p TRAP: %04lx %s (%s)\n",
1249 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1250 printk("MSR: "REG
" ", regs
->msr
);
1251 print_msr_bits(regs
->msr
);
1252 printk(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1254 if ((regs
->trap
!= 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1255 printk("CFAR: "REG
" ", regs
->orig_gpr3
);
1256 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1257 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1258 printk("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1260 printk("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1263 printk("SOFTE: %ld ", regs
->softe
);
1265 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1266 if (MSR_TM_ACTIVE(regs
->msr
))
1267 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1270 for (i
= 0; i
< 32; i
++) {
1271 if ((i
% REGS_PER_LINE
) == 0)
1272 printk("\nGPR%02d: ", i
);
1273 printk(REG
" ", regs
->gpr
[i
]);
1274 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1278 #ifdef CONFIG_KALLSYMS
1280 * Lookup NIP late so we have the best change of getting the
1281 * above info out without failing
1283 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1284 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1286 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1287 if (!user_mode(regs
))
1288 show_instructions(regs
);
1291 void exit_thread(void)
1295 void flush_thread(void)
1297 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1298 flush_ptrace_hw_breakpoint(current
);
1299 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1300 set_debug_reg_defaults(¤t
->thread
);
1301 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1305 release_thread(struct task_struct
*t
)
1310 * this gets called so that we can store coprocessor state into memory and
1311 * copy the current task into the new thread.
1313 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1315 flush_all_to_thread(src
);
1317 * Flush TM state out so we can copy it. __switch_to_tm() does this
1318 * flush but it removes the checkpointed state from the current CPU and
1319 * transitions the CPU out of TM mode. Hence we need to call
1320 * tm_recheckpoint_new_task() (on the same task) to restore the
1321 * checkpointed state back and the TM mode.
1323 __switch_to_tm(src
);
1324 tm_recheckpoint_new_task(src
);
1328 clear_task_ebb(dst
);
1333 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1335 #ifdef CONFIG_PPC_STD_MMU_64
1336 unsigned long sp_vsid
;
1337 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1339 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1340 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1341 << SLB_VSID_SHIFT_1T
;
1343 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1345 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1346 p
->thread
.ksp_vsid
= sp_vsid
;
1355 * Copy architecture-specific thread state
1357 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1358 unsigned long kthread_arg
, struct task_struct
*p
)
1360 struct pt_regs
*childregs
, *kregs
;
1361 extern void ret_from_fork(void);
1362 extern void ret_from_kernel_thread(void);
1364 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1366 /* Copy registers */
1367 sp
-= sizeof(struct pt_regs
);
1368 childregs
= (struct pt_regs
*) sp
;
1369 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1371 struct thread_info
*ti
= (void *)task_stack_page(p
);
1372 memset(childregs
, 0, sizeof(struct pt_regs
));
1373 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1376 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1378 clear_tsk_thread_flag(p
, TIF_32BIT
);
1379 childregs
->softe
= 1;
1381 childregs
->gpr
[15] = kthread_arg
;
1382 p
->thread
.regs
= NULL
; /* no user register state */
1383 ti
->flags
|= _TIF_RESTOREALL
;
1384 f
= ret_from_kernel_thread
;
1387 struct pt_regs
*regs
= current_pt_regs();
1388 CHECK_FULL_REGS(regs
);
1391 childregs
->gpr
[1] = usp
;
1392 p
->thread
.regs
= childregs
;
1393 childregs
->gpr
[3] = 0; /* Result from fork() */
1394 if (clone_flags
& CLONE_SETTLS
) {
1396 if (!is_32bit_task())
1397 childregs
->gpr
[13] = childregs
->gpr
[6];
1400 childregs
->gpr
[2] = childregs
->gpr
[6];
1405 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1406 sp
-= STACK_FRAME_OVERHEAD
;
1409 * The way this works is that at some point in the future
1410 * some task will call _switch to switch to the new task.
1411 * That will pop off the stack frame created below and start
1412 * the new task running at ret_from_fork. The new task will
1413 * do some house keeping and then return from the fork or clone
1414 * system call, using the stack frame created above.
1416 ((unsigned long *)sp
)[0] = 0;
1417 sp
-= sizeof(struct pt_regs
);
1418 kregs
= (struct pt_regs
*) sp
;
1419 sp
-= STACK_FRAME_OVERHEAD
;
1422 p
->thread
.ksp_limit
= (unsigned long)task_stack_page(p
) +
1423 _ALIGN_UP(sizeof(struct thread_info
), 16);
1425 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1426 p
->thread
.ptrace_bps
[0] = NULL
;
1429 p
->thread
.fp_save_area
= NULL
;
1430 #ifdef CONFIG_ALTIVEC
1431 p
->thread
.vr_save_area
= NULL
;
1434 setup_ksp_vsid(p
, sp
);
1437 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1438 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1439 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1441 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1442 p
->thread
.ppr
= INIT_PPR
;
1444 kregs
->nip
= ppc_function_entry(f
);
1449 * Set up a thread for executing a new program
1451 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1454 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1458 * If we exec out of a kernel thread then thread.regs will not be
1461 if (!current
->thread
.regs
) {
1462 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1463 current
->thread
.regs
= regs
- 1;
1466 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1474 * We have just cleared all the nonvolatile GPRs, so make
1475 * FULL_REGS(regs) return true. This is necessary to allow
1476 * ptrace to examine the thread immediately after exec.
1483 regs
->msr
= MSR_USER
;
1485 if (!is_32bit_task()) {
1486 unsigned long entry
;
1488 if (is_elf2_task()) {
1489 /* Look ma, no function descriptors! */
1494 * The latest iteration of the ABI requires that when
1495 * calling a function (at its global entry point),
1496 * the caller must ensure r12 holds the entry point
1497 * address (so that the function can quickly
1498 * establish addressability).
1500 regs
->gpr
[12] = start
;
1501 /* Make sure that's restored on entry to userspace. */
1502 set_thread_flag(TIF_RESTOREALL
);
1506 /* start is a relocated pointer to the function
1507 * descriptor for the elf _start routine. The first
1508 * entry in the function descriptor is the entry
1509 * address of _start and the second entry is the TOC
1510 * value we need to use.
1512 __get_user(entry
, (unsigned long __user
*)start
);
1513 __get_user(toc
, (unsigned long __user
*)start
+1);
1515 /* Check whether the e_entry function descriptor entries
1516 * need to be relocated before we can use them.
1518 if (load_addr
!= 0) {
1525 regs
->msr
= MSR_USER64
;
1529 regs
->msr
= MSR_USER32
;
1533 current
->thread
.used_vsr
= 0;
1535 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1536 current
->thread
.fp_save_area
= NULL
;
1537 #ifdef CONFIG_ALTIVEC
1538 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1539 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1540 current
->thread
.vr_save_area
= NULL
;
1541 current
->thread
.vrsave
= 0;
1542 current
->thread
.used_vr
= 0;
1543 #endif /* CONFIG_ALTIVEC */
1545 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1546 current
->thread
.acc
= 0;
1547 current
->thread
.spefscr
= 0;
1548 current
->thread
.used_spe
= 0;
1549 #endif /* CONFIG_SPE */
1550 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1551 if (cpu_has_feature(CPU_FTR_TM
))
1552 regs
->msr
|= MSR_TM
;
1553 current
->thread
.tm_tfhar
= 0;
1554 current
->thread
.tm_texasr
= 0;
1555 current
->thread
.tm_tfiar
= 0;
1556 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1558 EXPORT_SYMBOL(start_thread
);
1560 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1561 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1563 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1565 struct pt_regs
*regs
= tsk
->thread
.regs
;
1567 /* This is a bit hairy. If we are an SPE enabled processor
1568 * (have embedded fp) we store the IEEE exception enable flags in
1569 * fpexc_mode. fpexc_mode is also used for setting FP exception
1570 * mode (asyn, precise, disabled) for 'Classic' FP. */
1571 if (val
& PR_FP_EXC_SW_ENABLE
) {
1573 if (cpu_has_feature(CPU_FTR_SPE
)) {
1575 * When the sticky exception bits are set
1576 * directly by userspace, it must call prctl
1577 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1578 * in the existing prctl settings) or
1579 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1580 * the bits being set). <fenv.h> functions
1581 * saving and restoring the whole
1582 * floating-point environment need to do so
1583 * anyway to restore the prctl settings from
1584 * the saved environment.
1586 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1587 tsk
->thread
.fpexc_mode
= val
&
1588 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1598 /* on a CONFIG_SPE this does not hurt us. The bits that
1599 * __pack_fe01 use do not overlap with bits used for
1600 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1601 * on CONFIG_SPE implementations are reserved so writing to
1602 * them does not change anything */
1603 if (val
> PR_FP_EXC_PRECISE
)
1605 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1606 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1607 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1608 | tsk
->thread
.fpexc_mode
;
1612 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1616 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1618 if (cpu_has_feature(CPU_FTR_SPE
)) {
1620 * When the sticky exception bits are set
1621 * directly by userspace, it must call prctl
1622 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1623 * in the existing prctl settings) or
1624 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1625 * the bits being set). <fenv.h> functions
1626 * saving and restoring the whole
1627 * floating-point environment need to do so
1628 * anyway to restore the prctl settings from
1629 * the saved environment.
1631 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1632 val
= tsk
->thread
.fpexc_mode
;
1639 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1640 return put_user(val
, (unsigned int __user
*) adr
);
1643 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1645 struct pt_regs
*regs
= tsk
->thread
.regs
;
1647 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1648 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1654 if (val
== PR_ENDIAN_BIG
)
1655 regs
->msr
&= ~MSR_LE
;
1656 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1657 regs
->msr
|= MSR_LE
;
1664 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1666 struct pt_regs
*regs
= tsk
->thread
.regs
;
1669 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1670 !cpu_has_feature(CPU_FTR_REAL_LE
))
1676 if (regs
->msr
& MSR_LE
) {
1677 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1678 val
= PR_ENDIAN_LITTLE
;
1680 val
= PR_ENDIAN_PPC_LITTLE
;
1682 val
= PR_ENDIAN_BIG
;
1684 return put_user(val
, (unsigned int __user
*)adr
);
1687 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1689 tsk
->thread
.align_ctl
= val
;
1693 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1695 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1698 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1699 unsigned long nbytes
)
1701 unsigned long stack_page
;
1702 unsigned long cpu
= task_cpu(p
);
1705 * Avoid crashing if the stack has overflowed and corrupted
1706 * task_cpu(p), which is in the thread_info struct.
1708 if (cpu
< NR_CPUS
&& cpu_possible(cpu
)) {
1709 stack_page
= (unsigned long) hardirq_ctx
[cpu
];
1710 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1711 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1714 stack_page
= (unsigned long) softirq_ctx
[cpu
];
1715 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1716 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1722 int validate_sp(unsigned long sp
, struct task_struct
*p
,
1723 unsigned long nbytes
)
1725 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
1727 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1728 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1731 return valid_irq_stack(sp
, p
, nbytes
);
1734 EXPORT_SYMBOL(validate_sp
);
1736 unsigned long get_wchan(struct task_struct
*p
)
1738 unsigned long ip
, sp
;
1741 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
1745 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1749 sp
= *(unsigned long *)sp
;
1750 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1753 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
1754 if (!in_sched_functions(ip
))
1757 } while (count
++ < 16);
1761 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
1763 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
1765 unsigned long sp
, ip
, lr
, newsp
;
1768 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1769 int curr_frame
= current
->curr_ret_stack
;
1770 extern void return_to_handler(void);
1771 unsigned long rth
= (unsigned long)return_to_handler
;
1774 sp
= (unsigned long) stack
;
1779 sp
= current_stack_pointer();
1781 sp
= tsk
->thread
.ksp
;
1785 printk("Call Trace:\n");
1787 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
1790 stack
= (unsigned long *) sp
;
1792 ip
= stack
[STACK_FRAME_LR_SAVE
];
1793 if (!firstframe
|| ip
!= lr
) {
1794 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
1795 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1796 if ((ip
== rth
) && curr_frame
>= 0) {
1798 (void *)current
->ret_stack
[curr_frame
].ret
);
1803 printk(" (unreliable)");
1809 * See if this is an exception frame.
1810 * We look for the "regshere" marker in the current frame.
1812 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
1813 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
1814 struct pt_regs
*regs
= (struct pt_regs
*)
1815 (sp
+ STACK_FRAME_OVERHEAD
);
1817 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
1818 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
1823 } while (count
++ < kstack_depth_to_print
);
1827 /* Called with hard IRQs off */
1828 void notrace
__ppc64_runlatch_on(void)
1830 struct thread_info
*ti
= current_thread_info();
1833 ctrl
= mfspr(SPRN_CTRLF
);
1834 ctrl
|= CTRL_RUNLATCH
;
1835 mtspr(SPRN_CTRLT
, ctrl
);
1837 ti
->local_flags
|= _TLF_RUNLATCH
;
1840 /* Called with hard IRQs off */
1841 void notrace
__ppc64_runlatch_off(void)
1843 struct thread_info
*ti
= current_thread_info();
1846 ti
->local_flags
&= ~_TLF_RUNLATCH
;
1848 ctrl
= mfspr(SPRN_CTRLF
);
1849 ctrl
&= ~CTRL_RUNLATCH
;
1850 mtspr(SPRN_CTRLT
, ctrl
);
1852 #endif /* CONFIG_PPC64 */
1854 unsigned long arch_align_stack(unsigned long sp
)
1856 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
1857 sp
-= get_random_int() & ~PAGE_MASK
;
1861 static inline unsigned long brk_rnd(void)
1863 unsigned long rnd
= 0;
1865 /* 8MB for 32bit, 1GB for 64bit */
1866 if (is_32bit_task())
1867 rnd
= (long)(get_random_int() % (1<<(23-PAGE_SHIFT
)));
1869 rnd
= (long)(get_random_int() % (1<<(30-PAGE_SHIFT
)));
1871 return rnd
<< PAGE_SHIFT
;
1874 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
1876 unsigned long base
= mm
->brk
;
1879 #ifdef CONFIG_PPC_STD_MMU_64
1881 * If we are using 1TB segments and we are allowed to randomise
1882 * the heap, we can put it above 1TB so it is backed by a 1TB
1883 * segment. Otherwise the heap will be in the bottom 1TB
1884 * which always uses 256MB segments and this may result in a
1885 * performance penalty.
1887 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
1888 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
1891 ret
= PAGE_ALIGN(base
+ brk_rnd());