3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
11 * and Paul Mackerras (paulus@samba.org).
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
21 #include <linux/smp.h>
22 #include <linux/errno.h>
23 #include <linux/ptrace.h>
24 #include <linux/regset.h>
25 #include <linux/tracehook.h>
26 #include <linux/elf.h>
27 #include <linux/user.h>
28 #include <linux/security.h>
29 #include <linux/signal.h>
30 #include <linux/seccomp.h>
31 #include <linux/audit.h>
32 #include <trace/syscall.h>
33 #include <linux/hw_breakpoint.h>
34 #include <linux/perf_event.h>
35 #include <linux/context_tracking.h>
37 #include <linux/uaccess.h>
39 #include <asm/pgtable.h>
40 #include <asm/switch_to.h>
42 #include <asm/asm-prototypes.h>
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/syscalls.h>
48 * The parameter save area on the stack is used to store arguments being passed
49 * to callee function and is located at fixed offset from stack pointer.
52 #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
53 #else /* CONFIG_PPC32 */
54 #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
57 struct pt_regs_offset
{
62 #define STR(s) #s /* convert to string */
63 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
64 #define GPR_OFFSET_NAME(num) \
65 {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \
66 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
67 #define REG_OFFSET_END {.name = NULL, .offset = 0}
69 #define TVSO(f) (offsetof(struct thread_vr_state, f))
70 #define TFSO(f) (offsetof(struct thread_fp_state, f))
71 #define TSO(f) (offsetof(struct thread_struct, f))
73 static const struct pt_regs_offset regoffset_table
[] = {
106 REG_OFFSET_NAME(nip
),
107 REG_OFFSET_NAME(msr
),
108 REG_OFFSET_NAME(ctr
),
109 REG_OFFSET_NAME(link
),
110 REG_OFFSET_NAME(xer
),
111 REG_OFFSET_NAME(ccr
),
113 REG_OFFSET_NAME(softe
),
117 REG_OFFSET_NAME(trap
),
118 REG_OFFSET_NAME(dar
),
119 REG_OFFSET_NAME(dsisr
),
123 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
124 static void flush_tmregs_to_thread(struct task_struct
*tsk
)
127 * If task is not current, it will have been flushed already to
128 * it's thread_struct during __switch_to().
130 * A reclaim flushes ALL the state.
133 if (tsk
== current
&& MSR_TM_SUSPENDED(mfmsr()))
134 tm_reclaim_current(TM_CAUSE_SIGNAL
);
138 static inline void flush_tmregs_to_thread(struct task_struct
*tsk
) { }
142 * regs_query_register_offset() - query register offset from its name
143 * @name: the name of a register
145 * regs_query_register_offset() returns the offset of a register in struct
146 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
148 int regs_query_register_offset(const char *name
)
150 const struct pt_regs_offset
*roff
;
151 for (roff
= regoffset_table
; roff
->name
!= NULL
; roff
++)
152 if (!strcmp(roff
->name
, name
))
158 * regs_query_register_name() - query register name from its offset
159 * @offset: the offset of a register in struct pt_regs.
161 * regs_query_register_name() returns the name of a register from its
162 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
164 const char *regs_query_register_name(unsigned int offset
)
166 const struct pt_regs_offset
*roff
;
167 for (roff
= regoffset_table
; roff
->name
!= NULL
; roff
++)
168 if (roff
->offset
== offset
)
174 * does not yet catch signals sent when the child dies.
175 * in exit.c or in signal.c.
179 * Set of msr bits that gdb can change on behalf of a process.
181 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
182 #define MSR_DEBUGCHANGE 0
184 #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
188 * Max register writeable via put_reg
191 #define PT_MAX_PUT_REG PT_MQ
193 #define PT_MAX_PUT_REG PT_CCR
196 static unsigned long get_user_msr(struct task_struct
*task
)
198 return task
->thread
.regs
->msr
| task
->thread
.fpexc_mode
;
201 static int set_user_msr(struct task_struct
*task
, unsigned long msr
)
203 task
->thread
.regs
->msr
&= ~MSR_DEBUGCHANGE
;
204 task
->thread
.regs
->msr
|= msr
& MSR_DEBUGCHANGE
;
208 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
209 static unsigned long get_user_ckpt_msr(struct task_struct
*task
)
211 return task
->thread
.ckpt_regs
.msr
| task
->thread
.fpexc_mode
;
214 static int set_user_ckpt_msr(struct task_struct
*task
, unsigned long msr
)
216 task
->thread
.ckpt_regs
.msr
&= ~MSR_DEBUGCHANGE
;
217 task
->thread
.ckpt_regs
.msr
|= msr
& MSR_DEBUGCHANGE
;
221 static int set_user_ckpt_trap(struct task_struct
*task
, unsigned long trap
)
223 task
->thread
.ckpt_regs
.trap
= trap
& 0xfff0;
229 static int get_user_dscr(struct task_struct
*task
, unsigned long *data
)
231 *data
= task
->thread
.dscr
;
235 static int set_user_dscr(struct task_struct
*task
, unsigned long dscr
)
237 task
->thread
.dscr
= dscr
;
238 task
->thread
.dscr_inherit
= 1;
242 static int get_user_dscr(struct task_struct
*task
, unsigned long *data
)
247 static int set_user_dscr(struct task_struct
*task
, unsigned long dscr
)
254 * We prevent mucking around with the reserved area of trap
255 * which are used internally by the kernel.
257 static int set_user_trap(struct task_struct
*task
, unsigned long trap
)
259 task
->thread
.regs
->trap
= trap
& 0xfff0;
264 * Get contents of register REGNO in task TASK.
266 int ptrace_get_reg(struct task_struct
*task
, int regno
, unsigned long *data
)
268 if ((task
->thread
.regs
== NULL
) || !data
)
271 if (regno
== PT_MSR
) {
272 *data
= get_user_msr(task
);
276 if (regno
== PT_DSCR
)
277 return get_user_dscr(task
, data
);
279 if (regno
< (sizeof(struct pt_regs
) / sizeof(unsigned long))) {
280 *data
= ((unsigned long *)task
->thread
.regs
)[regno
];
288 * Write contents of register REGNO in task TASK.
290 int ptrace_put_reg(struct task_struct
*task
, int regno
, unsigned long data
)
292 if (task
->thread
.regs
== NULL
)
296 return set_user_msr(task
, data
);
297 if (regno
== PT_TRAP
)
298 return set_user_trap(task
, data
);
299 if (regno
== PT_DSCR
)
300 return set_user_dscr(task
, data
);
302 if (regno
<= PT_MAX_PUT_REG
) {
303 ((unsigned long *)task
->thread
.regs
)[regno
] = data
;
309 static int gpr_get(struct task_struct
*target
, const struct user_regset
*regset
,
310 unsigned int pos
, unsigned int count
,
311 void *kbuf
, void __user
*ubuf
)
315 if (target
->thread
.regs
== NULL
)
318 if (!FULL_REGS(target
->thread
.regs
)) {
319 /* We have a partial register set. Fill 14-31 with bogus values */
320 for (i
= 14; i
< 32; i
++)
321 target
->thread
.regs
->gpr
[i
] = NV_REG_POISON
;
324 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
326 0, offsetof(struct pt_regs
, msr
));
328 unsigned long msr
= get_user_msr(target
);
329 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, &msr
,
330 offsetof(struct pt_regs
, msr
),
331 offsetof(struct pt_regs
, msr
) +
335 BUILD_BUG_ON(offsetof(struct pt_regs
, orig_gpr3
) !=
336 offsetof(struct pt_regs
, msr
) + sizeof(long));
339 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
340 &target
->thread
.regs
->orig_gpr3
,
341 offsetof(struct pt_regs
, orig_gpr3
),
342 sizeof(struct pt_regs
));
344 ret
= user_regset_copyout_zero(&pos
, &count
, &kbuf
, &ubuf
,
345 sizeof(struct pt_regs
), -1);
350 static int gpr_set(struct task_struct
*target
, const struct user_regset
*regset
,
351 unsigned int pos
, unsigned int count
,
352 const void *kbuf
, const void __user
*ubuf
)
357 if (target
->thread
.regs
== NULL
)
360 CHECK_FULL_REGS(target
->thread
.regs
);
362 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
364 0, PT_MSR
* sizeof(reg
));
366 if (!ret
&& count
> 0) {
367 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, ®
,
368 PT_MSR
* sizeof(reg
),
369 (PT_MSR
+ 1) * sizeof(reg
));
371 ret
= set_user_msr(target
, reg
);
374 BUILD_BUG_ON(offsetof(struct pt_regs
, orig_gpr3
) !=
375 offsetof(struct pt_regs
, msr
) + sizeof(long));
378 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
379 &target
->thread
.regs
->orig_gpr3
,
380 PT_ORIG_R3
* sizeof(reg
),
381 (PT_MAX_PUT_REG
+ 1) * sizeof(reg
));
383 if (PT_MAX_PUT_REG
+ 1 < PT_TRAP
&& !ret
)
384 ret
= user_regset_copyin_ignore(
385 &pos
, &count
, &kbuf
, &ubuf
,
386 (PT_MAX_PUT_REG
+ 1) * sizeof(reg
),
387 PT_TRAP
* sizeof(reg
));
389 if (!ret
&& count
> 0) {
390 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, ®
,
391 PT_TRAP
* sizeof(reg
),
392 (PT_TRAP
+ 1) * sizeof(reg
));
394 ret
= set_user_trap(target
, reg
);
398 ret
= user_regset_copyin_ignore(
399 &pos
, &count
, &kbuf
, &ubuf
,
400 (PT_TRAP
+ 1) * sizeof(reg
), -1);
406 * Regardless of transactions, 'fp_state' holds the current running
407 * value of all FPR registers and 'ckfp_state' holds the last checkpointed
408 * value of all FPR registers for the current transaction.
410 * Userspace interface buffer layout:
417 static int fpr_get(struct task_struct
*target
, const struct user_regset
*regset
,
418 unsigned int pos
, unsigned int count
,
419 void *kbuf
, void __user
*ubuf
)
425 flush_fp_to_thread(target
);
427 /* copy to local buffer then write that out */
428 for (i
= 0; i
< 32 ; i
++)
429 buf
[i
] = target
->thread
.TS_FPR(i
);
430 buf
[32] = target
->thread
.fp_state
.fpscr
;
431 return user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, buf
, 0, -1);
433 BUILD_BUG_ON(offsetof(struct thread_fp_state
, fpscr
) !=
434 offsetof(struct thread_fp_state
, fpr
[32]));
436 flush_fp_to_thread(target
);
438 return user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
439 &target
->thread
.fp_state
, 0, -1);
444 * Regardless of transactions, 'fp_state' holds the current running
445 * value of all FPR registers and 'ckfp_state' holds the last checkpointed
446 * value of all FPR registers for the current transaction.
448 * Userspace interface buffer layout:
456 static int fpr_set(struct task_struct
*target
, const struct user_regset
*regset
,
457 unsigned int pos
, unsigned int count
,
458 const void *kbuf
, const void __user
*ubuf
)
464 flush_fp_to_thread(target
);
466 for (i
= 0; i
< 32 ; i
++)
467 buf
[i
] = target
->thread
.TS_FPR(i
);
468 buf
[32] = target
->thread
.fp_state
.fpscr
;
470 /* copy to local buffer then write that out */
471 i
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, buf
, 0, -1);
475 for (i
= 0; i
< 32 ; i
++)
476 target
->thread
.TS_FPR(i
) = buf
[i
];
477 target
->thread
.fp_state
.fpscr
= buf
[32];
480 BUILD_BUG_ON(offsetof(struct thread_fp_state
, fpscr
) !=
481 offsetof(struct thread_fp_state
, fpr
[32]));
483 flush_fp_to_thread(target
);
485 return user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
486 &target
->thread
.fp_state
, 0, -1);
490 #ifdef CONFIG_ALTIVEC
492 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
493 * The transfer totals 34 quadword. Quadwords 0-31 contain the
494 * corresponding vector registers. Quadword 32 contains the vscr as the
495 * last word (offset 12) within that quadword. Quadword 33 contains the
496 * vrsave as the first word (offset 0) within the quadword.
498 * This definition of the VMX state is compatible with the current PPC32
499 * ptrace interface. This allows signal handling and ptrace to use the
500 * same structures. This also simplifies the implementation of a bi-arch
501 * (combined (32- and 64-bit) gdb.
504 static int vr_active(struct task_struct
*target
,
505 const struct user_regset
*regset
)
507 flush_altivec_to_thread(target
);
508 return target
->thread
.used_vr
? regset
->n
: 0;
512 * Regardless of transactions, 'vr_state' holds the current running
513 * value of all the VMX registers and 'ckvr_state' holds the last
514 * checkpointed value of all the VMX registers for the current
515 * transaction to fall back on in case it aborts.
517 * Userspace interface buffer layout:
525 static int vr_get(struct task_struct
*target
, const struct user_regset
*regset
,
526 unsigned int pos
, unsigned int count
,
527 void *kbuf
, void __user
*ubuf
)
531 flush_altivec_to_thread(target
);
533 BUILD_BUG_ON(offsetof(struct thread_vr_state
, vscr
) !=
534 offsetof(struct thread_vr_state
, vr
[32]));
536 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
537 &target
->thread
.vr_state
, 0,
538 33 * sizeof(vector128
));
541 * Copy out only the low-order word of vrsave.
547 memset(&vrsave
, 0, sizeof(vrsave
));
549 vrsave
.word
= target
->thread
.vrsave
;
551 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, &vrsave
,
552 33 * sizeof(vector128
), -1);
559 * Regardless of transactions, 'vr_state' holds the current running
560 * value of all the VMX registers and 'ckvr_state' holds the last
561 * checkpointed value of all the VMX registers for the current
562 * transaction to fall back on in case it aborts.
564 * Userspace interface buffer layout:
572 static int vr_set(struct task_struct
*target
, const struct user_regset
*regset
,
573 unsigned int pos
, unsigned int count
,
574 const void *kbuf
, const void __user
*ubuf
)
578 flush_altivec_to_thread(target
);
580 BUILD_BUG_ON(offsetof(struct thread_vr_state
, vscr
) !=
581 offsetof(struct thread_vr_state
, vr
[32]));
583 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
584 &target
->thread
.vr_state
, 0,
585 33 * sizeof(vector128
));
586 if (!ret
&& count
> 0) {
588 * We use only the first word of vrsave.
594 memset(&vrsave
, 0, sizeof(vrsave
));
596 vrsave
.word
= target
->thread
.vrsave
;
598 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, &vrsave
,
599 33 * sizeof(vector128
), -1);
601 target
->thread
.vrsave
= vrsave
.word
;
606 #endif /* CONFIG_ALTIVEC */
610 * Currently to set and and get all the vsx state, you need to call
611 * the fp and VMX calls as well. This only get/sets the lower 32
612 * 128bit VSX registers.
615 static int vsr_active(struct task_struct
*target
,
616 const struct user_regset
*regset
)
618 flush_vsx_to_thread(target
);
619 return target
->thread
.used_vsr
? regset
->n
: 0;
623 * Regardless of transactions, 'fp_state' holds the current running
624 * value of all FPR registers and 'ckfp_state' holds the last
625 * checkpointed value of all FPR registers for the current
628 * Userspace interface buffer layout:
634 static int vsr_get(struct task_struct
*target
, const struct user_regset
*regset
,
635 unsigned int pos
, unsigned int count
,
636 void *kbuf
, void __user
*ubuf
)
641 flush_tmregs_to_thread(target
);
642 flush_fp_to_thread(target
);
643 flush_altivec_to_thread(target
);
644 flush_vsx_to_thread(target
);
646 for (i
= 0; i
< 32 ; i
++)
647 buf
[i
] = target
->thread
.fp_state
.fpr
[i
][TS_VSRLOWOFFSET
];
649 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
650 buf
, 0, 32 * sizeof(double));
656 * Regardless of transactions, 'fp_state' holds the current running
657 * value of all FPR registers and 'ckfp_state' holds the last
658 * checkpointed value of all FPR registers for the current
661 * Userspace interface buffer layout:
667 static int vsr_set(struct task_struct
*target
, const struct user_regset
*regset
,
668 unsigned int pos
, unsigned int count
,
669 const void *kbuf
, const void __user
*ubuf
)
674 flush_tmregs_to_thread(target
);
675 flush_fp_to_thread(target
);
676 flush_altivec_to_thread(target
);
677 flush_vsx_to_thread(target
);
679 for (i
= 0; i
< 32 ; i
++)
680 buf
[i
] = target
->thread
.fp_state
.fpr
[i
][TS_VSRLOWOFFSET
];
682 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
683 buf
, 0, 32 * sizeof(double));
685 for (i
= 0; i
< 32 ; i
++)
686 target
->thread
.fp_state
.fpr
[i
][TS_VSRLOWOFFSET
] = buf
[i
];
690 #endif /* CONFIG_VSX */
695 * For get_evrregs/set_evrregs functions 'data' has the following layout:
704 static int evr_active(struct task_struct
*target
,
705 const struct user_regset
*regset
)
707 flush_spe_to_thread(target
);
708 return target
->thread
.used_spe
? regset
->n
: 0;
711 static int evr_get(struct task_struct
*target
, const struct user_regset
*regset
,
712 unsigned int pos
, unsigned int count
,
713 void *kbuf
, void __user
*ubuf
)
717 flush_spe_to_thread(target
);
719 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
721 0, sizeof(target
->thread
.evr
));
723 BUILD_BUG_ON(offsetof(struct thread_struct
, acc
) + sizeof(u64
) !=
724 offsetof(struct thread_struct
, spefscr
));
727 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
729 sizeof(target
->thread
.evr
), -1);
734 static int evr_set(struct task_struct
*target
, const struct user_regset
*regset
,
735 unsigned int pos
, unsigned int count
,
736 const void *kbuf
, const void __user
*ubuf
)
740 flush_spe_to_thread(target
);
742 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
744 0, sizeof(target
->thread
.evr
));
746 BUILD_BUG_ON(offsetof(struct thread_struct
, acc
) + sizeof(u64
) !=
747 offsetof(struct thread_struct
, spefscr
));
750 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
752 sizeof(target
->thread
.evr
), -1);
756 #endif /* CONFIG_SPE */
758 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
760 * tm_cgpr_active - get active number of registers in CGPR
761 * @target: The target task.
762 * @regset: The user regset structure.
764 * This function checks for the active number of available
765 * regisers in transaction checkpointed GPR category.
767 static int tm_cgpr_active(struct task_struct
*target
,
768 const struct user_regset
*regset
)
770 if (!cpu_has_feature(CPU_FTR_TM
))
773 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
780 * tm_cgpr_get - get CGPR registers
781 * @target: The target task.
782 * @regset: The user regset structure.
783 * @pos: The buffer position.
784 * @count: Number of bytes to copy.
785 * @kbuf: Kernel buffer to copy from.
786 * @ubuf: User buffer to copy into.
788 * This function gets transaction checkpointed GPR registers.
790 * When the transaction is active, 'ckpt_regs' holds all the checkpointed
791 * GPR register values for the current transaction to fall back on if it
792 * aborts in between. This function gets those checkpointed GPR registers.
793 * The userspace interface buffer layout is as follows.
796 * struct pt_regs ckpt_regs;
799 static int tm_cgpr_get(struct task_struct
*target
,
800 const struct user_regset
*regset
,
801 unsigned int pos
, unsigned int count
,
802 void *kbuf
, void __user
*ubuf
)
806 if (!cpu_has_feature(CPU_FTR_TM
))
809 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
812 flush_tmregs_to_thread(target
);
813 flush_fp_to_thread(target
);
814 flush_altivec_to_thread(target
);
816 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
817 &target
->thread
.ckpt_regs
,
818 0, offsetof(struct pt_regs
, msr
));
820 unsigned long msr
= get_user_ckpt_msr(target
);
822 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, &msr
,
823 offsetof(struct pt_regs
, msr
),
824 offsetof(struct pt_regs
, msr
) +
828 BUILD_BUG_ON(offsetof(struct pt_regs
, orig_gpr3
) !=
829 offsetof(struct pt_regs
, msr
) + sizeof(long));
832 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
833 &target
->thread
.ckpt_regs
.orig_gpr3
,
834 offsetof(struct pt_regs
, orig_gpr3
),
835 sizeof(struct pt_regs
));
837 ret
= user_regset_copyout_zero(&pos
, &count
, &kbuf
, &ubuf
,
838 sizeof(struct pt_regs
), -1);
844 * tm_cgpr_set - set the CGPR registers
845 * @target: The target task.
846 * @regset: The user regset structure.
847 * @pos: The buffer position.
848 * @count: Number of bytes to copy.
849 * @kbuf: Kernel buffer to copy into.
850 * @ubuf: User buffer to copy from.
852 * This function sets in transaction checkpointed GPR registers.
854 * When the transaction is active, 'ckpt_regs' holds the checkpointed
855 * GPR register values for the current transaction to fall back on if it
856 * aborts in between. This function sets those checkpointed GPR registers.
857 * The userspace interface buffer layout is as follows.
860 * struct pt_regs ckpt_regs;
863 static int tm_cgpr_set(struct task_struct
*target
,
864 const struct user_regset
*regset
,
865 unsigned int pos
, unsigned int count
,
866 const void *kbuf
, const void __user
*ubuf
)
871 if (!cpu_has_feature(CPU_FTR_TM
))
874 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
877 flush_tmregs_to_thread(target
);
878 flush_fp_to_thread(target
);
879 flush_altivec_to_thread(target
);
881 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
882 &target
->thread
.ckpt_regs
,
883 0, PT_MSR
* sizeof(reg
));
885 if (!ret
&& count
> 0) {
886 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, ®
,
887 PT_MSR
* sizeof(reg
),
888 (PT_MSR
+ 1) * sizeof(reg
));
890 ret
= set_user_ckpt_msr(target
, reg
);
893 BUILD_BUG_ON(offsetof(struct pt_regs
, orig_gpr3
) !=
894 offsetof(struct pt_regs
, msr
) + sizeof(long));
897 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
898 &target
->thread
.ckpt_regs
.orig_gpr3
,
899 PT_ORIG_R3
* sizeof(reg
),
900 (PT_MAX_PUT_REG
+ 1) * sizeof(reg
));
902 if (PT_MAX_PUT_REG
+ 1 < PT_TRAP
&& !ret
)
903 ret
= user_regset_copyin_ignore(
904 &pos
, &count
, &kbuf
, &ubuf
,
905 (PT_MAX_PUT_REG
+ 1) * sizeof(reg
),
906 PT_TRAP
* sizeof(reg
));
908 if (!ret
&& count
> 0) {
909 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, ®
,
910 PT_TRAP
* sizeof(reg
),
911 (PT_TRAP
+ 1) * sizeof(reg
));
913 ret
= set_user_ckpt_trap(target
, reg
);
917 ret
= user_regset_copyin_ignore(
918 &pos
, &count
, &kbuf
, &ubuf
,
919 (PT_TRAP
+ 1) * sizeof(reg
), -1);
925 * tm_cfpr_active - get active number of registers in CFPR
926 * @target: The target task.
927 * @regset: The user regset structure.
929 * This function checks for the active number of available
930 * regisers in transaction checkpointed FPR category.
932 static int tm_cfpr_active(struct task_struct
*target
,
933 const struct user_regset
*regset
)
935 if (!cpu_has_feature(CPU_FTR_TM
))
938 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
945 * tm_cfpr_get - get CFPR registers
946 * @target: The target task.
947 * @regset: The user regset structure.
948 * @pos: The buffer position.
949 * @count: Number of bytes to copy.
950 * @kbuf: Kernel buffer to copy from.
951 * @ubuf: User buffer to copy into.
953 * This function gets in transaction checkpointed FPR registers.
955 * When the transaction is active 'ckfp_state' holds the checkpointed
956 * values for the current transaction to fall back on if it aborts
957 * in between. This function gets those checkpointed FPR registers.
958 * The userspace interface buffer layout is as follows.
965 static int tm_cfpr_get(struct task_struct
*target
,
966 const struct user_regset
*regset
,
967 unsigned int pos
, unsigned int count
,
968 void *kbuf
, void __user
*ubuf
)
973 if (!cpu_has_feature(CPU_FTR_TM
))
976 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
979 flush_tmregs_to_thread(target
);
980 flush_fp_to_thread(target
);
981 flush_altivec_to_thread(target
);
983 /* copy to local buffer then write that out */
984 for (i
= 0; i
< 32 ; i
++)
985 buf
[i
] = target
->thread
.TS_CKFPR(i
);
986 buf
[32] = target
->thread
.ckfp_state
.fpscr
;
987 return user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, buf
, 0, -1);
991 * tm_cfpr_set - set CFPR registers
992 * @target: The target task.
993 * @regset: The user regset structure.
994 * @pos: The buffer position.
995 * @count: Number of bytes to copy.
996 * @kbuf: Kernel buffer to copy into.
997 * @ubuf: User buffer to copy from.
999 * This function sets in transaction checkpointed FPR registers.
1001 * When the transaction is active 'ckfp_state' holds the checkpointed
1002 * FPR register values for the current transaction to fall back on
1003 * if it aborts in between. This function sets these checkpointed
1004 * FPR registers. The userspace interface buffer layout is as follows.
1011 static int tm_cfpr_set(struct task_struct
*target
,
1012 const struct user_regset
*regset
,
1013 unsigned int pos
, unsigned int count
,
1014 const void *kbuf
, const void __user
*ubuf
)
1019 if (!cpu_has_feature(CPU_FTR_TM
))
1022 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1025 flush_tmregs_to_thread(target
);
1026 flush_fp_to_thread(target
);
1027 flush_altivec_to_thread(target
);
1029 for (i
= 0; i
< 32; i
++)
1030 buf
[i
] = target
->thread
.TS_CKFPR(i
);
1031 buf
[32] = target
->thread
.ckfp_state
.fpscr
;
1033 /* copy to local buffer then write that out */
1034 i
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, buf
, 0, -1);
1037 for (i
= 0; i
< 32 ; i
++)
1038 target
->thread
.TS_CKFPR(i
) = buf
[i
];
1039 target
->thread
.ckfp_state
.fpscr
= buf
[32];
1044 * tm_cvmx_active - get active number of registers in CVMX
1045 * @target: The target task.
1046 * @regset: The user regset structure.
1048 * This function checks for the active number of available
1049 * regisers in checkpointed VMX category.
1051 static int tm_cvmx_active(struct task_struct
*target
,
1052 const struct user_regset
*regset
)
1054 if (!cpu_has_feature(CPU_FTR_TM
))
1057 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1064 * tm_cvmx_get - get CMVX registers
1065 * @target: The target task.
1066 * @regset: The user regset structure.
1067 * @pos: The buffer position.
1068 * @count: Number of bytes to copy.
1069 * @kbuf: Kernel buffer to copy from.
1070 * @ubuf: User buffer to copy into.
1072 * This function gets in transaction checkpointed VMX registers.
1074 * When the transaction is active 'ckvr_state' and 'ckvrsave' hold
1075 * the checkpointed values for the current transaction to fall
1076 * back on if it aborts in between. The userspace interface buffer
1077 * layout is as follows.
1085 static int tm_cvmx_get(struct task_struct
*target
,
1086 const struct user_regset
*regset
,
1087 unsigned int pos
, unsigned int count
,
1088 void *kbuf
, void __user
*ubuf
)
1092 BUILD_BUG_ON(TVSO(vscr
) != TVSO(vr
[32]));
1094 if (!cpu_has_feature(CPU_FTR_TM
))
1097 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1100 /* Flush the state */
1101 flush_tmregs_to_thread(target
);
1102 flush_fp_to_thread(target
);
1103 flush_altivec_to_thread(target
);
1105 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1106 &target
->thread
.ckvr_state
, 0,
1107 33 * sizeof(vector128
));
1110 * Copy out only the low-order word of vrsave.
1116 memset(&vrsave
, 0, sizeof(vrsave
));
1117 vrsave
.word
= target
->thread
.ckvrsave
;
1118 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, &vrsave
,
1119 33 * sizeof(vector128
), -1);
1126 * tm_cvmx_set - set CMVX registers
1127 * @target: The target task.
1128 * @regset: The user regset structure.
1129 * @pos: The buffer position.
1130 * @count: Number of bytes to copy.
1131 * @kbuf: Kernel buffer to copy into.
1132 * @ubuf: User buffer to copy from.
1134 * This function sets in transaction checkpointed VMX registers.
1136 * When the transaction is active 'ckvr_state' and 'ckvrsave' hold
1137 * the checkpointed values for the current transaction to fall
1138 * back on if it aborts in between. The userspace interface buffer
1139 * layout is as follows.
1147 static int tm_cvmx_set(struct task_struct
*target
,
1148 const struct user_regset
*regset
,
1149 unsigned int pos
, unsigned int count
,
1150 const void *kbuf
, const void __user
*ubuf
)
1154 BUILD_BUG_ON(TVSO(vscr
) != TVSO(vr
[32]));
1156 if (!cpu_has_feature(CPU_FTR_TM
))
1159 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1162 flush_tmregs_to_thread(target
);
1163 flush_fp_to_thread(target
);
1164 flush_altivec_to_thread(target
);
1166 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1167 &target
->thread
.ckvr_state
, 0,
1168 33 * sizeof(vector128
));
1169 if (!ret
&& count
> 0) {
1171 * We use only the low-order word of vrsave.
1177 memset(&vrsave
, 0, sizeof(vrsave
));
1178 vrsave
.word
= target
->thread
.ckvrsave
;
1179 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, &vrsave
,
1180 33 * sizeof(vector128
), -1);
1182 target
->thread
.ckvrsave
= vrsave
.word
;
1189 * tm_cvsx_active - get active number of registers in CVSX
1190 * @target: The target task.
1191 * @regset: The user regset structure.
1193 * This function checks for the active number of available
1194 * regisers in transaction checkpointed VSX category.
1196 static int tm_cvsx_active(struct task_struct
*target
,
1197 const struct user_regset
*regset
)
1199 if (!cpu_has_feature(CPU_FTR_TM
))
1202 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1205 flush_vsx_to_thread(target
);
1206 return target
->thread
.used_vsr
? regset
->n
: 0;
1210 * tm_cvsx_get - get CVSX registers
1211 * @target: The target task.
1212 * @regset: The user regset structure.
1213 * @pos: The buffer position.
1214 * @count: Number of bytes to copy.
1215 * @kbuf: Kernel buffer to copy from.
1216 * @ubuf: User buffer to copy into.
1218 * This function gets in transaction checkpointed VSX registers.
1220 * When the transaction is active 'ckfp_state' holds the checkpointed
1221 * values for the current transaction to fall back on if it aborts
1222 * in between. This function gets those checkpointed VSX registers.
1223 * The userspace interface buffer layout is as follows.
1229 static int tm_cvsx_get(struct task_struct
*target
,
1230 const struct user_regset
*regset
,
1231 unsigned int pos
, unsigned int count
,
1232 void *kbuf
, void __user
*ubuf
)
1237 if (!cpu_has_feature(CPU_FTR_TM
))
1240 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1243 /* Flush the state */
1244 flush_tmregs_to_thread(target
);
1245 flush_fp_to_thread(target
);
1246 flush_altivec_to_thread(target
);
1247 flush_vsx_to_thread(target
);
1249 for (i
= 0; i
< 32 ; i
++)
1250 buf
[i
] = target
->thread
.ckfp_state
.fpr
[i
][TS_VSRLOWOFFSET
];
1251 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1252 buf
, 0, 32 * sizeof(double));
1258 * tm_cvsx_set - set CFPR registers
1259 * @target: The target task.
1260 * @regset: The user regset structure.
1261 * @pos: The buffer position.
1262 * @count: Number of bytes to copy.
1263 * @kbuf: Kernel buffer to copy into.
1264 * @ubuf: User buffer to copy from.
1266 * This function sets in transaction checkpointed VSX registers.
1268 * When the transaction is active 'ckfp_state' holds the checkpointed
1269 * VSX register values for the current transaction to fall back on
1270 * if it aborts in between. This function sets these checkpointed
1271 * FPR registers. The userspace interface buffer layout is as follows.
1277 static int tm_cvsx_set(struct task_struct
*target
,
1278 const struct user_regset
*regset
,
1279 unsigned int pos
, unsigned int count
,
1280 const void *kbuf
, const void __user
*ubuf
)
1285 if (!cpu_has_feature(CPU_FTR_TM
))
1288 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1291 /* Flush the state */
1292 flush_tmregs_to_thread(target
);
1293 flush_fp_to_thread(target
);
1294 flush_altivec_to_thread(target
);
1295 flush_vsx_to_thread(target
);
1297 for (i
= 0; i
< 32 ; i
++)
1298 buf
[i
] = target
->thread
.ckfp_state
.fpr
[i
][TS_VSRLOWOFFSET
];
1300 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1301 buf
, 0, 32 * sizeof(double));
1303 for (i
= 0; i
< 32 ; i
++)
1304 target
->thread
.ckfp_state
.fpr
[i
][TS_VSRLOWOFFSET
] = buf
[i
];
1310 * tm_spr_active - get active number of registers in TM SPR
1311 * @target: The target task.
1312 * @regset: The user regset structure.
1314 * This function checks the active number of available
1315 * regisers in the transactional memory SPR category.
1317 static int tm_spr_active(struct task_struct
*target
,
1318 const struct user_regset
*regset
)
1320 if (!cpu_has_feature(CPU_FTR_TM
))
1327 * tm_spr_get - get the TM related SPR registers
1328 * @target: The target task.
1329 * @regset: The user regset structure.
1330 * @pos: The buffer position.
1331 * @count: Number of bytes to copy.
1332 * @kbuf: Kernel buffer to copy from.
1333 * @ubuf: User buffer to copy into.
1335 * This function gets transactional memory related SPR registers.
1336 * The userspace interface buffer layout is as follows.
1344 static int tm_spr_get(struct task_struct
*target
,
1345 const struct user_regset
*regset
,
1346 unsigned int pos
, unsigned int count
,
1347 void *kbuf
, void __user
*ubuf
)
1352 BUILD_BUG_ON(TSO(tm_tfhar
) + sizeof(u64
) != TSO(tm_texasr
));
1353 BUILD_BUG_ON(TSO(tm_texasr
) + sizeof(u64
) != TSO(tm_tfiar
));
1354 BUILD_BUG_ON(TSO(tm_tfiar
) + sizeof(u64
) != TSO(ckpt_regs
));
1356 if (!cpu_has_feature(CPU_FTR_TM
))
1359 /* Flush the states */
1360 flush_tmregs_to_thread(target
);
1361 flush_fp_to_thread(target
);
1362 flush_altivec_to_thread(target
);
1364 /* TFHAR register */
1365 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1366 &target
->thread
.tm_tfhar
, 0, sizeof(u64
));
1368 /* TEXASR register */
1370 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1371 &target
->thread
.tm_texasr
, sizeof(u64
),
1374 /* TFIAR register */
1376 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1377 &target
->thread
.tm_tfiar
,
1378 2 * sizeof(u64
), 3 * sizeof(u64
));
1383 * tm_spr_set - set the TM related SPR registers
1384 * @target: The target task.
1385 * @regset: The user regset structure.
1386 * @pos: The buffer position.
1387 * @count: Number of bytes to copy.
1388 * @kbuf: Kernel buffer to copy into.
1389 * @ubuf: User buffer to copy from.
1391 * This function sets transactional memory related SPR registers.
1392 * The userspace interface buffer layout is as follows.
1400 static int tm_spr_set(struct task_struct
*target
,
1401 const struct user_regset
*regset
,
1402 unsigned int pos
, unsigned int count
,
1403 const void *kbuf
, const void __user
*ubuf
)
1408 BUILD_BUG_ON(TSO(tm_tfhar
) + sizeof(u64
) != TSO(tm_texasr
));
1409 BUILD_BUG_ON(TSO(tm_texasr
) + sizeof(u64
) != TSO(tm_tfiar
));
1410 BUILD_BUG_ON(TSO(tm_tfiar
) + sizeof(u64
) != TSO(ckpt_regs
));
1412 if (!cpu_has_feature(CPU_FTR_TM
))
1415 /* Flush the states */
1416 flush_tmregs_to_thread(target
);
1417 flush_fp_to_thread(target
);
1418 flush_altivec_to_thread(target
);
1420 /* TFHAR register */
1421 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1422 &target
->thread
.tm_tfhar
, 0, sizeof(u64
));
1424 /* TEXASR register */
1426 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1427 &target
->thread
.tm_texasr
, sizeof(u64
),
1430 /* TFIAR register */
1432 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1433 &target
->thread
.tm_tfiar
,
1434 2 * sizeof(u64
), 3 * sizeof(u64
));
1438 static int tm_tar_active(struct task_struct
*target
,
1439 const struct user_regset
*regset
)
1441 if (!cpu_has_feature(CPU_FTR_TM
))
1444 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1450 static int tm_tar_get(struct task_struct
*target
,
1451 const struct user_regset
*regset
,
1452 unsigned int pos
, unsigned int count
,
1453 void *kbuf
, void __user
*ubuf
)
1457 if (!cpu_has_feature(CPU_FTR_TM
))
1460 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1463 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1464 &target
->thread
.tm_tar
, 0, sizeof(u64
));
1468 static int tm_tar_set(struct task_struct
*target
,
1469 const struct user_regset
*regset
,
1470 unsigned int pos
, unsigned int count
,
1471 const void *kbuf
, const void __user
*ubuf
)
1475 if (!cpu_has_feature(CPU_FTR_TM
))
1478 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1481 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1482 &target
->thread
.tm_tar
, 0, sizeof(u64
));
1486 static int tm_ppr_active(struct task_struct
*target
,
1487 const struct user_regset
*regset
)
1489 if (!cpu_has_feature(CPU_FTR_TM
))
1492 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1499 static int tm_ppr_get(struct task_struct
*target
,
1500 const struct user_regset
*regset
,
1501 unsigned int pos
, unsigned int count
,
1502 void *kbuf
, void __user
*ubuf
)
1506 if (!cpu_has_feature(CPU_FTR_TM
))
1509 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1512 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1513 &target
->thread
.tm_ppr
, 0, sizeof(u64
));
1517 static int tm_ppr_set(struct task_struct
*target
,
1518 const struct user_regset
*regset
,
1519 unsigned int pos
, unsigned int count
,
1520 const void *kbuf
, const void __user
*ubuf
)
1524 if (!cpu_has_feature(CPU_FTR_TM
))
1527 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1530 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1531 &target
->thread
.tm_ppr
, 0, sizeof(u64
));
1535 static int tm_dscr_active(struct task_struct
*target
,
1536 const struct user_regset
*regset
)
1538 if (!cpu_has_feature(CPU_FTR_TM
))
1541 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1547 static int tm_dscr_get(struct task_struct
*target
,
1548 const struct user_regset
*regset
,
1549 unsigned int pos
, unsigned int count
,
1550 void *kbuf
, void __user
*ubuf
)
1554 if (!cpu_has_feature(CPU_FTR_TM
))
1557 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1560 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1561 &target
->thread
.tm_dscr
, 0, sizeof(u64
));
1565 static int tm_dscr_set(struct task_struct
*target
,
1566 const struct user_regset
*regset
,
1567 unsigned int pos
, unsigned int count
,
1568 const void *kbuf
, const void __user
*ubuf
)
1572 if (!cpu_has_feature(CPU_FTR_TM
))
1575 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1578 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1579 &target
->thread
.tm_dscr
, 0, sizeof(u64
));
1582 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1585 static int ppr_get(struct task_struct
*target
,
1586 const struct user_regset
*regset
,
1587 unsigned int pos
, unsigned int count
,
1588 void *kbuf
, void __user
*ubuf
)
1592 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1593 &target
->thread
.ppr
, 0, sizeof(u64
));
1597 static int ppr_set(struct task_struct
*target
,
1598 const struct user_regset
*regset
,
1599 unsigned int pos
, unsigned int count
,
1600 const void *kbuf
, const void __user
*ubuf
)
1604 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1605 &target
->thread
.ppr
, 0, sizeof(u64
));
1609 static int dscr_get(struct task_struct
*target
,
1610 const struct user_regset
*regset
,
1611 unsigned int pos
, unsigned int count
,
1612 void *kbuf
, void __user
*ubuf
)
1616 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1617 &target
->thread
.dscr
, 0, sizeof(u64
));
1620 static int dscr_set(struct task_struct
*target
,
1621 const struct user_regset
*regset
,
1622 unsigned int pos
, unsigned int count
,
1623 const void *kbuf
, const void __user
*ubuf
)
1627 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1628 &target
->thread
.dscr
, 0, sizeof(u64
));
1632 #ifdef CONFIG_PPC_BOOK3S_64
1633 static int tar_get(struct task_struct
*target
,
1634 const struct user_regset
*regset
,
1635 unsigned int pos
, unsigned int count
,
1636 void *kbuf
, void __user
*ubuf
)
1640 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1641 &target
->thread
.tar
, 0, sizeof(u64
));
1644 static int tar_set(struct task_struct
*target
,
1645 const struct user_regset
*regset
,
1646 unsigned int pos
, unsigned int count
,
1647 const void *kbuf
, const void __user
*ubuf
)
1651 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1652 &target
->thread
.tar
, 0, sizeof(u64
));
1656 static int ebb_active(struct task_struct
*target
,
1657 const struct user_regset
*regset
)
1659 if (!cpu_has_feature(CPU_FTR_ARCH_207S
))
1662 if (target
->thread
.used_ebb
)
1668 static int ebb_get(struct task_struct
*target
,
1669 const struct user_regset
*regset
,
1670 unsigned int pos
, unsigned int count
,
1671 void *kbuf
, void __user
*ubuf
)
1674 BUILD_BUG_ON(TSO(ebbrr
) + sizeof(unsigned long) != TSO(ebbhr
));
1675 BUILD_BUG_ON(TSO(ebbhr
) + sizeof(unsigned long) != TSO(bescr
));
1677 if (!cpu_has_feature(CPU_FTR_ARCH_207S
))
1680 if (!target
->thread
.used_ebb
)
1683 return user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1684 &target
->thread
.ebbrr
, 0, 3 * sizeof(unsigned long));
1687 static int ebb_set(struct task_struct
*target
,
1688 const struct user_regset
*regset
,
1689 unsigned int pos
, unsigned int count
,
1690 const void *kbuf
, const void __user
*ubuf
)
1695 BUILD_BUG_ON(TSO(ebbrr
) + sizeof(unsigned long) != TSO(ebbhr
));
1696 BUILD_BUG_ON(TSO(ebbhr
) + sizeof(unsigned long) != TSO(bescr
));
1698 if (!cpu_has_feature(CPU_FTR_ARCH_207S
))
1701 if (target
->thread
.used_ebb
)
1704 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1705 &target
->thread
.ebbrr
, 0, sizeof(unsigned long));
1708 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1709 &target
->thread
.ebbhr
, sizeof(unsigned long),
1710 2 * sizeof(unsigned long));
1713 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1714 &target
->thread
.bescr
,
1715 2 * sizeof(unsigned long), 3 * sizeof(unsigned long));
1719 static int pmu_active(struct task_struct
*target
,
1720 const struct user_regset
*regset
)
1722 if (!cpu_has_feature(CPU_FTR_ARCH_207S
))
1728 static int pmu_get(struct task_struct
*target
,
1729 const struct user_regset
*regset
,
1730 unsigned int pos
, unsigned int count
,
1731 void *kbuf
, void __user
*ubuf
)
1734 BUILD_BUG_ON(TSO(siar
) + sizeof(unsigned long) != TSO(sdar
));
1735 BUILD_BUG_ON(TSO(sdar
) + sizeof(unsigned long) != TSO(sier
));
1736 BUILD_BUG_ON(TSO(sier
) + sizeof(unsigned long) != TSO(mmcr2
));
1737 BUILD_BUG_ON(TSO(mmcr2
) + sizeof(unsigned long) != TSO(mmcr0
));
1739 if (!cpu_has_feature(CPU_FTR_ARCH_207S
))
1742 return user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1743 &target
->thread
.siar
, 0,
1744 5 * sizeof(unsigned long));
1747 static int pmu_set(struct task_struct
*target
,
1748 const struct user_regset
*regset
,
1749 unsigned int pos
, unsigned int count
,
1750 const void *kbuf
, const void __user
*ubuf
)
1755 BUILD_BUG_ON(TSO(siar
) + sizeof(unsigned long) != TSO(sdar
));
1756 BUILD_BUG_ON(TSO(sdar
) + sizeof(unsigned long) != TSO(sier
));
1757 BUILD_BUG_ON(TSO(sier
) + sizeof(unsigned long) != TSO(mmcr2
));
1758 BUILD_BUG_ON(TSO(mmcr2
) + sizeof(unsigned long) != TSO(mmcr0
));
1760 if (!cpu_has_feature(CPU_FTR_ARCH_207S
))
1763 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1764 &target
->thread
.siar
, 0,
1765 sizeof(unsigned long));
1768 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1769 &target
->thread
.sdar
, sizeof(unsigned long),
1770 2 * sizeof(unsigned long));
1773 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1774 &target
->thread
.sier
, 2 * sizeof(unsigned long),
1775 3 * sizeof(unsigned long));
1778 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1779 &target
->thread
.mmcr2
, 3 * sizeof(unsigned long),
1780 4 * sizeof(unsigned long));
1783 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1784 &target
->thread
.mmcr0
, 4 * sizeof(unsigned long),
1785 5 * sizeof(unsigned long));
1790 * These are our native regset flavors.
1792 enum powerpc_regset
{
1795 #ifdef CONFIG_ALTIVEC
1804 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1805 REGSET_TM_CGPR
, /* TM checkpointed GPR registers */
1806 REGSET_TM_CFPR
, /* TM checkpointed FPR registers */
1807 REGSET_TM_CVMX
, /* TM checkpointed VMX registers */
1808 REGSET_TM_CVSX
, /* TM checkpointed VSX registers */
1809 REGSET_TM_SPR
, /* TM specific SPR registers */
1810 REGSET_TM_CTAR
, /* TM checkpointed TAR register */
1811 REGSET_TM_CPPR
, /* TM checkpointed PPR register */
1812 REGSET_TM_CDSCR
, /* TM checkpointed DSCR register */
1815 REGSET_PPR
, /* PPR register */
1816 REGSET_DSCR
, /* DSCR register */
1818 #ifdef CONFIG_PPC_BOOK3S_64
1819 REGSET_TAR
, /* TAR register */
1820 REGSET_EBB
, /* EBB registers */
1821 REGSET_PMR
, /* Performance Monitor Registers */
1825 static const struct user_regset native_regsets
[] = {
1827 .core_note_type
= NT_PRSTATUS
, .n
= ELF_NGREG
,
1828 .size
= sizeof(long), .align
= sizeof(long),
1829 .get
= gpr_get
, .set
= gpr_set
1832 .core_note_type
= NT_PRFPREG
, .n
= ELF_NFPREG
,
1833 .size
= sizeof(double), .align
= sizeof(double),
1834 .get
= fpr_get
, .set
= fpr_set
1836 #ifdef CONFIG_ALTIVEC
1838 .core_note_type
= NT_PPC_VMX
, .n
= 34,
1839 .size
= sizeof(vector128
), .align
= sizeof(vector128
),
1840 .active
= vr_active
, .get
= vr_get
, .set
= vr_set
1845 .core_note_type
= NT_PPC_VSX
, .n
= 32,
1846 .size
= sizeof(double), .align
= sizeof(double),
1847 .active
= vsr_active
, .get
= vsr_get
, .set
= vsr_set
1852 .core_note_type
= NT_PPC_SPE
, .n
= 35,
1853 .size
= sizeof(u32
), .align
= sizeof(u32
),
1854 .active
= evr_active
, .get
= evr_get
, .set
= evr_set
1857 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1858 [REGSET_TM_CGPR
] = {
1859 .core_note_type
= NT_PPC_TM_CGPR
, .n
= ELF_NGREG
,
1860 .size
= sizeof(long), .align
= sizeof(long),
1861 .active
= tm_cgpr_active
, .get
= tm_cgpr_get
, .set
= tm_cgpr_set
1863 [REGSET_TM_CFPR
] = {
1864 .core_note_type
= NT_PPC_TM_CFPR
, .n
= ELF_NFPREG
,
1865 .size
= sizeof(double), .align
= sizeof(double),
1866 .active
= tm_cfpr_active
, .get
= tm_cfpr_get
, .set
= tm_cfpr_set
1868 [REGSET_TM_CVMX
] = {
1869 .core_note_type
= NT_PPC_TM_CVMX
, .n
= ELF_NVMX
,
1870 .size
= sizeof(vector128
), .align
= sizeof(vector128
),
1871 .active
= tm_cvmx_active
, .get
= tm_cvmx_get
, .set
= tm_cvmx_set
1873 [REGSET_TM_CVSX
] = {
1874 .core_note_type
= NT_PPC_TM_CVSX
, .n
= ELF_NVSX
,
1875 .size
= sizeof(double), .align
= sizeof(double),
1876 .active
= tm_cvsx_active
, .get
= tm_cvsx_get
, .set
= tm_cvsx_set
1879 .core_note_type
= NT_PPC_TM_SPR
, .n
= ELF_NTMSPRREG
,
1880 .size
= sizeof(u64
), .align
= sizeof(u64
),
1881 .active
= tm_spr_active
, .get
= tm_spr_get
, .set
= tm_spr_set
1883 [REGSET_TM_CTAR
] = {
1884 .core_note_type
= NT_PPC_TM_CTAR
, .n
= 1,
1885 .size
= sizeof(u64
), .align
= sizeof(u64
),
1886 .active
= tm_tar_active
, .get
= tm_tar_get
, .set
= tm_tar_set
1888 [REGSET_TM_CPPR
] = {
1889 .core_note_type
= NT_PPC_TM_CPPR
, .n
= 1,
1890 .size
= sizeof(u64
), .align
= sizeof(u64
),
1891 .active
= tm_ppr_active
, .get
= tm_ppr_get
, .set
= tm_ppr_set
1893 [REGSET_TM_CDSCR
] = {
1894 .core_note_type
= NT_PPC_TM_CDSCR
, .n
= 1,
1895 .size
= sizeof(u64
), .align
= sizeof(u64
),
1896 .active
= tm_dscr_active
, .get
= tm_dscr_get
, .set
= tm_dscr_set
1901 .core_note_type
= NT_PPC_PPR
, .n
= 1,
1902 .size
= sizeof(u64
), .align
= sizeof(u64
),
1903 .get
= ppr_get
, .set
= ppr_set
1906 .core_note_type
= NT_PPC_DSCR
, .n
= 1,
1907 .size
= sizeof(u64
), .align
= sizeof(u64
),
1908 .get
= dscr_get
, .set
= dscr_set
1911 #ifdef CONFIG_PPC_BOOK3S_64
1913 .core_note_type
= NT_PPC_TAR
, .n
= 1,
1914 .size
= sizeof(u64
), .align
= sizeof(u64
),
1915 .get
= tar_get
, .set
= tar_set
1918 .core_note_type
= NT_PPC_EBB
, .n
= ELF_NEBB
,
1919 .size
= sizeof(u64
), .align
= sizeof(u64
),
1920 .active
= ebb_active
, .get
= ebb_get
, .set
= ebb_set
1923 .core_note_type
= NT_PPC_PMU
, .n
= ELF_NPMU
,
1924 .size
= sizeof(u64
), .align
= sizeof(u64
),
1925 .active
= pmu_active
, .get
= pmu_get
, .set
= pmu_set
1930 static const struct user_regset_view user_ppc_native_view
= {
1931 .name
= UTS_MACHINE
, .e_machine
= ELF_ARCH
, .ei_osabi
= ELF_OSABI
,
1932 .regsets
= native_regsets
, .n
= ARRAY_SIZE(native_regsets
)
1936 #include <linux/compat.h>
1938 static int gpr32_get_common(struct task_struct
*target
,
1939 const struct user_regset
*regset
,
1940 unsigned int pos
, unsigned int count
,
1941 void *kbuf
, void __user
*ubuf
,
1942 unsigned long *regs
)
1944 compat_ulong_t
*k
= kbuf
;
1945 compat_ulong_t __user
*u
= ubuf
;
1949 count
/= sizeof(reg
);
1952 for (; count
> 0 && pos
< PT_MSR
; --count
)
1955 for (; count
> 0 && pos
< PT_MSR
; --count
)
1956 if (__put_user((compat_ulong_t
) regs
[pos
++], u
++))
1959 if (count
> 0 && pos
== PT_MSR
) {
1960 reg
= get_user_msr(target
);
1963 else if (__put_user(reg
, u
++))
1970 for (; count
> 0 && pos
< PT_REGS_COUNT
; --count
)
1973 for (; count
> 0 && pos
< PT_REGS_COUNT
; --count
)
1974 if (__put_user((compat_ulong_t
) regs
[pos
++], u
++))
1980 count
*= sizeof(reg
);
1981 return user_regset_copyout_zero(&pos
, &count
, &kbuf
, &ubuf
,
1982 PT_REGS_COUNT
* sizeof(reg
), -1);
1985 static int gpr32_set_common(struct task_struct
*target
,
1986 const struct user_regset
*regset
,
1987 unsigned int pos
, unsigned int count
,
1988 const void *kbuf
, const void __user
*ubuf
,
1989 unsigned long *regs
)
1991 const compat_ulong_t
*k
= kbuf
;
1992 const compat_ulong_t __user
*u
= ubuf
;
1996 count
/= sizeof(reg
);
1999 for (; count
> 0 && pos
< PT_MSR
; --count
)
2002 for (; count
> 0 && pos
< PT_MSR
; --count
) {
2003 if (__get_user(reg
, u
++))
2009 if (count
> 0 && pos
== PT_MSR
) {
2012 else if (__get_user(reg
, u
++))
2014 set_user_msr(target
, reg
);
2020 for (; count
> 0 && pos
<= PT_MAX_PUT_REG
; --count
)
2022 for (; count
> 0 && pos
< PT_TRAP
; --count
, ++pos
)
2025 for (; count
> 0 && pos
<= PT_MAX_PUT_REG
; --count
) {
2026 if (__get_user(reg
, u
++))
2030 for (; count
> 0 && pos
< PT_TRAP
; --count
, ++pos
)
2031 if (__get_user(reg
, u
++))
2035 if (count
> 0 && pos
== PT_TRAP
) {
2038 else if (__get_user(reg
, u
++))
2040 set_user_trap(target
, reg
);
2048 count
*= sizeof(reg
);
2049 return user_regset_copyin_ignore(&pos
, &count
, &kbuf
, &ubuf
,
2050 (PT_TRAP
+ 1) * sizeof(reg
), -1);
2053 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2054 static int tm_cgpr32_get(struct task_struct
*target
,
2055 const struct user_regset
*regset
,
2056 unsigned int pos
, unsigned int count
,
2057 void *kbuf
, void __user
*ubuf
)
2059 return gpr32_get_common(target
, regset
, pos
, count
, kbuf
, ubuf
,
2060 &target
->thread
.ckpt_regs
.gpr
[0]);
2063 static int tm_cgpr32_set(struct task_struct
*target
,
2064 const struct user_regset
*regset
,
2065 unsigned int pos
, unsigned int count
,
2066 const void *kbuf
, const void __user
*ubuf
)
2068 return gpr32_set_common(target
, regset
, pos
, count
, kbuf
, ubuf
,
2069 &target
->thread
.ckpt_regs
.gpr
[0]);
2071 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2073 static int gpr32_get(struct task_struct
*target
,
2074 const struct user_regset
*regset
,
2075 unsigned int pos
, unsigned int count
,
2076 void *kbuf
, void __user
*ubuf
)
2080 if (target
->thread
.regs
== NULL
)
2083 if (!FULL_REGS(target
->thread
.regs
)) {
2085 * We have a partial register set.
2086 * Fill 14-31 with bogus values.
2088 for (i
= 14; i
< 32; i
++)
2089 target
->thread
.regs
->gpr
[i
] = NV_REG_POISON
;
2091 return gpr32_get_common(target
, regset
, pos
, count
, kbuf
, ubuf
,
2092 &target
->thread
.regs
->gpr
[0]);
2095 static int gpr32_set(struct task_struct
*target
,
2096 const struct user_regset
*regset
,
2097 unsigned int pos
, unsigned int count
,
2098 const void *kbuf
, const void __user
*ubuf
)
2100 if (target
->thread
.regs
== NULL
)
2103 CHECK_FULL_REGS(target
->thread
.regs
);
2104 return gpr32_set_common(target
, regset
, pos
, count
, kbuf
, ubuf
,
2105 &target
->thread
.regs
->gpr
[0]);
2109 * These are the regset flavors matching the CONFIG_PPC32 native set.
2111 static const struct user_regset compat_regsets
[] = {
2113 .core_note_type
= NT_PRSTATUS
, .n
= ELF_NGREG
,
2114 .size
= sizeof(compat_long_t
), .align
= sizeof(compat_long_t
),
2115 .get
= gpr32_get
, .set
= gpr32_set
2118 .core_note_type
= NT_PRFPREG
, .n
= ELF_NFPREG
,
2119 .size
= sizeof(double), .align
= sizeof(double),
2120 .get
= fpr_get
, .set
= fpr_set
2122 #ifdef CONFIG_ALTIVEC
2124 .core_note_type
= NT_PPC_VMX
, .n
= 34,
2125 .size
= sizeof(vector128
), .align
= sizeof(vector128
),
2126 .active
= vr_active
, .get
= vr_get
, .set
= vr_set
2131 .core_note_type
= NT_PPC_SPE
, .n
= 35,
2132 .size
= sizeof(u32
), .align
= sizeof(u32
),
2133 .active
= evr_active
, .get
= evr_get
, .set
= evr_set
2136 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2137 [REGSET_TM_CGPR
] = {
2138 .core_note_type
= NT_PPC_TM_CGPR
, .n
= ELF_NGREG
,
2139 .size
= sizeof(long), .align
= sizeof(long),
2140 .active
= tm_cgpr_active
,
2141 .get
= tm_cgpr32_get
, .set
= tm_cgpr32_set
2143 [REGSET_TM_CFPR
] = {
2144 .core_note_type
= NT_PPC_TM_CFPR
, .n
= ELF_NFPREG
,
2145 .size
= sizeof(double), .align
= sizeof(double),
2146 .active
= tm_cfpr_active
, .get
= tm_cfpr_get
, .set
= tm_cfpr_set
2148 [REGSET_TM_CVMX
] = {
2149 .core_note_type
= NT_PPC_TM_CVMX
, .n
= ELF_NVMX
,
2150 .size
= sizeof(vector128
), .align
= sizeof(vector128
),
2151 .active
= tm_cvmx_active
, .get
= tm_cvmx_get
, .set
= tm_cvmx_set
2153 [REGSET_TM_CVSX
] = {
2154 .core_note_type
= NT_PPC_TM_CVSX
, .n
= ELF_NVSX
,
2155 .size
= sizeof(double), .align
= sizeof(double),
2156 .active
= tm_cvsx_active
, .get
= tm_cvsx_get
, .set
= tm_cvsx_set
2159 .core_note_type
= NT_PPC_TM_SPR
, .n
= ELF_NTMSPRREG
,
2160 .size
= sizeof(u64
), .align
= sizeof(u64
),
2161 .active
= tm_spr_active
, .get
= tm_spr_get
, .set
= tm_spr_set
2163 [REGSET_TM_CTAR
] = {
2164 .core_note_type
= NT_PPC_TM_CTAR
, .n
= 1,
2165 .size
= sizeof(u64
), .align
= sizeof(u64
),
2166 .active
= tm_tar_active
, .get
= tm_tar_get
, .set
= tm_tar_set
2168 [REGSET_TM_CPPR
] = {
2169 .core_note_type
= NT_PPC_TM_CPPR
, .n
= 1,
2170 .size
= sizeof(u64
), .align
= sizeof(u64
),
2171 .active
= tm_ppr_active
, .get
= tm_ppr_get
, .set
= tm_ppr_set
2173 [REGSET_TM_CDSCR
] = {
2174 .core_note_type
= NT_PPC_TM_CDSCR
, .n
= 1,
2175 .size
= sizeof(u64
), .align
= sizeof(u64
),
2176 .active
= tm_dscr_active
, .get
= tm_dscr_get
, .set
= tm_dscr_set
2181 .core_note_type
= NT_PPC_PPR
, .n
= 1,
2182 .size
= sizeof(u64
), .align
= sizeof(u64
),
2183 .get
= ppr_get
, .set
= ppr_set
2186 .core_note_type
= NT_PPC_DSCR
, .n
= 1,
2187 .size
= sizeof(u64
), .align
= sizeof(u64
),
2188 .get
= dscr_get
, .set
= dscr_set
2191 #ifdef CONFIG_PPC_BOOK3S_64
2193 .core_note_type
= NT_PPC_TAR
, .n
= 1,
2194 .size
= sizeof(u64
), .align
= sizeof(u64
),
2195 .get
= tar_get
, .set
= tar_set
2198 .core_note_type
= NT_PPC_EBB
, .n
= ELF_NEBB
,
2199 .size
= sizeof(u64
), .align
= sizeof(u64
),
2200 .active
= ebb_active
, .get
= ebb_get
, .set
= ebb_set
2205 static const struct user_regset_view user_ppc_compat_view
= {
2206 .name
= "ppc", .e_machine
= EM_PPC
, .ei_osabi
= ELF_OSABI
,
2207 .regsets
= compat_regsets
, .n
= ARRAY_SIZE(compat_regsets
)
2209 #endif /* CONFIG_PPC64 */
2211 const struct user_regset_view
*task_user_regset_view(struct task_struct
*task
)
2214 if (test_tsk_thread_flag(task
, TIF_32BIT
))
2215 return &user_ppc_compat_view
;
2217 return &user_ppc_native_view
;
2221 void user_enable_single_step(struct task_struct
*task
)
2223 struct pt_regs
*regs
= task
->thread
.regs
;
2226 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2227 task
->thread
.debug
.dbcr0
&= ~DBCR0_BT
;
2228 task
->thread
.debug
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
2229 regs
->msr
|= MSR_DE
;
2231 regs
->msr
&= ~MSR_BE
;
2232 regs
->msr
|= MSR_SE
;
2235 set_tsk_thread_flag(task
, TIF_SINGLESTEP
);
2238 void user_enable_block_step(struct task_struct
*task
)
2240 struct pt_regs
*regs
= task
->thread
.regs
;
2243 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2244 task
->thread
.debug
.dbcr0
&= ~DBCR0_IC
;
2245 task
->thread
.debug
.dbcr0
= DBCR0_IDM
| DBCR0_BT
;
2246 regs
->msr
|= MSR_DE
;
2248 regs
->msr
&= ~MSR_SE
;
2249 regs
->msr
|= MSR_BE
;
2252 set_tsk_thread_flag(task
, TIF_SINGLESTEP
);
2255 void user_disable_single_step(struct task_struct
*task
)
2257 struct pt_regs
*regs
= task
->thread
.regs
;
2260 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2262 * The logic to disable single stepping should be as
2263 * simple as turning off the Instruction Complete flag.
2264 * And, after doing so, if all debug flags are off, turn
2265 * off DBCR0(IDM) and MSR(DE) .... Torez
2267 task
->thread
.debug
.dbcr0
&= ~(DBCR0_IC
|DBCR0_BT
);
2269 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
2271 if (!DBCR_ACTIVE_EVENTS(task
->thread
.debug
.dbcr0
,
2272 task
->thread
.debug
.dbcr1
)) {
2274 * All debug events were off.....
2276 task
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
2277 regs
->msr
&= ~MSR_DE
;
2280 regs
->msr
&= ~(MSR_SE
| MSR_BE
);
2283 clear_tsk_thread_flag(task
, TIF_SINGLESTEP
);
2286 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2287 void ptrace_triggered(struct perf_event
*bp
,
2288 struct perf_sample_data
*data
, struct pt_regs
*regs
)
2290 struct perf_event_attr attr
;
2293 * Disable the breakpoint request here since ptrace has defined a
2294 * one-shot behaviour for breakpoint exceptions in PPC64.
2295 * The SIGTRAP signal is generated automatically for us in do_dabr().
2296 * We don't have to do anything about that here
2299 attr
.disabled
= true;
2300 modify_user_hw_breakpoint(bp
, &attr
);
2302 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2304 static int ptrace_set_debugreg(struct task_struct
*task
, unsigned long addr
,
2307 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2309 struct thread_struct
*thread
= &(task
->thread
);
2310 struct perf_event
*bp
;
2311 struct perf_event_attr attr
;
2312 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2313 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2314 struct arch_hw_breakpoint hw_brk
;
2317 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
2318 * For embedded processors we support one DAC and no IAC's at the
2324 /* The bottom 3 bits in dabr are flags */
2325 if ((data
& ~0x7UL
) >= TASK_SIZE
)
2328 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2329 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
2330 * It was assumed, on previous implementations, that 3 bits were
2331 * passed together with the data address, fitting the design of the
2332 * DABR register, as follows:
2336 * bit 2: Breakpoint translation
2338 * Thus, we use them here as so.
2341 /* Ensure breakpoint translation bit is set */
2342 if (data
&& !(data
& HW_BRK_TYPE_TRANSLATE
))
2344 hw_brk
.address
= data
& (~HW_BRK_TYPE_DABR
);
2345 hw_brk
.type
= (data
& HW_BRK_TYPE_DABR
) | HW_BRK_TYPE_PRIV_ALL
;
2347 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2348 bp
= thread
->ptrace_bps
[0];
2349 if ((!data
) || !(hw_brk
.type
& HW_BRK_TYPE_RDWR
)) {
2351 unregister_hw_breakpoint(bp
);
2352 thread
->ptrace_bps
[0] = NULL
;
2358 attr
.bp_addr
= hw_brk
.address
;
2359 arch_bp_generic_fields(hw_brk
.type
, &attr
.bp_type
);
2361 /* Enable breakpoint */
2362 attr
.disabled
= false;
2364 ret
= modify_user_hw_breakpoint(bp
, &attr
);
2368 thread
->ptrace_bps
[0] = bp
;
2369 thread
->hw_brk
= hw_brk
;
2373 /* Create a new breakpoint request if one doesn't exist already */
2374 hw_breakpoint_init(&attr
);
2375 attr
.bp_addr
= hw_brk
.address
;
2376 arch_bp_generic_fields(hw_brk
.type
,
2379 thread
->ptrace_bps
[0] = bp
= register_user_hw_breakpoint(&attr
,
2380 ptrace_triggered
, NULL
, task
);
2382 thread
->ptrace_bps
[0] = NULL
;
2386 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2387 task
->thread
.hw_brk
= hw_brk
;
2388 #else /* CONFIG_PPC_ADV_DEBUG_REGS */
2389 /* As described above, it was assumed 3 bits were passed with the data
2390 * address, but we will assume only the mode bits will be passed
2391 * as to not cause alignment restrictions for DAC-based processors.
2394 /* DAC's hold the whole address without any mode flags */
2395 task
->thread
.debug
.dac1
= data
& ~0x3UL
;
2397 if (task
->thread
.debug
.dac1
== 0) {
2398 dbcr_dac(task
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
2399 if (!DBCR_ACTIVE_EVENTS(task
->thread
.debug
.dbcr0
,
2400 task
->thread
.debug
.dbcr1
)) {
2401 task
->thread
.regs
->msr
&= ~MSR_DE
;
2402 task
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
2407 /* Read or Write bits must be set */
2409 if (!(data
& 0x3UL
))
2412 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
2414 task
->thread
.debug
.dbcr0
|= DBCR0_IDM
;
2416 /* Check for write and read flags and set DBCR0
2418 dbcr_dac(task
) &= ~(DBCR_DAC1R
|DBCR_DAC1W
);
2420 dbcr_dac(task
) |= DBCR_DAC1R
;
2422 dbcr_dac(task
) |= DBCR_DAC1W
;
2423 task
->thread
.regs
->msr
|= MSR_DE
;
2424 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2429 * Called by kernel/ptrace.c when detaching..
2431 * Make sure single step bits etc are not set.
2433 void ptrace_disable(struct task_struct
*child
)
2435 /* make sure the single step bit is not set. */
2436 user_disable_single_step(child
);
2439 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2440 static long set_instruction_bp(struct task_struct
*child
,
2441 struct ppc_hw_breakpoint
*bp_info
)
2444 int slot1_in_use
= ((child
->thread
.debug
.dbcr0
& DBCR0_IAC1
) != 0);
2445 int slot2_in_use
= ((child
->thread
.debug
.dbcr0
& DBCR0_IAC2
) != 0);
2446 int slot3_in_use
= ((child
->thread
.debug
.dbcr0
& DBCR0_IAC3
) != 0);
2447 int slot4_in_use
= ((child
->thread
.debug
.dbcr0
& DBCR0_IAC4
) != 0);
2449 if (dbcr_iac_range(child
) & DBCR_IAC12MODE
)
2451 if (dbcr_iac_range(child
) & DBCR_IAC34MODE
)
2454 if (bp_info
->addr
>= TASK_SIZE
)
2457 if (bp_info
->addr_mode
!= PPC_BREAKPOINT_MODE_EXACT
) {
2459 /* Make sure range is valid. */
2460 if (bp_info
->addr2
>= TASK_SIZE
)
2463 /* We need a pair of IAC regsisters */
2464 if ((!slot1_in_use
) && (!slot2_in_use
)) {
2466 child
->thread
.debug
.iac1
= bp_info
->addr
;
2467 child
->thread
.debug
.iac2
= bp_info
->addr2
;
2468 child
->thread
.debug
.dbcr0
|= DBCR0_IAC1
;
2469 if (bp_info
->addr_mode
==
2470 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE
)
2471 dbcr_iac_range(child
) |= DBCR_IAC12X
;
2473 dbcr_iac_range(child
) |= DBCR_IAC12I
;
2474 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2475 } else if ((!slot3_in_use
) && (!slot4_in_use
)) {
2477 child
->thread
.debug
.iac3
= bp_info
->addr
;
2478 child
->thread
.debug
.iac4
= bp_info
->addr2
;
2479 child
->thread
.debug
.dbcr0
|= DBCR0_IAC3
;
2480 if (bp_info
->addr_mode
==
2481 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE
)
2482 dbcr_iac_range(child
) |= DBCR_IAC34X
;
2484 dbcr_iac_range(child
) |= DBCR_IAC34I
;
2489 /* We only need one. If possible leave a pair free in
2490 * case a range is needed later
2492 if (!slot1_in_use
) {
2494 * Don't use iac1 if iac1-iac2 are free and either
2495 * iac3 or iac4 (but not both) are free
2497 if (slot2_in_use
|| (slot3_in_use
== slot4_in_use
)) {
2499 child
->thread
.debug
.iac1
= bp_info
->addr
;
2500 child
->thread
.debug
.dbcr0
|= DBCR0_IAC1
;
2504 if (!slot2_in_use
) {
2506 child
->thread
.debug
.iac2
= bp_info
->addr
;
2507 child
->thread
.debug
.dbcr0
|= DBCR0_IAC2
;
2508 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2509 } else if (!slot3_in_use
) {
2511 child
->thread
.debug
.iac3
= bp_info
->addr
;
2512 child
->thread
.debug
.dbcr0
|= DBCR0_IAC3
;
2513 } else if (!slot4_in_use
) {
2515 child
->thread
.debug
.iac4
= bp_info
->addr
;
2516 child
->thread
.debug
.dbcr0
|= DBCR0_IAC4
;
2522 child
->thread
.debug
.dbcr0
|= DBCR0_IDM
;
2523 child
->thread
.regs
->msr
|= MSR_DE
;
2528 static int del_instruction_bp(struct task_struct
*child
, int slot
)
2532 if ((child
->thread
.debug
.dbcr0
& DBCR0_IAC1
) == 0)
2535 if (dbcr_iac_range(child
) & DBCR_IAC12MODE
) {
2536 /* address range - clear slots 1 & 2 */
2537 child
->thread
.debug
.iac2
= 0;
2538 dbcr_iac_range(child
) &= ~DBCR_IAC12MODE
;
2540 child
->thread
.debug
.iac1
= 0;
2541 child
->thread
.debug
.dbcr0
&= ~DBCR0_IAC1
;
2544 if ((child
->thread
.debug
.dbcr0
& DBCR0_IAC2
) == 0)
2547 if (dbcr_iac_range(child
) & DBCR_IAC12MODE
)
2548 /* used in a range */
2550 child
->thread
.debug
.iac2
= 0;
2551 child
->thread
.debug
.dbcr0
&= ~DBCR0_IAC2
;
2553 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2555 if ((child
->thread
.debug
.dbcr0
& DBCR0_IAC3
) == 0)
2558 if (dbcr_iac_range(child
) & DBCR_IAC34MODE
) {
2559 /* address range - clear slots 3 & 4 */
2560 child
->thread
.debug
.iac4
= 0;
2561 dbcr_iac_range(child
) &= ~DBCR_IAC34MODE
;
2563 child
->thread
.debug
.iac3
= 0;
2564 child
->thread
.debug
.dbcr0
&= ~DBCR0_IAC3
;
2567 if ((child
->thread
.debug
.dbcr0
& DBCR0_IAC4
) == 0)
2570 if (dbcr_iac_range(child
) & DBCR_IAC34MODE
)
2571 /* Used in a range */
2573 child
->thread
.debug
.iac4
= 0;
2574 child
->thread
.debug
.dbcr0
&= ~DBCR0_IAC4
;
2583 static int set_dac(struct task_struct
*child
, struct ppc_hw_breakpoint
*bp_info
)
2586 (bp_info
->condition_mode
>> PPC_BREAKPOINT_CONDITION_BE_SHIFT
)
2588 int condition_mode
=
2589 bp_info
->condition_mode
& PPC_BREAKPOINT_CONDITION_MODE
;
2592 if (byte_enable
&& (condition_mode
== 0))
2595 if (bp_info
->addr
>= TASK_SIZE
)
2598 if ((dbcr_dac(child
) & (DBCR_DAC1R
| DBCR_DAC1W
)) == 0) {
2600 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_READ
)
2601 dbcr_dac(child
) |= DBCR_DAC1R
;
2602 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_WRITE
)
2603 dbcr_dac(child
) |= DBCR_DAC1W
;
2604 child
->thread
.debug
.dac1
= (unsigned long)bp_info
->addr
;
2605 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2607 child
->thread
.debug
.dvc1
=
2608 (unsigned long)bp_info
->condition_value
;
2609 child
->thread
.debug
.dbcr2
|=
2610 ((byte_enable
<< DBCR2_DVC1BE_SHIFT
) |
2611 (condition_mode
<< DBCR2_DVC1M_SHIFT
));
2614 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2615 } else if (child
->thread
.debug
.dbcr2
& DBCR2_DAC12MODE
) {
2616 /* Both dac1 and dac2 are part of a range */
2619 } else if ((dbcr_dac(child
) & (DBCR_DAC2R
| DBCR_DAC2W
)) == 0) {
2621 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_READ
)
2622 dbcr_dac(child
) |= DBCR_DAC2R
;
2623 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_WRITE
)
2624 dbcr_dac(child
) |= DBCR_DAC2W
;
2625 child
->thread
.debug
.dac2
= (unsigned long)bp_info
->addr
;
2626 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2628 child
->thread
.debug
.dvc2
=
2629 (unsigned long)bp_info
->condition_value
;
2630 child
->thread
.debug
.dbcr2
|=
2631 ((byte_enable
<< DBCR2_DVC2BE_SHIFT
) |
2632 (condition_mode
<< DBCR2_DVC2M_SHIFT
));
2637 child
->thread
.debug
.dbcr0
|= DBCR0_IDM
;
2638 child
->thread
.regs
->msr
|= MSR_DE
;
2643 static int del_dac(struct task_struct
*child
, int slot
)
2646 if ((dbcr_dac(child
) & (DBCR_DAC1R
| DBCR_DAC1W
)) == 0)
2649 child
->thread
.debug
.dac1
= 0;
2650 dbcr_dac(child
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
2651 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2652 if (child
->thread
.debug
.dbcr2
& DBCR2_DAC12MODE
) {
2653 child
->thread
.debug
.dac2
= 0;
2654 child
->thread
.debug
.dbcr2
&= ~DBCR2_DAC12MODE
;
2656 child
->thread
.debug
.dbcr2
&= ~(DBCR2_DVC1M
| DBCR2_DVC1BE
);
2658 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2659 child
->thread
.debug
.dvc1
= 0;
2661 } else if (slot
== 2) {
2662 if ((dbcr_dac(child
) & (DBCR_DAC2R
| DBCR_DAC2W
)) == 0)
2665 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2666 if (child
->thread
.debug
.dbcr2
& DBCR2_DAC12MODE
)
2667 /* Part of a range */
2669 child
->thread
.debug
.dbcr2
&= ~(DBCR2_DVC2M
| DBCR2_DVC2BE
);
2671 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2672 child
->thread
.debug
.dvc2
= 0;
2674 child
->thread
.debug
.dac2
= 0;
2675 dbcr_dac(child
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
2681 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2683 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2684 static int set_dac_range(struct task_struct
*child
,
2685 struct ppc_hw_breakpoint
*bp_info
)
2687 int mode
= bp_info
->addr_mode
& PPC_BREAKPOINT_MODE_MASK
;
2689 /* We don't allow range watchpoints to be used with DVC */
2690 if (bp_info
->condition_mode
)
2694 * Best effort to verify the address range. The user/supervisor bits
2695 * prevent trapping in kernel space, but let's fail on an obvious bad
2696 * range. The simple test on the mask is not fool-proof, and any
2697 * exclusive range will spill over into kernel space.
2699 if (bp_info
->addr
>= TASK_SIZE
)
2701 if (mode
== PPC_BREAKPOINT_MODE_MASK
) {
2703 * dac2 is a bitmask. Don't allow a mask that makes a
2704 * kernel space address from a valid dac1 value
2706 if (~((unsigned long)bp_info
->addr2
) >= TASK_SIZE
)
2710 * For range breakpoints, addr2 must also be a valid address
2712 if (bp_info
->addr2
>= TASK_SIZE
)
2716 if (child
->thread
.debug
.dbcr0
&
2717 (DBCR0_DAC1R
| DBCR0_DAC1W
| DBCR0_DAC2R
| DBCR0_DAC2W
))
2720 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_READ
)
2721 child
->thread
.debug
.dbcr0
|= (DBCR0_DAC1R
| DBCR0_IDM
);
2722 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_WRITE
)
2723 child
->thread
.debug
.dbcr0
|= (DBCR0_DAC1W
| DBCR0_IDM
);
2724 child
->thread
.debug
.dac1
= bp_info
->addr
;
2725 child
->thread
.debug
.dac2
= bp_info
->addr2
;
2726 if (mode
== PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
)
2727 child
->thread
.debug
.dbcr2
|= DBCR2_DAC12M
;
2728 else if (mode
== PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE
)
2729 child
->thread
.debug
.dbcr2
|= DBCR2_DAC12MX
;
2730 else /* PPC_BREAKPOINT_MODE_MASK */
2731 child
->thread
.debug
.dbcr2
|= DBCR2_DAC12MM
;
2732 child
->thread
.regs
->msr
|= MSR_DE
;
2736 #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
2738 static long ppc_set_hwdebug(struct task_struct
*child
,
2739 struct ppc_hw_breakpoint
*bp_info
)
2741 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2743 struct thread_struct
*thread
= &(child
->thread
);
2744 struct perf_event
*bp
;
2745 struct perf_event_attr attr
;
2746 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2747 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2748 struct arch_hw_breakpoint brk
;
2751 if (bp_info
->version
!= 1)
2753 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2755 * Check for invalid flags and combinations
2757 if ((bp_info
->trigger_type
== 0) ||
2758 (bp_info
->trigger_type
& ~(PPC_BREAKPOINT_TRIGGER_EXECUTE
|
2759 PPC_BREAKPOINT_TRIGGER_RW
)) ||
2760 (bp_info
->addr_mode
& ~PPC_BREAKPOINT_MODE_MASK
) ||
2761 (bp_info
->condition_mode
&
2762 ~(PPC_BREAKPOINT_CONDITION_MODE
|
2763 PPC_BREAKPOINT_CONDITION_BE_ALL
)))
2765 #if CONFIG_PPC_ADV_DEBUG_DVCS == 0
2766 if (bp_info
->condition_mode
!= PPC_BREAKPOINT_CONDITION_NONE
)
2770 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_EXECUTE
) {
2771 if ((bp_info
->trigger_type
!= PPC_BREAKPOINT_TRIGGER_EXECUTE
) ||
2772 (bp_info
->condition_mode
!= PPC_BREAKPOINT_CONDITION_NONE
))
2774 return set_instruction_bp(child
, bp_info
);
2776 if (bp_info
->addr_mode
== PPC_BREAKPOINT_MODE_EXACT
)
2777 return set_dac(child
, bp_info
);
2779 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2780 return set_dac_range(child
, bp_info
);
2784 #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2786 * We only support one data breakpoint
2788 if ((bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_RW
) == 0 ||
2789 (bp_info
->trigger_type
& ~PPC_BREAKPOINT_TRIGGER_RW
) != 0 ||
2790 bp_info
->condition_mode
!= PPC_BREAKPOINT_CONDITION_NONE
)
2793 if ((unsigned long)bp_info
->addr
>= TASK_SIZE
)
2796 brk
.address
= bp_info
->addr
& ~7UL;
2797 brk
.type
= HW_BRK_TYPE_TRANSLATE
;
2799 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_READ
)
2800 brk
.type
|= HW_BRK_TYPE_READ
;
2801 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_WRITE
)
2802 brk
.type
|= HW_BRK_TYPE_WRITE
;
2803 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2805 * Check if the request is for 'range' breakpoints. We can
2806 * support it if range < 8 bytes.
2808 if (bp_info
->addr_mode
== PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
)
2809 len
= bp_info
->addr2
- bp_info
->addr
;
2810 else if (bp_info
->addr_mode
== PPC_BREAKPOINT_MODE_EXACT
)
2814 bp
= thread
->ptrace_bps
[0];
2818 /* Create a new breakpoint request if one doesn't exist already */
2819 hw_breakpoint_init(&attr
);
2820 attr
.bp_addr
= (unsigned long)bp_info
->addr
& ~HW_BREAKPOINT_ALIGN
;
2822 arch_bp_generic_fields(brk
.type
, &attr
.bp_type
);
2824 thread
->ptrace_bps
[0] = bp
= register_user_hw_breakpoint(&attr
,
2825 ptrace_triggered
, NULL
, child
);
2827 thread
->ptrace_bps
[0] = NULL
;
2832 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2834 if (bp_info
->addr_mode
!= PPC_BREAKPOINT_MODE_EXACT
)
2837 if (child
->thread
.hw_brk
.address
)
2840 child
->thread
.hw_brk
= brk
;
2843 #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2846 static long ppc_del_hwdebug(struct task_struct
*child
, long data
)
2848 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2850 struct thread_struct
*thread
= &(child
->thread
);
2851 struct perf_event
*bp
;
2852 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2853 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2857 rc
= del_instruction_bp(child
, (int)data
);
2859 rc
= del_dac(child
, (int)data
- 4);
2862 if (!DBCR_ACTIVE_EVENTS(child
->thread
.debug
.dbcr0
,
2863 child
->thread
.debug
.dbcr1
)) {
2864 child
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
2865 child
->thread
.regs
->msr
&= ~MSR_DE
;
2873 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2874 bp
= thread
->ptrace_bps
[0];
2876 unregister_hw_breakpoint(bp
);
2877 thread
->ptrace_bps
[0] = NULL
;
2881 #else /* CONFIG_HAVE_HW_BREAKPOINT */
2882 if (child
->thread
.hw_brk
.address
== 0)
2885 child
->thread
.hw_brk
.address
= 0;
2886 child
->thread
.hw_brk
.type
= 0;
2887 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2893 long arch_ptrace(struct task_struct
*child
, long request
,
2894 unsigned long addr
, unsigned long data
)
2897 void __user
*datavp
= (void __user
*) data
;
2898 unsigned long __user
*datalp
= datavp
;
2901 /* read the word at location addr in the USER area. */
2902 case PTRACE_PEEKUSR
: {
2903 unsigned long index
, tmp
;
2906 /* convert to index and check */
2909 if ((addr
& 3) || (index
> PT_FPSCR
)
2910 || (child
->thread
.regs
== NULL
))
2913 if ((addr
& 7) || (index
> PT_FPSCR
))
2917 CHECK_FULL_REGS(child
->thread
.regs
);
2918 if (index
< PT_FPR0
) {
2919 ret
= ptrace_get_reg(child
, (int) index
, &tmp
);
2923 unsigned int fpidx
= index
- PT_FPR0
;
2925 flush_fp_to_thread(child
);
2926 if (fpidx
< (PT_FPSCR
- PT_FPR0
))
2927 memcpy(&tmp
, &child
->thread
.TS_FPR(fpidx
),
2930 tmp
= child
->thread
.fp_state
.fpscr
;
2932 ret
= put_user(tmp
, datalp
);
2936 /* write the word at location addr in the USER area */
2937 case PTRACE_POKEUSR
: {
2938 unsigned long index
;
2941 /* convert to index and check */
2944 if ((addr
& 3) || (index
> PT_FPSCR
)
2945 || (child
->thread
.regs
== NULL
))
2948 if ((addr
& 7) || (index
> PT_FPSCR
))
2952 CHECK_FULL_REGS(child
->thread
.regs
);
2953 if (index
< PT_FPR0
) {
2954 ret
= ptrace_put_reg(child
, index
, data
);
2956 unsigned int fpidx
= index
- PT_FPR0
;
2958 flush_fp_to_thread(child
);
2959 if (fpidx
< (PT_FPSCR
- PT_FPR0
))
2960 memcpy(&child
->thread
.TS_FPR(fpidx
), &data
,
2963 child
->thread
.fp_state
.fpscr
= data
;
2969 case PPC_PTRACE_GETHWDBGINFO
: {
2970 struct ppc_debug_info dbginfo
;
2972 dbginfo
.version
= 1;
2973 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2974 dbginfo
.num_instruction_bps
= CONFIG_PPC_ADV_DEBUG_IACS
;
2975 dbginfo
.num_data_bps
= CONFIG_PPC_ADV_DEBUG_DACS
;
2976 dbginfo
.num_condition_regs
= CONFIG_PPC_ADV_DEBUG_DVCS
;
2977 dbginfo
.data_bp_alignment
= 4;
2978 dbginfo
.sizeof_condition
= 4;
2979 dbginfo
.features
= PPC_DEBUG_FEATURE_INSN_BP_RANGE
|
2980 PPC_DEBUG_FEATURE_INSN_BP_MASK
;
2981 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2983 PPC_DEBUG_FEATURE_DATA_BP_RANGE
|
2984 PPC_DEBUG_FEATURE_DATA_BP_MASK
;
2986 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
2987 dbginfo
.num_instruction_bps
= 0;
2988 dbginfo
.num_data_bps
= 1;
2989 dbginfo
.num_condition_regs
= 0;
2991 dbginfo
.data_bp_alignment
= 8;
2993 dbginfo
.data_bp_alignment
= 4;
2995 dbginfo
.sizeof_condition
= 0;
2996 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2997 dbginfo
.features
= PPC_DEBUG_FEATURE_DATA_BP_RANGE
;
2998 if (cpu_has_feature(CPU_FTR_DAWR
))
2999 dbginfo
.features
|= PPC_DEBUG_FEATURE_DATA_BP_DAWR
;
3001 dbginfo
.features
= 0;
3002 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
3003 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
3005 if (!access_ok(VERIFY_WRITE
, datavp
,
3006 sizeof(struct ppc_debug_info
)))
3008 ret
= __copy_to_user(datavp
, &dbginfo
,
3009 sizeof(struct ppc_debug_info
)) ?
3014 case PPC_PTRACE_SETHWDEBUG
: {
3015 struct ppc_hw_breakpoint bp_info
;
3017 if (!access_ok(VERIFY_READ
, datavp
,
3018 sizeof(struct ppc_hw_breakpoint
)))
3020 ret
= __copy_from_user(&bp_info
, datavp
,
3021 sizeof(struct ppc_hw_breakpoint
)) ?
3024 ret
= ppc_set_hwdebug(child
, &bp_info
);
3028 case PPC_PTRACE_DELHWDEBUG
: {
3029 ret
= ppc_del_hwdebug(child
, data
);
3033 case PTRACE_GET_DEBUGREG
: {
3034 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
3035 unsigned long dabr_fake
;
3038 /* We only support one DABR and no IABRS at the moment */
3041 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
3042 ret
= put_user(child
->thread
.debug
.dac1
, datalp
);
3044 dabr_fake
= ((child
->thread
.hw_brk
.address
& (~HW_BRK_TYPE_DABR
)) |
3045 (child
->thread
.hw_brk
.type
& HW_BRK_TYPE_DABR
));
3046 ret
= put_user(dabr_fake
, datalp
);
3051 case PTRACE_SET_DEBUGREG
:
3052 ret
= ptrace_set_debugreg(child
, addr
, data
);
3056 case PTRACE_GETREGS64
:
3058 case PTRACE_GETREGS
: /* Get all pt_regs from the child. */
3059 return copy_regset_to_user(child
, &user_ppc_native_view
,
3061 0, sizeof(struct pt_regs
),
3065 case PTRACE_SETREGS64
:
3067 case PTRACE_SETREGS
: /* Set all gp regs in the child. */
3068 return copy_regset_from_user(child
, &user_ppc_native_view
,
3070 0, sizeof(struct pt_regs
),
3073 case PTRACE_GETFPREGS
: /* Get the child FPU state (FPR0...31 + FPSCR) */
3074 return copy_regset_to_user(child
, &user_ppc_native_view
,
3076 0, sizeof(elf_fpregset_t
),
3079 case PTRACE_SETFPREGS
: /* Set the child FPU state (FPR0...31 + FPSCR) */
3080 return copy_regset_from_user(child
, &user_ppc_native_view
,
3082 0, sizeof(elf_fpregset_t
),
3085 #ifdef CONFIG_ALTIVEC
3086 case PTRACE_GETVRREGS
:
3087 return copy_regset_to_user(child
, &user_ppc_native_view
,
3089 0, (33 * sizeof(vector128
) +
3093 case PTRACE_SETVRREGS
:
3094 return copy_regset_from_user(child
, &user_ppc_native_view
,
3096 0, (33 * sizeof(vector128
) +
3101 case PTRACE_GETVSRREGS
:
3102 return copy_regset_to_user(child
, &user_ppc_native_view
,
3104 0, 32 * sizeof(double),
3107 case PTRACE_SETVSRREGS
:
3108 return copy_regset_from_user(child
, &user_ppc_native_view
,
3110 0, 32 * sizeof(double),
3114 case PTRACE_GETEVRREGS
:
3115 /* Get the child spe register state. */
3116 return copy_regset_to_user(child
, &user_ppc_native_view
,
3117 REGSET_SPE
, 0, 35 * sizeof(u32
),
3120 case PTRACE_SETEVRREGS
:
3121 /* Set the child spe register state. */
3122 return copy_regset_from_user(child
, &user_ppc_native_view
,
3123 REGSET_SPE
, 0, 35 * sizeof(u32
),
3128 ret
= ptrace_request(child
, request
, addr
, data
);
3134 #ifdef CONFIG_SECCOMP
3135 static int do_seccomp(struct pt_regs
*regs
)
3137 if (!test_thread_flag(TIF_SECCOMP
))
3141 * The ABI we present to seccomp tracers is that r3 contains
3142 * the syscall return value and orig_gpr3 contains the first
3143 * syscall parameter. This is different to the ptrace ABI where
3144 * both r3 and orig_gpr3 contain the first syscall parameter.
3146 regs
->gpr
[3] = -ENOSYS
;
3149 * We use the __ version here because we have already checked
3150 * TIF_SECCOMP. If this fails, there is nothing left to do, we
3151 * have already loaded -ENOSYS into r3, or seccomp has put
3152 * something else in r3 (via SECCOMP_RET_ERRNO/TRACE).
3154 if (__secure_computing(NULL
))
3158 * The syscall was allowed by seccomp, restore the register
3159 * state to what audit expects.
3160 * Note that we use orig_gpr3, which means a seccomp tracer can
3161 * modify the first syscall parameter (in orig_gpr3) and also
3162 * allow the syscall to proceed.
3164 regs
->gpr
[3] = regs
->orig_gpr3
;
3169 static inline int do_seccomp(struct pt_regs
*regs
) { return 0; }
3170 #endif /* CONFIG_SECCOMP */
3173 * do_syscall_trace_enter() - Do syscall tracing on kernel entry.
3174 * @regs: the pt_regs of the task to trace (current)
3176 * Performs various types of tracing on syscall entry. This includes seccomp,
3177 * ptrace, syscall tracepoints and audit.
3179 * The pt_regs are potentially visible to userspace via ptrace, so their
3182 * One or more of the tracers may modify the contents of pt_regs, in particular
3183 * to modify arguments or even the syscall number itself.
3185 * It's also possible that a tracer can choose to reject the system call. In
3186 * that case this function will return an illegal syscall number, and will put
3187 * an appropriate return value in regs->r3.
3189 * Return: the (possibly changed) syscall number.
3191 long do_syscall_trace_enter(struct pt_regs
*regs
)
3196 * The tracer may decide to abort the syscall, if so tracehook
3197 * will return !0. Note that the tracer may also just change
3198 * regs->gpr[0] to an invalid syscall number, that is handled
3199 * below on the exit path.
3201 if (test_thread_flag(TIF_SYSCALL_TRACE
) &&
3202 tracehook_report_syscall_entry(regs
))
3205 /* Run seccomp after ptrace; allow it to set gpr[3]. */
3206 if (do_seccomp(regs
))
3209 /* Avoid trace and audit when syscall is invalid. */
3210 if (regs
->gpr
[0] >= NR_syscalls
)
3213 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT
)))
3214 trace_sys_enter(regs
, regs
->gpr
[0]);
3217 if (!is_32bit_task())
3218 audit_syscall_entry(regs
->gpr
[0], regs
->gpr
[3], regs
->gpr
[4],
3219 regs
->gpr
[5], regs
->gpr
[6]);
3222 audit_syscall_entry(regs
->gpr
[0],
3223 regs
->gpr
[3] & 0xffffffff,
3224 regs
->gpr
[4] & 0xffffffff,
3225 regs
->gpr
[5] & 0xffffffff,
3226 regs
->gpr
[6] & 0xffffffff);
3228 /* Return the possibly modified but valid syscall number */
3229 return regs
->gpr
[0];
3233 * If we are aborting explicitly, or if the syscall number is
3234 * now invalid, set the return value to -ENOSYS.
3236 regs
->gpr
[3] = -ENOSYS
;
3240 void do_syscall_trace_leave(struct pt_regs
*regs
)
3244 audit_syscall_exit(regs
);
3246 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT
)))
3247 trace_sys_exit(regs
, regs
->result
);
3249 step
= test_thread_flag(TIF_SINGLESTEP
);
3250 if (step
|| test_thread_flag(TIF_SYSCALL_TRACE
))
3251 tracehook_report_syscall_exit(regs
, step
);