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1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Security related flags and so on.
4 //
5 // Copyright 2018, Michael Ellerman, IBM Corporation.
6
7 #include <linux/kernel.h>
8 #include <linux/device.h>
9 #include <linux/seq_buf.h>
10
11 #include <asm/asm-prototypes.h>
12 #include <asm/code-patching.h>
13 #include <asm/debugfs.h>
14 #include <asm/security_features.h>
15 #include <asm/setup.h>
16
17
18 unsigned long powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
19
20 enum count_cache_flush_type {
21 COUNT_CACHE_FLUSH_NONE = 0x1,
22 COUNT_CACHE_FLUSH_SW = 0x2,
23 COUNT_CACHE_FLUSH_HW = 0x4,
24 };
25 static enum count_cache_flush_type count_cache_flush_type = COUNT_CACHE_FLUSH_NONE;
26
27 bool barrier_nospec_enabled;
28 static bool no_nospec;
29 static bool btb_flush_enabled;
30 #ifdef CONFIG_PPC_FSL_BOOK3E
31 static bool no_spectrev2;
32 #endif
33
34 static void enable_barrier_nospec(bool enable)
35 {
36 barrier_nospec_enabled = enable;
37 do_barrier_nospec_fixups(enable);
38 }
39
40 void setup_barrier_nospec(void)
41 {
42 bool enable;
43
44 /*
45 * It would make sense to check SEC_FTR_SPEC_BAR_ORI31 below as well.
46 * But there's a good reason not to. The two flags we check below are
47 * both are enabled by default in the kernel, so if the hcall is not
48 * functional they will be enabled.
49 * On a system where the host firmware has been updated (so the ori
50 * functions as a barrier), but on which the hypervisor (KVM/Qemu) has
51 * not been updated, we would like to enable the barrier. Dropping the
52 * check for SEC_FTR_SPEC_BAR_ORI31 achieves that. The only downside is
53 * we potentially enable the barrier on systems where the host firmware
54 * is not updated, but that's harmless as it's a no-op.
55 */
56 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
57 security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR);
58
59 if (!no_nospec)
60 enable_barrier_nospec(enable);
61 }
62
63 static int __init handle_nospectre_v1(char *p)
64 {
65 no_nospec = true;
66
67 return 0;
68 }
69 early_param("nospectre_v1", handle_nospectre_v1);
70
71 #ifdef CONFIG_DEBUG_FS
72 static int barrier_nospec_set(void *data, u64 val)
73 {
74 switch (val) {
75 case 0:
76 case 1:
77 break;
78 default:
79 return -EINVAL;
80 }
81
82 if (!!val == !!barrier_nospec_enabled)
83 return 0;
84
85 enable_barrier_nospec(!!val);
86
87 return 0;
88 }
89
90 static int barrier_nospec_get(void *data, u64 *val)
91 {
92 *val = barrier_nospec_enabled ? 1 : 0;
93 return 0;
94 }
95
96 DEFINE_SIMPLE_ATTRIBUTE(fops_barrier_nospec,
97 barrier_nospec_get, barrier_nospec_set, "%llu\n");
98
99 static __init int barrier_nospec_debugfs_init(void)
100 {
101 debugfs_create_file("barrier_nospec", 0600, powerpc_debugfs_root, NULL,
102 &fops_barrier_nospec);
103 return 0;
104 }
105 device_initcall(barrier_nospec_debugfs_init);
106 #endif /* CONFIG_DEBUG_FS */
107
108 #ifdef CONFIG_PPC_FSL_BOOK3E
109 static int __init handle_nospectre_v2(char *p)
110 {
111 no_spectrev2 = true;
112
113 return 0;
114 }
115 early_param("nospectre_v2", handle_nospectre_v2);
116 void setup_spectre_v2(void)
117 {
118 if (no_spectrev2)
119 do_btb_flush_fixups();
120 else
121 btb_flush_enabled = true;
122 }
123 #endif /* CONFIG_PPC_FSL_BOOK3E */
124
125 #ifdef CONFIG_PPC_BOOK3S_64
126 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
127 {
128 bool thread_priv;
129
130 thread_priv = security_ftr_enabled(SEC_FTR_L1D_THREAD_PRIV);
131
132 if (rfi_flush || thread_priv) {
133 struct seq_buf s;
134 seq_buf_init(&s, buf, PAGE_SIZE - 1);
135
136 seq_buf_printf(&s, "Mitigation: ");
137
138 if (rfi_flush)
139 seq_buf_printf(&s, "RFI Flush");
140
141 if (rfi_flush && thread_priv)
142 seq_buf_printf(&s, ", ");
143
144 if (thread_priv)
145 seq_buf_printf(&s, "L1D private per thread");
146
147 seq_buf_printf(&s, "\n");
148
149 return s.len;
150 }
151
152 if (!security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) &&
153 !security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR))
154 return sprintf(buf, "Not affected\n");
155
156 return sprintf(buf, "Vulnerable\n");
157 }
158 #endif
159
160 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
161 {
162 struct seq_buf s;
163
164 seq_buf_init(&s, buf, PAGE_SIZE - 1);
165
166 if (security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR)) {
167 if (barrier_nospec_enabled)
168 seq_buf_printf(&s, "Mitigation: __user pointer sanitization");
169 else
170 seq_buf_printf(&s, "Vulnerable");
171
172 if (security_ftr_enabled(SEC_FTR_SPEC_BAR_ORI31))
173 seq_buf_printf(&s, ", ori31 speculation barrier enabled");
174
175 seq_buf_printf(&s, "\n");
176 } else
177 seq_buf_printf(&s, "Not affected\n");
178
179 return s.len;
180 }
181
182 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
183 {
184 struct seq_buf s;
185 bool bcs, ccd;
186
187 seq_buf_init(&s, buf, PAGE_SIZE - 1);
188
189 bcs = security_ftr_enabled(SEC_FTR_BCCTRL_SERIALISED);
190 ccd = security_ftr_enabled(SEC_FTR_COUNT_CACHE_DISABLED);
191
192 if (bcs || ccd || count_cache_flush_type != COUNT_CACHE_FLUSH_NONE) {
193 bool comma = false;
194 seq_buf_printf(&s, "Mitigation: ");
195
196 if (bcs) {
197 seq_buf_printf(&s, "Indirect branch serialisation (kernel only)");
198 comma = true;
199 }
200
201 if (ccd) {
202 if (comma)
203 seq_buf_printf(&s, ", ");
204 seq_buf_printf(&s, "Indirect branch cache disabled");
205 comma = true;
206 }
207
208 if (comma)
209 seq_buf_printf(&s, ", ");
210
211 seq_buf_printf(&s, "Software count cache flush");
212
213 if (count_cache_flush_type == COUNT_CACHE_FLUSH_HW)
214 seq_buf_printf(&s, "(hardware accelerated)");
215 } else
216 seq_buf_printf(&s, "Vulnerable");
217
218 seq_buf_printf(&s, "\n");
219
220 return s.len;
221 }
222
223 #ifdef CONFIG_PPC_BOOK3S_64
224 /*
225 * Store-forwarding barrier support.
226 */
227
228 static enum stf_barrier_type stf_enabled_flush_types;
229 static bool no_stf_barrier;
230 bool stf_barrier;
231
232 static int __init handle_no_stf_barrier(char *p)
233 {
234 pr_info("stf-barrier: disabled on command line.");
235 no_stf_barrier = true;
236 return 0;
237 }
238
239 early_param("no_stf_barrier", handle_no_stf_barrier);
240
241 /* This is the generic flag used by other architectures */
242 static int __init handle_ssbd(char *p)
243 {
244 if (!p || strncmp(p, "auto", 5) == 0 || strncmp(p, "on", 2) == 0 ) {
245 /* Until firmware tells us, we have the barrier with auto */
246 return 0;
247 } else if (strncmp(p, "off", 3) == 0) {
248 handle_no_stf_barrier(NULL);
249 return 0;
250 } else
251 return 1;
252
253 return 0;
254 }
255 early_param("spec_store_bypass_disable", handle_ssbd);
256
257 /* This is the generic flag used by other architectures */
258 static int __init handle_no_ssbd(char *p)
259 {
260 handle_no_stf_barrier(NULL);
261 return 0;
262 }
263 early_param("nospec_store_bypass_disable", handle_no_ssbd);
264
265 static void stf_barrier_enable(bool enable)
266 {
267 if (enable)
268 do_stf_barrier_fixups(stf_enabled_flush_types);
269 else
270 do_stf_barrier_fixups(STF_BARRIER_NONE);
271
272 stf_barrier = enable;
273 }
274
275 void setup_stf_barrier(void)
276 {
277 enum stf_barrier_type type;
278 bool enable, hv;
279
280 hv = cpu_has_feature(CPU_FTR_HVMODE);
281
282 /* Default to fallback in case fw-features are not available */
283 if (cpu_has_feature(CPU_FTR_ARCH_300))
284 type = STF_BARRIER_EIEIO;
285 else if (cpu_has_feature(CPU_FTR_ARCH_207S))
286 type = STF_BARRIER_SYNC_ORI;
287 else if (cpu_has_feature(CPU_FTR_ARCH_206))
288 type = STF_BARRIER_FALLBACK;
289 else
290 type = STF_BARRIER_NONE;
291
292 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
293 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) ||
294 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) && hv));
295
296 if (type == STF_BARRIER_FALLBACK) {
297 pr_info("stf-barrier: fallback barrier available\n");
298 } else if (type == STF_BARRIER_SYNC_ORI) {
299 pr_info("stf-barrier: hwsync barrier available\n");
300 } else if (type == STF_BARRIER_EIEIO) {
301 pr_info("stf-barrier: eieio barrier available\n");
302 }
303
304 stf_enabled_flush_types = type;
305
306 if (!no_stf_barrier)
307 stf_barrier_enable(enable);
308 }
309
310 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
311 {
312 if (stf_barrier && stf_enabled_flush_types != STF_BARRIER_NONE) {
313 const char *type;
314 switch (stf_enabled_flush_types) {
315 case STF_BARRIER_EIEIO:
316 type = "eieio";
317 break;
318 case STF_BARRIER_SYNC_ORI:
319 type = "hwsync";
320 break;
321 case STF_BARRIER_FALLBACK:
322 type = "fallback";
323 break;
324 default:
325 type = "unknown";
326 }
327 return sprintf(buf, "Mitigation: Kernel entry/exit barrier (%s)\n", type);
328 }
329
330 if (!security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) &&
331 !security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR))
332 return sprintf(buf, "Not affected\n");
333
334 return sprintf(buf, "Vulnerable\n");
335 }
336
337 #ifdef CONFIG_DEBUG_FS
338 static int stf_barrier_set(void *data, u64 val)
339 {
340 bool enable;
341
342 if (val == 1)
343 enable = true;
344 else if (val == 0)
345 enable = false;
346 else
347 return -EINVAL;
348
349 /* Only do anything if we're changing state */
350 if (enable != stf_barrier)
351 stf_barrier_enable(enable);
352
353 return 0;
354 }
355
356 static int stf_barrier_get(void *data, u64 *val)
357 {
358 *val = stf_barrier ? 1 : 0;
359 return 0;
360 }
361
362 DEFINE_SIMPLE_ATTRIBUTE(fops_stf_barrier, stf_barrier_get, stf_barrier_set, "%llu\n");
363
364 static __init int stf_barrier_debugfs_init(void)
365 {
366 debugfs_create_file("stf_barrier", 0600, powerpc_debugfs_root, NULL, &fops_stf_barrier);
367 return 0;
368 }
369 device_initcall(stf_barrier_debugfs_init);
370 #endif /* CONFIG_DEBUG_FS */
371
372 static void toggle_count_cache_flush(bool enable)
373 {
374 if (!enable || !security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE)) {
375 patch_instruction_site(&patch__call_flush_count_cache, PPC_INST_NOP);
376 count_cache_flush_type = COUNT_CACHE_FLUSH_NONE;
377 pr_info("count-cache-flush: software flush disabled.\n");
378 return;
379 }
380
381 patch_branch_site(&patch__call_flush_count_cache,
382 (u64)&flush_count_cache, BRANCH_SET_LINK);
383
384 if (!security_ftr_enabled(SEC_FTR_BCCTR_FLUSH_ASSIST)) {
385 count_cache_flush_type = COUNT_CACHE_FLUSH_SW;
386 pr_info("count-cache-flush: full software flush sequence enabled.\n");
387 return;
388 }
389
390 patch_instruction_site(&patch__flush_count_cache_return, PPC_INST_BLR);
391 count_cache_flush_type = COUNT_CACHE_FLUSH_HW;
392 pr_info("count-cache-flush: hardware assisted flush sequence enabled\n");
393 }
394
395 void setup_count_cache_flush(void)
396 {
397 toggle_count_cache_flush(true);
398 }
399
400 #ifdef CONFIG_DEBUG_FS
401 static int count_cache_flush_set(void *data, u64 val)
402 {
403 bool enable;
404
405 if (val == 1)
406 enable = true;
407 else if (val == 0)
408 enable = false;
409 else
410 return -EINVAL;
411
412 toggle_count_cache_flush(enable);
413
414 return 0;
415 }
416
417 static int count_cache_flush_get(void *data, u64 *val)
418 {
419 if (count_cache_flush_type == COUNT_CACHE_FLUSH_NONE)
420 *val = 0;
421 else
422 *val = 1;
423
424 return 0;
425 }
426
427 DEFINE_SIMPLE_ATTRIBUTE(fops_count_cache_flush, count_cache_flush_get,
428 count_cache_flush_set, "%llu\n");
429
430 static __init int count_cache_flush_debugfs_init(void)
431 {
432 debugfs_create_file("count_cache_flush", 0600, powerpc_debugfs_root,
433 NULL, &fops_count_cache_flush);
434 return 0;
435 }
436 device_initcall(count_cache_flush_debugfs_init);
437 #endif /* CONFIG_DEBUG_FS */
438 #endif /* CONFIG_PPC_BOOK3S_64 */