3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/hugetlb.h>
39 #include <linux/memory.h>
42 #include <asm/kdump.h>
44 #include <asm/processor.h>
45 #include <asm/pgtable.h>
48 #include <asm/machdep.h>
51 #include <asm/cputable.h>
52 #include <asm/sections.h>
53 #include <asm/btext.h>
54 #include <asm/nvram.h>
55 #include <asm/setup.h>
57 #include <asm/iommu.h>
58 #include <asm/serial.h>
59 #include <asm/cache.h>
62 #include <asm/firmware.h>
65 #include <asm/kexec.h>
66 #include <asm/mmu_context.h>
67 #include <asm/code-patching.h>
68 #include <asm/kvm_ppc.h>
69 #include <asm/hugetlb.h>
70 #include <asm/epapr_hcalls.h>
73 #define DBG(fmt...) udbg_printf(fmt)
78 int spinning_secondaries
;
81 /* Pick defaults since we might want to patch instructions
82 * before we've read this from the device tree.
84 struct ppc64_caches ppc64_caches
= {
90 EXPORT_SYMBOL_GPL(ppc64_caches
);
93 * These are used in binfmt_elf.c to put aux entries on the stack
94 * for each elf executable being started.
100 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
101 static void setup_tlb_core_data(void)
105 BUILD_BUG_ON(offsetof(struct tlb_core_data
, lock
) != 0);
107 for_each_possible_cpu(cpu
) {
108 int first
= cpu_first_thread_sibling(cpu
);
110 paca
[cpu
].tcd_ptr
= &paca
[first
].tcd
;
113 * If we have threads, we need either tlbsrx.
114 * or e6500 tablewalk mode, or else TLB handlers
115 * will be racy and could produce duplicate entries.
117 if (smt_enabled_at_boot
>= 2 &&
118 !mmu_has_feature(MMU_FTR_USE_TLBRSRV
) &&
119 book3e_htw_mode
!= PPC_HTW_E6500
) {
120 /* Should we panic instead? */
121 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
127 static void setup_tlb_core_data(void)
134 static char *smt_enabled_cmdline
;
136 /* Look for ibm,smt-enabled OF option */
137 static void check_smt_enabled(void)
139 struct device_node
*dn
;
140 const char *smt_option
;
142 /* Default to enabling all threads */
143 smt_enabled_at_boot
= threads_per_core
;
145 /* Allow the command line to overrule the OF option */
146 if (smt_enabled_cmdline
) {
147 if (!strcmp(smt_enabled_cmdline
, "on"))
148 smt_enabled_at_boot
= threads_per_core
;
149 else if (!strcmp(smt_enabled_cmdline
, "off"))
150 smt_enabled_at_boot
= 0;
155 rc
= kstrtoint(smt_enabled_cmdline
, 10, &smt
);
157 smt_enabled_at_boot
=
158 min(threads_per_core
, smt
);
161 dn
= of_find_node_by_path("/options");
163 smt_option
= of_get_property(dn
, "ibm,smt-enabled",
167 if (!strcmp(smt_option
, "on"))
168 smt_enabled_at_boot
= threads_per_core
;
169 else if (!strcmp(smt_option
, "off"))
170 smt_enabled_at_boot
= 0;
178 /* Look for smt-enabled= cmdline option */
179 static int __init
early_smt_enabled(char *p
)
181 smt_enabled_cmdline
= p
;
184 early_param("smt-enabled", early_smt_enabled
);
187 #define check_smt_enabled()
188 #endif /* CONFIG_SMP */
190 /** Fix up paca fields required for the boot cpu */
191 static void fixup_boot_paca(void)
193 /* The boot cpu is started */
194 get_paca()->cpu_start
= 1;
195 /* Allow percpu accesses to work until we setup percpu data */
196 get_paca()->data_offset
= 0;
199 static void cpu_ready_for_interrupts(void)
201 /* Set IR and DR in PACA MSR */
202 get_paca()->kernel_msr
= MSR_KERNEL
;
205 * Enable AIL if supported, and we are in hypervisor mode. If we are
206 * not in hypervisor mode, we enable relocation-on interrupts later
207 * in pSeries_setup_arch() using the H_SET_MODE hcall.
209 if (cpu_has_feature(CPU_FTR_HVMODE
) &&
210 cpu_has_feature(CPU_FTR_ARCH_207S
)) {
211 unsigned long lpcr
= mfspr(SPRN_LPCR
);
212 mtspr(SPRN_LPCR
, lpcr
| LPCR_AIL_3
);
217 * Early initialization entry point. This is called by head.S
218 * with MMU translation disabled. We rely on the "feature" of
219 * the CPU that ignores the top 2 bits of the address in real
220 * mode so we can access kernel globals normally provided we
221 * only toy with things in the RMO region. From here, we do
222 * some early parsing of the device-tree to setup out MEMBLOCK
223 * data structures, and allocate & initialize the hash table
224 * and segment tables so we can start running with translation
227 * It is this function which will call the probe() callback of
228 * the various platform types and copy the matching one to the
229 * global ppc_md structure. Your platform can eventually do
230 * some very early initializations from the probe() routine, but
231 * this is not recommended, be very careful as, for example, the
232 * device-tree is not accessible via normal means at this point.
235 void __init
early_setup(unsigned long dt_ptr
)
237 static __initdata
struct paca_struct boot_paca
;
239 /* -------- printk is _NOT_ safe to use here ! ------- */
241 /* Identify CPU type */
242 identify_cpu(0, mfspr(SPRN_PVR
));
244 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
245 initialise_paca(&boot_paca
, 0);
246 setup_paca(&boot_paca
);
249 /* Initialize lockdep early or else spinlocks will blow */
252 /* -------- printk is now safe to use ------- */
254 /* Enable early debugging if any specified (see udbg.h) */
257 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr
);
260 * Do early initialization using the flattened device
261 * tree, such as retrieving the physical memory map or
262 * calculating/retrieving the hash table size.
264 early_init_devtree(__va(dt_ptr
));
266 epapr_paravirt_early_init();
268 /* Now we know the logical id of our boot cpu, setup the paca. */
269 setup_paca(&paca
[boot_cpuid
]);
272 /* Probe the machine type */
275 setup_kdump_trampoline();
277 DBG("Found, Initializing memory management...\n");
279 /* Initialize the hash table or TLB handling */
283 * At this point, we can let interrupts switch to virtual mode
284 * (the MMU has been setup), so adjust the MSR in the PACA to
285 * have IR and DR set and enable AIL if it exists
287 cpu_ready_for_interrupts();
289 /* Reserve large chunks of memory for use by CMA for KVM */
293 * Reserve any gigantic pages requested on the command line.
294 * memblock needs to have been initialized by the time this is
295 * called since this will reserve memory.
297 reserve_hugetlb_gpages();
299 DBG(" <- early_setup()\n");
301 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
303 * This needs to be done *last* (after the above DBG() even)
305 * Right after we return from this function, we turn on the MMU
306 * which means the real-mode access trick that btext does will
307 * no longer work, it needs to switch to using a real MMU
308 * mapping. This call will ensure that it does
311 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
315 void early_setup_secondary(void)
317 /* Mark interrupts enabled in PACA */
318 get_paca()->soft_enabled
= 0;
320 /* Initialize the hash table or TLB handling */
321 early_init_mmu_secondary();
324 * At this point, we can let interrupts switch to virtual mode
325 * (the MMU has been setup), so adjust the MSR in the PACA to
326 * have IR and DR set.
328 cpu_ready_for_interrupts();
331 #endif /* CONFIG_SMP */
333 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
334 void smp_release_cpus(void)
339 DBG(" -> smp_release_cpus()\n");
341 /* All secondary cpus are spinning on a common spinloop, release them
342 * all now so they can start to spin on their individual paca
343 * spinloops. For non SMP kernels, the secondary cpus never get out
344 * of the common spinloop.
347 ptr
= (unsigned long *)((unsigned long)&__secondary_hold_spinloop
349 *ptr
= ppc_function_entry(generic_secondary_smp_init
);
351 /* And wait a bit for them to catch up */
352 for (i
= 0; i
< 100000; i
++) {
355 if (spinning_secondaries
== 0)
359 DBG("spinning_secondaries = %d\n", spinning_secondaries
);
361 DBG(" <- smp_release_cpus()\n");
363 #endif /* CONFIG_SMP || CONFIG_KEXEC */
366 * Initialize some remaining members of the ppc64_caches and systemcfg
368 * (at least until we get rid of them completely). This is mostly some
369 * cache informations about the CPU that will be used by cache flush
370 * routines and/or provided to userland
372 static void __init
initialize_cache_info(void)
374 struct device_node
*np
;
375 unsigned long num_cpus
= 0;
377 DBG(" -> initialize_cache_info()\n");
379 for_each_node_by_type(np
, "cpu") {
383 * We're assuming *all* of the CPUs have the same
384 * d-cache and i-cache sizes... -Peter
387 const __be32
*sizep
, *lsizep
;
391 lsize
= cur_cpu_spec
->dcache_bsize
;
392 sizep
= of_get_property(np
, "d-cache-size", NULL
);
394 size
= be32_to_cpu(*sizep
);
395 lsizep
= of_get_property(np
, "d-cache-block-size",
397 /* fallback if block size missing */
399 lsizep
= of_get_property(np
,
403 lsize
= be32_to_cpu(*lsizep
);
404 if (sizep
== NULL
|| lsizep
== NULL
)
405 DBG("Argh, can't find dcache properties ! "
406 "sizep: %p, lsizep: %p\n", sizep
, lsizep
);
408 ppc64_caches
.dsize
= size
;
409 ppc64_caches
.dline_size
= lsize
;
410 ppc64_caches
.log_dline_size
= __ilog2(lsize
);
411 ppc64_caches
.dlines_per_page
= PAGE_SIZE
/ lsize
;
414 lsize
= cur_cpu_spec
->icache_bsize
;
415 sizep
= of_get_property(np
, "i-cache-size", NULL
);
417 size
= be32_to_cpu(*sizep
);
418 lsizep
= of_get_property(np
, "i-cache-block-size",
421 lsizep
= of_get_property(np
,
425 lsize
= be32_to_cpu(*lsizep
);
426 if (sizep
== NULL
|| lsizep
== NULL
)
427 DBG("Argh, can't find icache properties ! "
428 "sizep: %p, lsizep: %p\n", sizep
, lsizep
);
430 ppc64_caches
.isize
= size
;
431 ppc64_caches
.iline_size
= lsize
;
432 ppc64_caches
.log_iline_size
= __ilog2(lsize
);
433 ppc64_caches
.ilines_per_page
= PAGE_SIZE
/ lsize
;
437 DBG(" <- initialize_cache_info()\n");
442 * Do some initial setup of the system. The parameters are those which
443 * were passed in from the bootloader.
445 void __init
setup_system(void)
447 DBG(" -> setup_system()\n");
449 /* Apply the CPUs-specific and firmware specific fixups to kernel
450 * text (nop out sections not relevant to this CPU or this firmware)
452 do_feature_fixups(cur_cpu_spec
->cpu_features
,
453 &__start___ftr_fixup
, &__stop___ftr_fixup
);
454 do_feature_fixups(cur_cpu_spec
->mmu_features
,
455 &__start___mmu_ftr_fixup
, &__stop___mmu_ftr_fixup
);
456 do_feature_fixups(powerpc_firmware_features
,
457 &__start___fw_ftr_fixup
, &__stop___fw_ftr_fixup
);
458 do_lwsync_fixups(cur_cpu_spec
->cpu_features
,
459 &__start___lwsync_fixup
, &__stop___lwsync_fixup
);
463 * Unflatten the device-tree passed by prom_init or kexec
465 unflatten_device_tree();
468 * Fill the ppc64_caches & systemcfg structures with informations
469 * retrieved from the device-tree.
471 initialize_cache_info();
473 #ifdef CONFIG_PPC_RTAS
475 * Initialize RTAS if available
478 #endif /* CONFIG_PPC_RTAS */
481 * Check if we have an initrd provided via the device-tree
486 * Do some platform specific early initializations, that includes
487 * setting up the hash table pointers. It also sets up some interrupt-mapping
488 * related options that will be used by finish_device_tree()
490 if (ppc_md
.init_early
)
494 * We can discover serial ports now since the above did setup the
495 * hash table management for us, thus ioremap works. We do that early
496 * so that further code can be debugged
498 find_legacy_serial_ports();
501 * Register early console
503 register_early_udbg_console();
510 smp_setup_cpu_maps();
512 setup_tlb_core_data();
515 * Freescale Book3e parts spin in a loop provided by firmware,
516 * so smp_release_cpus() does nothing for them
518 #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_FSL_BOOK3E)
519 /* Release secondary cpus out of their spinloops at 0x60 now that
520 * we can map physical -> logical CPU ids
525 pr_info("Starting Linux PPC64 %s\n", init_utsname()->version
);
527 pr_info("-----------------------------------------------------\n");
528 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size
);
529 pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size());
531 if (ppc64_caches
.dline_size
!= 0x80)
532 pr_info("dcache_line_size = 0x%x\n", ppc64_caches
.dline_size
);
533 if (ppc64_caches
.iline_size
!= 0x80)
534 pr_info("icache_line_size = 0x%x\n", ppc64_caches
.iline_size
);
536 pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec
->cpu_features
);
537 pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE
);
538 pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS
);
539 pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec
->cpu_user_features
,
540 cur_cpu_spec
->cpu_user_features2
);
541 pr_info("mmu_features = 0x%08x\n", cur_cpu_spec
->mmu_features
);
542 pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features
);
544 #ifdef CONFIG_PPC_STD_MMU_64
546 pr_info("htab_address = 0x%p\n", htab_address
);
548 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask
);
551 if (PHYSICAL_START
> 0)
552 pr_info("physical_start = 0x%llx\n",
553 (unsigned long long)PHYSICAL_START
);
554 pr_info("-----------------------------------------------------\n");
556 DBG(" <- setup_system()\n");
559 /* This returns the limit below which memory accesses to the linear
560 * mapping are guarnateed not to cause a TLB or SLB miss. This is
561 * used to allocate interrupt or emergency stacks for which our
562 * exception entry path doesn't deal with being interrupted.
564 static u64
safe_stack_limit(void)
566 #ifdef CONFIG_PPC_BOOK3E
567 /* Freescale BookE bolts the entire linear mapping */
568 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E
))
569 return linear_map_top
;
570 /* Other BookE, we assume the first GB is bolted */
573 /* BookS, the first segment is bolted */
574 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
575 return 1UL << SID_SHIFT_1T
;
576 return 1UL << SID_SHIFT
;
580 static void __init
irqstack_early_init(void)
582 u64 limit
= safe_stack_limit();
586 * Interrupt stacks must be in the first segment since we
587 * cannot afford to take SLB misses on them.
589 for_each_possible_cpu(i
) {
590 softirq_ctx
[i
] = (struct thread_info
*)
591 __va(memblock_alloc_base(THREAD_SIZE
,
592 THREAD_SIZE
, limit
));
593 hardirq_ctx
[i
] = (struct thread_info
*)
594 __va(memblock_alloc_base(THREAD_SIZE
,
595 THREAD_SIZE
, limit
));
599 #ifdef CONFIG_PPC_BOOK3E
600 static void __init
exc_lvl_early_init(void)
605 for_each_possible_cpu(i
) {
606 sp
= memblock_alloc(THREAD_SIZE
, THREAD_SIZE
);
607 critirq_ctx
[i
] = (struct thread_info
*)__va(sp
);
608 paca
[i
].crit_kstack
= __va(sp
+ THREAD_SIZE
);
610 sp
= memblock_alloc(THREAD_SIZE
, THREAD_SIZE
);
611 dbgirq_ctx
[i
] = (struct thread_info
*)__va(sp
);
612 paca
[i
].dbg_kstack
= __va(sp
+ THREAD_SIZE
);
614 sp
= memblock_alloc(THREAD_SIZE
, THREAD_SIZE
);
615 mcheckirq_ctx
[i
] = (struct thread_info
*)__va(sp
);
616 paca
[i
].mc_kstack
= __va(sp
+ THREAD_SIZE
);
619 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC
))
620 patch_exception(0x040, exc_debug_debug_book3e
);
623 #define exc_lvl_early_init()
627 * Stack space used when we detect a bad kernel stack pointer, and
628 * early in SMP boots before relocation is enabled. Exclusive emergency
629 * stack for machine checks.
631 static void __init
emergency_stack_init(void)
637 * Emergency stacks must be under 256MB, we cannot afford to take
638 * SLB misses on them. The ABI also requires them to be 128-byte
641 * Since we use these as temporary stacks during secondary CPU
642 * bringup, we need to get at them in real mode. This means they
643 * must also be within the RMO region.
645 limit
= min(safe_stack_limit(), ppc64_rma_size
);
647 for_each_possible_cpu(i
) {
649 sp
= memblock_alloc_base(THREAD_SIZE
, THREAD_SIZE
, limit
);
651 paca
[i
].emergency_sp
= __va(sp
);
653 #ifdef CONFIG_PPC_BOOK3S_64
654 /* emergency stack for machine check exception handling. */
655 sp
= memblock_alloc_base(THREAD_SIZE
, THREAD_SIZE
, limit
);
657 paca
[i
].mc_emergency_sp
= __va(sp
);
663 * Called into from start_kernel this initializes memblock, which is used
664 * to manage page allocation until mem_init is called.
666 void __init
setup_arch(char **cmdline_p
)
668 *cmdline_p
= boot_command_line
;
671 * Set cache line size based on type of cpu as a default.
672 * Systems with OF can look in the properties on the cpu node(s)
673 * for a possibly more accurate value.
675 dcache_bsize
= ppc64_caches
.dline_size
;
676 icache_bsize
= ppc64_caches
.iline_size
;
681 init_mm
.start_code
= (unsigned long)_stext
;
682 init_mm
.end_code
= (unsigned long) _etext
;
683 init_mm
.end_data
= (unsigned long) _edata
;
684 init_mm
.brk
= klimit
;
685 #ifdef CONFIG_PPC_64K_PAGES
686 init_mm
.context
.pte_frag
= NULL
;
688 irqstack_early_init();
689 exc_lvl_early_init();
690 emergency_stack_init();
694 #ifdef CONFIG_DUMMY_CONSOLE
695 conswitchp
= &dummy_con
;
698 if (ppc_md
.setup_arch
)
703 /* Initialize the MMU context management stuff */
706 /* Interrupt code needs to be 64K-aligned */
707 if ((unsigned long)_stext
& 0xffff)
708 panic("Kernelbase not 64K-aligned (0x%lx)!\n",
709 (unsigned long)_stext
);
713 #define PCPU_DYN_SIZE ()
715 static void * __init
pcpu_fc_alloc(unsigned int cpu
, size_t size
, size_t align
)
717 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu
)), size
, align
,
718 __pa(MAX_DMA_ADDRESS
));
721 static void __init
pcpu_fc_free(void *ptr
, size_t size
)
723 free_bootmem(__pa(ptr
), size
);
726 static int pcpu_cpu_distance(unsigned int from
, unsigned int to
)
728 if (cpu_to_node(from
) == cpu_to_node(to
))
729 return LOCAL_DISTANCE
;
731 return REMOTE_DISTANCE
;
734 unsigned long __per_cpu_offset
[NR_CPUS
] __read_mostly
;
735 EXPORT_SYMBOL(__per_cpu_offset
);
737 void __init
setup_per_cpu_areas(void)
739 const size_t dyn_size
= PERCPU_MODULE_RESERVE
+ PERCPU_DYNAMIC_RESERVE
;
746 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
747 * to group units. For larger mappings, use 1M atom which
748 * should be large enough to contain a number of units.
750 if (mmu_linear_psize
== MMU_PAGE_4K
)
751 atom_size
= PAGE_SIZE
;
755 rc
= pcpu_embed_first_chunk(0, dyn_size
, atom_size
, pcpu_cpu_distance
,
756 pcpu_fc_alloc
, pcpu_fc_free
);
758 panic("cannot initialize percpu area (err=%d)", rc
);
760 delta
= (unsigned long)pcpu_base_addr
- (unsigned long)__per_cpu_start
;
761 for_each_possible_cpu(cpu
) {
762 __per_cpu_offset
[cpu
] = delta
+ pcpu_unit_offsets
[cpu
];
763 paca
[cpu
].data_offset
= __per_cpu_offset
[cpu
];
768 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
769 unsigned long memory_block_size_bytes(void)
771 if (ppc_md
.memory_block_size
)
772 return ppc_md
.memory_block_size();
774 return MIN_MEMORY_BLOCK_SIZE
;
778 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
779 struct ppc_pci_io ppc_pci_io
;
780 EXPORT_SYMBOL(ppc_pci_io
);