3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/memory.h>
39 #include <linux/nmi.h>
41 #include <asm/debugfs.h>
43 #include <asm/kdump.h>
45 #include <asm/processor.h>
46 #include <asm/pgtable.h>
49 #include <asm/machdep.h>
52 #include <asm/cputable.h>
53 #include <asm/dt_cpu_ftrs.h>
54 #include <asm/sections.h>
55 #include <asm/btext.h>
56 #include <asm/nvram.h>
57 #include <asm/setup.h>
59 #include <asm/iommu.h>
60 #include <asm/serial.h>
61 #include <asm/cache.h>
64 #include <asm/firmware.h>
67 #include <asm/kexec.h>
68 #include <asm/code-patching.h>
69 #include <asm/livepatch.h>
71 #include <asm/cputhreads.h>
76 #define DBG(fmt...) udbg_printf(fmt)
81 int spinning_secondaries
;
84 struct ppc64_caches ppc64_caches
= {
94 EXPORT_SYMBOL_GPL(ppc64_caches
);
96 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
97 void __init
setup_tlb_core_data(void)
101 BUILD_BUG_ON(offsetof(struct tlb_core_data
, lock
) != 0);
103 for_each_possible_cpu(cpu
) {
104 int first
= cpu_first_thread_sibling(cpu
);
107 * If we boot via kdump on a non-primary thread,
108 * make sure we point at the thread that actually
111 if (cpu_first_thread_sibling(boot_cpuid
) == first
)
114 paca
[cpu
].tcd_ptr
= &paca
[first
].tcd
;
117 * If we have threads, we need either tlbsrx.
118 * or e6500 tablewalk mode, or else TLB handlers
119 * will be racy and could produce duplicate entries.
120 * Should we panic instead?
122 WARN_ONCE(smt_enabled_at_boot
>= 2 &&
123 !mmu_has_feature(MMU_FTR_USE_TLBRSRV
) &&
124 book3e_htw_mode
!= PPC_HTW_E6500
,
125 "%s: unsupported MMU configuration\n", __func__
);
132 static char *smt_enabled_cmdline
;
134 /* Look for ibm,smt-enabled OF option */
135 void __init
check_smt_enabled(void)
137 struct device_node
*dn
;
138 const char *smt_option
;
140 /* Default to enabling all threads */
141 smt_enabled_at_boot
= threads_per_core
;
143 /* Allow the command line to overrule the OF option */
144 if (smt_enabled_cmdline
) {
145 if (!strcmp(smt_enabled_cmdline
, "on"))
146 smt_enabled_at_boot
= threads_per_core
;
147 else if (!strcmp(smt_enabled_cmdline
, "off"))
148 smt_enabled_at_boot
= 0;
153 rc
= kstrtoint(smt_enabled_cmdline
, 10, &smt
);
155 smt_enabled_at_boot
=
156 min(threads_per_core
, smt
);
159 dn
= of_find_node_by_path("/options");
161 smt_option
= of_get_property(dn
, "ibm,smt-enabled",
165 if (!strcmp(smt_option
, "on"))
166 smt_enabled_at_boot
= threads_per_core
;
167 else if (!strcmp(smt_option
, "off"))
168 smt_enabled_at_boot
= 0;
176 /* Look for smt-enabled= cmdline option */
177 static int __init
early_smt_enabled(char *p
)
179 smt_enabled_cmdline
= p
;
182 early_param("smt-enabled", early_smt_enabled
);
184 #endif /* CONFIG_SMP */
186 /** Fix up paca fields required for the boot cpu */
187 static void __init
fixup_boot_paca(void)
189 /* The boot cpu is started */
190 get_paca()->cpu_start
= 1;
191 /* Allow percpu accesses to work until we setup percpu data */
192 get_paca()->data_offset
= 0;
195 static void __init
configure_exceptions(void)
198 * Setup the trampolines from the lowmem exception vectors
199 * to the kdump kernel when not using a relocatable kernel.
201 setup_kdump_trampoline();
203 /* Under a PAPR hypervisor, we need hypercalls */
204 if (firmware_has_feature(FW_FEATURE_SET_MODE
)) {
205 /* Enable AIL if possible */
206 pseries_enable_reloc_on_exc();
209 * Tell the hypervisor that we want our exceptions to
210 * be taken in little endian mode.
212 * We don't call this for big endian as our calling convention
213 * makes us always enter in BE, and the call may fail under
214 * some circumstances with kdump.
216 #ifdef __LITTLE_ENDIAN__
217 pseries_little_endian_exceptions();
220 /* Set endian mode using OPAL */
221 if (firmware_has_feature(FW_FEATURE_OPAL
))
222 opal_configure_cores();
224 /* AIL on native is done in cpu_ready_for_interrupts() */
228 static void cpu_ready_for_interrupts(void)
231 * Enable AIL if supported, and we are in hypervisor mode. This
232 * is called once for every processor.
234 * If we are not in hypervisor mode the job is done once for
235 * the whole partition in configure_exceptions().
237 if (cpu_has_feature(CPU_FTR_HVMODE
) &&
238 cpu_has_feature(CPU_FTR_ARCH_207S
)) {
239 unsigned long lpcr
= mfspr(SPRN_LPCR
);
240 mtspr(SPRN_LPCR
, lpcr
| LPCR_AIL_3
);
244 * Fixup HFSCR:TM based on CPU features. The bit is set by our
245 * early asm init because at that point we haven't updated our
246 * CPU features from firmware and device-tree. Here we have,
249 if (cpu_has_feature(CPU_FTR_HVMODE
) && !cpu_has_feature(CPU_FTR_TM_COMP
))
250 mtspr(SPRN_HFSCR
, mfspr(SPRN_HFSCR
) & ~HFSCR_TM
);
252 /* Set IR and DR in PACA MSR */
253 get_paca()->kernel_msr
= MSR_KERNEL
;
257 * Early initialization entry point. This is called by head.S
258 * with MMU translation disabled. We rely on the "feature" of
259 * the CPU that ignores the top 2 bits of the address in real
260 * mode so we can access kernel globals normally provided we
261 * only toy with things in the RMO region. From here, we do
262 * some early parsing of the device-tree to setup out MEMBLOCK
263 * data structures, and allocate & initialize the hash table
264 * and segment tables so we can start running with translation
267 * It is this function which will call the probe() callback of
268 * the various platform types and copy the matching one to the
269 * global ppc_md structure. Your platform can eventually do
270 * some very early initializations from the probe() routine, but
271 * this is not recommended, be very careful as, for example, the
272 * device-tree is not accessible via normal means at this point.
275 void __init
early_setup(unsigned long dt_ptr
)
277 static __initdata
struct paca_struct boot_paca
;
279 /* -------- printk is _NOT_ safe to use here ! ------- */
281 /* Try new device tree based feature discovery ... */
282 if (!dt_cpu_ftrs_init(__va(dt_ptr
)))
283 /* Otherwise use the old style CPU table */
284 identify_cpu(0, mfspr(SPRN_PVR
));
286 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
287 initialise_paca(&boot_paca
, 0);
288 setup_paca(&boot_paca
);
291 /* -------- printk is now safe to use ------- */
293 /* Enable early debugging if any specified (see udbg.h) */
296 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr
);
299 * Do early initialization using the flattened device
300 * tree, such as retrieving the physical memory map or
301 * calculating/retrieving the hash table size.
303 early_init_devtree(__va(dt_ptr
));
305 /* Now we know the logical id of our boot cpu, setup the paca. */
306 setup_paca(&paca
[boot_cpuid
]);
310 * Configure exception handlers. This include setting up trampolines
311 * if needed, setting exception endian mode, etc...
313 configure_exceptions();
315 /* Apply all the dynamic patching */
316 apply_feature_fixups();
317 setup_feature_keys();
319 /* Initialize the hash table or TLB handling */
323 * After firmware and early platform setup code has set things up,
324 * we note the SPR values for configurable control/performance
325 * registers, and use those as initial defaults.
327 record_spr_defaults();
330 * At this point, we can let interrupts switch to virtual mode
331 * (the MMU has been setup), so adjust the MSR in the PACA to
332 * have IR and DR set and enable AIL if it exists
334 cpu_ready_for_interrupts();
336 DBG(" <- early_setup()\n");
338 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
340 * This needs to be done *last* (after the above DBG() even)
342 * Right after we return from this function, we turn on the MMU
343 * which means the real-mode access trick that btext does will
344 * no longer work, it needs to switch to using a real MMU
345 * mapping. This call will ensure that it does
348 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
352 void early_setup_secondary(void)
354 /* Mark interrupts disabled in PACA */
355 get_paca()->soft_enabled
= 0;
357 /* Initialize the hash table or TLB handling */
358 early_init_mmu_secondary();
361 * At this point, we can let interrupts switch to virtual mode
362 * (the MMU has been setup), so adjust the MSR in the PACA to
363 * have IR and DR set.
365 cpu_ready_for_interrupts();
368 #endif /* CONFIG_SMP */
370 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
371 static bool use_spinloop(void)
373 if (IS_ENABLED(CONFIG_PPC_BOOK3S
)) {
375 * See comments in head_64.S -- not all platforms insert
376 * secondaries at __secondary_hold and wait at the spin
379 if (firmware_has_feature(FW_FEATURE_OPAL
))
385 * When book3e boots from kexec, the ePAPR spin table does
388 return of_property_read_bool(of_chosen
, "linux,booted-from-kexec");
391 void smp_release_cpus(void)
399 DBG(" -> smp_release_cpus()\n");
401 /* All secondary cpus are spinning on a common spinloop, release them
402 * all now so they can start to spin on their individual paca
403 * spinloops. For non SMP kernels, the secondary cpus never get out
404 * of the common spinloop.
407 ptr
= (unsigned long *)((unsigned long)&__secondary_hold_spinloop
409 *ptr
= ppc_function_entry(generic_secondary_smp_init
);
411 /* And wait a bit for them to catch up */
412 for (i
= 0; i
< 100000; i
++) {
415 if (spinning_secondaries
== 0)
419 DBG("spinning_secondaries = %d\n", spinning_secondaries
);
421 DBG(" <- smp_release_cpus()\n");
423 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
426 * Initialize some remaining members of the ppc64_caches and systemcfg
428 * (at least until we get rid of them completely). This is mostly some
429 * cache informations about the CPU that will be used by cache flush
430 * routines and/or provided to userland
433 static void init_cache_info(struct ppc_cache_info
*info
, u32 size
, u32 lsize
,
438 info
->line_size
= lsize
;
439 info
->block_size
= bsize
;
440 info
->log_block_size
= __ilog2(bsize
);
442 info
->blocks_per_page
= PAGE_SIZE
/ bsize
;
444 info
->blocks_per_page
= 0;
447 info
->assoc
= 0xffff;
449 info
->assoc
= size
/ (sets
* lsize
);
452 static bool __init
parse_cache_info(struct device_node
*np
,
454 struct ppc_cache_info
*info
)
456 static const char *ipropnames
[] __initdata
= {
459 "i-cache-block-size",
462 static const char *dpropnames
[] __initdata
= {
465 "d-cache-block-size",
468 const char **propnames
= icache
? ipropnames
: dpropnames
;
469 const __be32
*sizep
, *lsizep
, *bsizep
, *setsp
;
470 u32 size
, lsize
, bsize
, sets
;
475 lsize
= bsize
= cur_cpu_spec
->dcache_bsize
;
476 sizep
= of_get_property(np
, propnames
[0], NULL
);
478 size
= be32_to_cpu(*sizep
);
479 setsp
= of_get_property(np
, propnames
[1], NULL
);
481 sets
= be32_to_cpu(*setsp
);
482 bsizep
= of_get_property(np
, propnames
[2], NULL
);
483 lsizep
= of_get_property(np
, propnames
[3], NULL
);
487 lsize
= be32_to_cpu(*lsizep
);
489 bsize
= be32_to_cpu(*bsizep
);
490 if (sizep
== NULL
|| bsizep
== NULL
|| lsizep
== NULL
)
494 * OF is weird .. it represents fully associative caches
495 * as "1 way" which doesn't make much sense and doesn't
496 * leave room for direct mapped. We'll assume that 0
497 * in OF means direct mapped for that reason.
504 init_cache_info(info
, size
, lsize
, bsize
, sets
);
509 void __init
initialize_cache_info(void)
511 struct device_node
*cpu
= NULL
, *l2
, *l3
= NULL
;
514 DBG(" -> initialize_cache_info()\n");
517 * All shipping POWER8 machines have a firmware bug that
518 * puts incorrect information in the device-tree. This will
519 * be (hopefully) fixed for future chips but for now hard
520 * code the values if we are running on one of these
522 pvr
= PVR_VER(mfspr(SPRN_PVR
));
523 if (pvr
== PVR_POWER8
|| pvr
== PVR_POWER8E
||
524 pvr
== PVR_POWER8NVL
) {
525 /* size lsize blk sets */
526 init_cache_info(&ppc64_caches
.l1i
, 0x8000, 128, 128, 32);
527 init_cache_info(&ppc64_caches
.l1d
, 0x10000, 128, 128, 64);
528 init_cache_info(&ppc64_caches
.l2
, 0x80000, 128, 0, 512);
529 init_cache_info(&ppc64_caches
.l3
, 0x800000, 128, 0, 8192);
531 cpu
= of_find_node_by_type(NULL
, "cpu");
534 * We're assuming *all* of the CPUs have the same
535 * d-cache and i-cache sizes... -Peter
538 if (!parse_cache_info(cpu
, false, &ppc64_caches
.l1d
))
539 DBG("Argh, can't find dcache properties !\n");
541 if (!parse_cache_info(cpu
, true, &ppc64_caches
.l1i
))
542 DBG("Argh, can't find icache properties !\n");
545 * Try to find the L2 and L3 if any. Assume they are
546 * unified and use the D-side properties.
548 l2
= of_find_next_cache_node(cpu
);
551 parse_cache_info(l2
, false, &ppc64_caches
.l2
);
552 l3
= of_find_next_cache_node(l2
);
556 parse_cache_info(l3
, false, &ppc64_caches
.l3
);
561 /* For use by binfmt_elf */
562 dcache_bsize
= ppc64_caches
.l1d
.block_size
;
563 icache_bsize
= ppc64_caches
.l1i
.block_size
;
565 cur_cpu_spec
->dcache_bsize
= dcache_bsize
;
566 cur_cpu_spec
->icache_bsize
= icache_bsize
;
568 DBG(" <- initialize_cache_info()\n");
571 /* This returns the limit below which memory accesses to the linear
572 * mapping are guarnateed not to cause a TLB or SLB miss. This is
573 * used to allocate interrupt or emergency stacks for which our
574 * exception entry path doesn't deal with being interrupted.
576 static __init u64
safe_stack_limit(void)
578 #ifdef CONFIG_PPC_BOOK3E
579 /* Freescale BookE bolts the entire linear mapping */
580 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E
))
581 return linear_map_top
;
582 /* Other BookE, we assume the first GB is bolted */
585 if (early_radix_enabled())
588 /* BookS, the first segment is bolted */
589 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
590 return 1UL << SID_SHIFT_1T
;
591 return 1UL << SID_SHIFT
;
595 void __init
irqstack_early_init(void)
597 u64 limit
= safe_stack_limit();
601 * Interrupt stacks must be in the first segment since we
602 * cannot afford to take SLB misses on them. They are not
603 * accessed in realmode.
605 for_each_possible_cpu(i
) {
606 softirq_ctx
[i
] = (struct thread_info
*)
607 __va(memblock_alloc_base(THREAD_SIZE
,
608 THREAD_SIZE
, limit
));
609 hardirq_ctx
[i
] = (struct thread_info
*)
610 __va(memblock_alloc_base(THREAD_SIZE
,
611 THREAD_SIZE
, limit
));
615 #ifdef CONFIG_PPC_BOOK3E
616 void __init
exc_lvl_early_init(void)
621 for_each_possible_cpu(i
) {
622 sp
= memblock_alloc(THREAD_SIZE
, THREAD_SIZE
);
623 critirq_ctx
[i
] = (struct thread_info
*)__va(sp
);
624 paca
[i
].crit_kstack
= __va(sp
+ THREAD_SIZE
);
626 sp
= memblock_alloc(THREAD_SIZE
, THREAD_SIZE
);
627 dbgirq_ctx
[i
] = (struct thread_info
*)__va(sp
);
628 paca
[i
].dbg_kstack
= __va(sp
+ THREAD_SIZE
);
630 sp
= memblock_alloc(THREAD_SIZE
, THREAD_SIZE
);
631 mcheckirq_ctx
[i
] = (struct thread_info
*)__va(sp
);
632 paca
[i
].mc_kstack
= __va(sp
+ THREAD_SIZE
);
635 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC
))
636 patch_exception(0x040, exc_debug_debug_book3e
);
641 * Emergency stacks are used for a range of things, from asynchronous
642 * NMIs (system reset, machine check) to synchronous, process context.
643 * We set preempt_count to zero, even though that isn't necessarily correct. To
644 * get the right value we'd need to copy it from the previous thread_info, but
645 * doing that might fault causing more problems.
646 * TODO: what to do with accounting?
648 static void emerg_stack_init_thread_info(struct thread_info
*ti
, int cpu
)
652 ti
->preempt_count
= 0;
655 klp_init_thread_info(ti
);
659 * Stack space used when we detect a bad kernel stack pointer, and
660 * early in SMP boots before relocation is enabled. Exclusive emergency
661 * stack for machine checks.
663 void __init
emergency_stack_init(void)
669 * Emergency stacks must be under 256MB, we cannot afford to take
670 * SLB misses on them. The ABI also requires them to be 128-byte
673 * Since we use these as temporary stacks during secondary CPU
674 * bringup, machine check, system reset, and HMI, we need to get
675 * at them in real mode. This means they must also be within the RMO
678 * The IRQ stacks allocated elsewhere in this file are zeroed and
679 * initialized in kernel/irq.c. These are initialized here in order
680 * to have emergency stacks available as early as possible.
682 limit
= min(safe_stack_limit(), ppc64_rma_size
);
684 for_each_possible_cpu(i
) {
685 struct thread_info
*ti
;
686 ti
= __va(memblock_alloc_base(THREAD_SIZE
, THREAD_SIZE
, limit
));
687 memset(ti
, 0, THREAD_SIZE
);
688 emerg_stack_init_thread_info(ti
, i
);
689 paca
[i
].emergency_sp
= (void *)ti
+ THREAD_SIZE
;
691 #ifdef CONFIG_PPC_BOOK3S_64
692 /* emergency stack for NMI exception handling. */
693 ti
= __va(memblock_alloc_base(THREAD_SIZE
, THREAD_SIZE
, limit
));
694 memset(ti
, 0, THREAD_SIZE
);
695 emerg_stack_init_thread_info(ti
, i
);
696 paca
[i
].nmi_emergency_sp
= (void *)ti
+ THREAD_SIZE
;
698 /* emergency stack for machine check exception handling. */
699 ti
= __va(memblock_alloc_base(THREAD_SIZE
, THREAD_SIZE
, limit
));
700 memset(ti
, 0, THREAD_SIZE
);
701 emerg_stack_init_thread_info(ti
, i
);
702 paca
[i
].mc_emergency_sp
= (void *)ti
+ THREAD_SIZE
;
708 #define PCPU_DYN_SIZE ()
710 static void * __init
pcpu_fc_alloc(unsigned int cpu
, size_t size
, size_t align
)
712 return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu
)), size
, align
,
713 __pa(MAX_DMA_ADDRESS
));
716 static void __init
pcpu_fc_free(void *ptr
, size_t size
)
718 free_bootmem(__pa(ptr
), size
);
721 static int pcpu_cpu_distance(unsigned int from
, unsigned int to
)
723 if (early_cpu_to_node(from
) == early_cpu_to_node(to
))
724 return LOCAL_DISTANCE
;
726 return REMOTE_DISTANCE
;
729 unsigned long __per_cpu_offset
[NR_CPUS
] __read_mostly
;
730 EXPORT_SYMBOL(__per_cpu_offset
);
732 void __init
setup_per_cpu_areas(void)
734 const size_t dyn_size
= PERCPU_MODULE_RESERVE
+ PERCPU_DYNAMIC_RESERVE
;
741 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
742 * to group units. For larger mappings, use 1M atom which
743 * should be large enough to contain a number of units.
745 if (mmu_linear_psize
== MMU_PAGE_4K
)
746 atom_size
= PAGE_SIZE
;
750 rc
= pcpu_embed_first_chunk(0, dyn_size
, atom_size
, pcpu_cpu_distance
,
751 pcpu_fc_alloc
, pcpu_fc_free
);
753 panic("cannot initialize percpu area (err=%d)", rc
);
755 delta
= (unsigned long)pcpu_base_addr
- (unsigned long)__per_cpu_start
;
756 for_each_possible_cpu(cpu
) {
757 __per_cpu_offset
[cpu
] = delta
+ pcpu_unit_offsets
[cpu
];
758 paca
[cpu
].data_offset
= __per_cpu_offset
[cpu
];
763 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
764 unsigned long memory_block_size_bytes(void)
766 if (ppc_md
.memory_block_size
)
767 return ppc_md
.memory_block_size();
769 return MIN_MEMORY_BLOCK_SIZE
;
773 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
774 struct ppc_pci_io ppc_pci_io
;
775 EXPORT_SYMBOL(ppc_pci_io
);
778 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
779 u64
hw_nmi_get_sample_period(int watchdog_thresh
)
781 return ppc_proc_freq
* watchdog_thresh
;
786 * The perf based hardlockup detector breaks PMU event based branches, so
787 * disable it by default. Book3S has a soft-nmi hardlockup detector based
788 * on the decrementer interrupt, so it does not suffer from this problem.
790 * It is likely to get false positives in VM guests, so disable it there
793 static int __init
disable_hardlockup_detector(void)
795 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
796 hardlockup_detector_disable();
798 if (firmware_has_feature(FW_FEATURE_LPAR
))
799 hardlockup_detector_disable();
804 early_initcall(disable_hardlockup_detector
);
806 #ifdef CONFIG_PPC_BOOK3S_64
807 static enum l1d_flush_type enabled_flush_types
;
808 static void *l1d_flush_fallback_area
;
809 static bool no_rfi_flush
;
812 static int __init
handle_no_rfi_flush(char *p
)
814 pr_info("rfi-flush: disabled on command line.");
818 early_param("no_rfi_flush", handle_no_rfi_flush
);
821 * The RFI flush is not KPTI, but because users will see doco that says to use
822 * nopti we hijack that option here to also disable the RFI flush.
824 static int __init
handle_no_pti(char *p
)
826 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
827 handle_no_rfi_flush(NULL
);
830 early_param("nopti", handle_no_pti
);
832 static void do_nothing(void *unused
)
835 * We don't need to do the flush explicitly, just enter+exit kernel is
836 * sufficient, the RFI exit handlers will do the right thing.
840 void rfi_flush_enable(bool enable
)
843 do_rfi_flush_fixups(enabled_flush_types
);
844 on_each_cpu(do_nothing
, NULL
, 1);
846 do_rfi_flush_fixups(L1D_FLUSH_NONE
);
851 static void __ref
init_fallback_flush(void)
856 /* Only allocate the fallback flush area once (at boot time). */
857 if (l1d_flush_fallback_area
)
860 l1d_size
= ppc64_caches
.l1d
.size
;
863 * If there is no d-cache-size property in the device tree, l1d_size
864 * could be zero. That leads to the loop in the asm wrapping around to
865 * 2^64-1, and then walking off the end of the fallback area and
866 * eventually causing a page fault which is fatal. Just default to
867 * something vaguely sane.
870 l1d_size
= (64 * 1024);
872 limit
= min(safe_stack_limit(), ppc64_rma_size
);
875 * Align to L1d size, and size it at 2x L1d size, to catch possible
876 * hardware prefetch runoff. We don't have a recipe for load patterns to
877 * reliably avoid the prefetcher.
879 l1d_flush_fallback_area
= __va(memblock_alloc_base(l1d_size
* 2, l1d_size
, limit
));
880 memset(l1d_flush_fallback_area
, 0, l1d_size
* 2);
882 for_each_possible_cpu(cpu
) {
883 paca
[cpu
].rfi_flush_fallback_area
= l1d_flush_fallback_area
;
884 paca
[cpu
].l1d_flush_size
= l1d_size
;
888 void setup_rfi_flush(enum l1d_flush_type types
, bool enable
)
890 if (types
& L1D_FLUSH_FALLBACK
) {
891 pr_info("rfi-flush: fallback displacement flush available\n");
892 init_fallback_flush();
895 if (types
& L1D_FLUSH_ORI
)
896 pr_info("rfi-flush: ori type flush available\n");
898 if (types
& L1D_FLUSH_MTTRIG
)
899 pr_info("rfi-flush: mttrig type flush available\n");
901 enabled_flush_types
= types
;
904 rfi_flush_enable(enable
);
907 #ifdef CONFIG_DEBUG_FS
908 static int rfi_flush_set(void *data
, u64 val
)
919 /* Only do anything if we're changing state */
920 if (enable
!= rfi_flush
)
921 rfi_flush_enable(enable
);
926 static int rfi_flush_get(void *data
, u64
*val
)
928 *val
= rfi_flush
? 1 : 0;
932 DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush
, rfi_flush_get
, rfi_flush_set
, "%llu\n");
934 static __init
int rfi_flush_debugfs_init(void)
936 debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root
, NULL
, &fops_rfi_flush
);
939 device_initcall(rfi_flush_debugfs_init
);
941 #endif /* CONFIG_PPC_BOOK3S_64 */