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1 /*
2 * SMP support for ppc.
3 *
4 * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great
5 * deal of code from the sparc and intel versions.
6 *
7 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
8 *
9 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and
10 * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18 #undef DEBUG
19
20 #include <linux/kernel.h>
21 #include <linux/export.h>
22 #include <linux/sched/mm.h>
23 #include <linux/sched/topology.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/spinlock.h>
29 #include <linux/cache.h>
30 #include <linux/err.h>
31 #include <linux/device.h>
32 #include <linux/cpu.h>
33 #include <linux/notifier.h>
34 #include <linux/topology.h>
35 #include <linux/profile.h>
36 #include <linux/processor.h>
37
38 #include <asm/ptrace.h>
39 #include <linux/atomic.h>
40 #include <asm/irq.h>
41 #include <asm/hw_irq.h>
42 #include <asm/kvm_ppc.h>
43 #include <asm/dbell.h>
44 #include <asm/page.h>
45 #include <asm/pgtable.h>
46 #include <asm/prom.h>
47 #include <asm/smp.h>
48 #include <asm/time.h>
49 #include <asm/machdep.h>
50 #include <asm/cputhreads.h>
51 #include <asm/cputable.h>
52 #include <asm/mpic.h>
53 #include <asm/vdso_datapage.h>
54 #ifdef CONFIG_PPC64
55 #include <asm/paca.h>
56 #endif
57 #include <asm/vdso.h>
58 #include <asm/debug.h>
59 #include <asm/kexec.h>
60 #include <asm/asm-prototypes.h>
61 #include <asm/cpu_has_feature.h>
62
63 #ifdef DEBUG
64 #include <asm/udbg.h>
65 #define DBG(fmt...) udbg_printf(fmt)
66 #else
67 #define DBG(fmt...)
68 #endif
69
70 #ifdef CONFIG_HOTPLUG_CPU
71 /* State of each CPU during hotplug phases */
72 static DEFINE_PER_CPU(int, cpu_state) = { 0 };
73 #endif
74
75 struct thread_info *secondary_ti;
76
77 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
78 DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map);
79 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
80
81 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
82 EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map);
83 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
84
85 /* SMP operations for this machine */
86 struct smp_ops_t *smp_ops;
87
88 /* Can't be static due to PowerMac hackery */
89 volatile unsigned int cpu_callin_map[NR_CPUS];
90
91 int smt_enabled_at_boot = 1;
92
93 /*
94 * Returns 1 if the specified cpu should be brought up during boot.
95 * Used to inhibit booting threads if they've been disabled or
96 * limited on the command line
97 */
98 int smp_generic_cpu_bootable(unsigned int nr)
99 {
100 /* Special case - we inhibit secondary thread startup
101 * during boot if the user requests it.
102 */
103 if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) {
104 if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
105 return 0;
106 if (smt_enabled_at_boot
107 && cpu_thread_in_core(nr) >= smt_enabled_at_boot)
108 return 0;
109 }
110
111 return 1;
112 }
113
114
115 #ifdef CONFIG_PPC64
116 int smp_generic_kick_cpu(int nr)
117 {
118 if (nr < 0 || nr >= nr_cpu_ids)
119 return -EINVAL;
120
121 /*
122 * The processor is currently spinning, waiting for the
123 * cpu_start field to become non-zero After we set cpu_start,
124 * the processor will continue on to secondary_start
125 */
126 if (!paca[nr].cpu_start) {
127 paca[nr].cpu_start = 1;
128 smp_mb();
129 return 0;
130 }
131
132 #ifdef CONFIG_HOTPLUG_CPU
133 /*
134 * Ok it's not there, so it might be soft-unplugged, let's
135 * try to bring it back
136 */
137 generic_set_cpu_up(nr);
138 smp_wmb();
139 smp_send_reschedule(nr);
140 #endif /* CONFIG_HOTPLUG_CPU */
141
142 return 0;
143 }
144 #endif /* CONFIG_PPC64 */
145
146 static irqreturn_t call_function_action(int irq, void *data)
147 {
148 generic_smp_call_function_interrupt();
149 return IRQ_HANDLED;
150 }
151
152 static irqreturn_t reschedule_action(int irq, void *data)
153 {
154 scheduler_ipi();
155 return IRQ_HANDLED;
156 }
157
158 static irqreturn_t tick_broadcast_ipi_action(int irq, void *data)
159 {
160 tick_broadcast_ipi_handler();
161 return IRQ_HANDLED;
162 }
163
164 #ifdef CONFIG_NMI_IPI
165 static irqreturn_t nmi_ipi_action(int irq, void *data)
166 {
167 smp_handle_nmi_ipi(get_irq_regs());
168 return IRQ_HANDLED;
169 }
170 #endif
171
172 static irq_handler_t smp_ipi_action[] = {
173 [PPC_MSG_CALL_FUNCTION] = call_function_action,
174 [PPC_MSG_RESCHEDULE] = reschedule_action,
175 [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action,
176 #ifdef CONFIG_NMI_IPI
177 [PPC_MSG_NMI_IPI] = nmi_ipi_action,
178 #endif
179 };
180
181 /*
182 * The NMI IPI is a fallback and not truly non-maskable. It is simpler
183 * than going through the call function infrastructure, and strongly
184 * serialized, so it is more appropriate for debugging.
185 */
186 const char *smp_ipi_name[] = {
187 [PPC_MSG_CALL_FUNCTION] = "ipi call function",
188 [PPC_MSG_RESCHEDULE] = "ipi reschedule",
189 [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast",
190 [PPC_MSG_NMI_IPI] = "nmi ipi",
191 };
192
193 /* optional function to request ipi, for controllers with >= 4 ipis */
194 int smp_request_message_ipi(int virq, int msg)
195 {
196 int err;
197
198 if (msg < 0 || msg > PPC_MSG_NMI_IPI)
199 return -EINVAL;
200 #ifndef CONFIG_NMI_IPI
201 if (msg == PPC_MSG_NMI_IPI)
202 return 1;
203 #endif
204
205 err = request_irq(virq, smp_ipi_action[msg],
206 IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND,
207 smp_ipi_name[msg], NULL);
208 WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n",
209 virq, smp_ipi_name[msg], err);
210
211 return err;
212 }
213
214 #ifdef CONFIG_PPC_SMP_MUXED_IPI
215 struct cpu_messages {
216 long messages; /* current messages */
217 };
218 static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message);
219
220 void smp_muxed_ipi_set_message(int cpu, int msg)
221 {
222 struct cpu_messages *info = &per_cpu(ipi_message, cpu);
223 char *message = (char *)&info->messages;
224
225 /*
226 * Order previous accesses before accesses in the IPI handler.
227 */
228 smp_mb();
229 message[msg] = 1;
230 }
231
232 void smp_muxed_ipi_message_pass(int cpu, int msg)
233 {
234 smp_muxed_ipi_set_message(cpu, msg);
235
236 /*
237 * cause_ipi functions are required to include a full barrier
238 * before doing whatever causes the IPI.
239 */
240 smp_ops->cause_ipi(cpu);
241 }
242
243 #ifdef __BIG_ENDIAN__
244 #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A)))
245 #else
246 #define IPI_MESSAGE(A) (1uL << (8 * (A)))
247 #endif
248
249 irqreturn_t smp_ipi_demux(void)
250 {
251 mb(); /* order any irq clear */
252
253 return smp_ipi_demux_relaxed();
254 }
255
256 /* sync-free variant. Callers should ensure synchronization */
257 irqreturn_t smp_ipi_demux_relaxed(void)
258 {
259 struct cpu_messages *info;
260 unsigned long all;
261
262 info = this_cpu_ptr(&ipi_message);
263 do {
264 all = xchg(&info->messages, 0);
265 #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE)
266 /*
267 * Must check for PPC_MSG_RM_HOST_ACTION messages
268 * before PPC_MSG_CALL_FUNCTION messages because when
269 * a VM is destroyed, we call kick_all_cpus_sync()
270 * to ensure that any pending PPC_MSG_RM_HOST_ACTION
271 * messages have completed before we free any VCPUs.
272 */
273 if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION))
274 kvmppc_xics_ipi_action();
275 #endif
276 if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION))
277 generic_smp_call_function_interrupt();
278 if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE))
279 scheduler_ipi();
280 if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST))
281 tick_broadcast_ipi_handler();
282 #ifdef CONFIG_NMI_IPI
283 if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI))
284 nmi_ipi_action(0, NULL);
285 #endif
286 } while (info->messages);
287
288 return IRQ_HANDLED;
289 }
290 #endif /* CONFIG_PPC_SMP_MUXED_IPI */
291
292 static inline void do_message_pass(int cpu, int msg)
293 {
294 if (smp_ops->message_pass)
295 smp_ops->message_pass(cpu, msg);
296 #ifdef CONFIG_PPC_SMP_MUXED_IPI
297 else
298 smp_muxed_ipi_message_pass(cpu, msg);
299 #endif
300 }
301
302 void smp_send_reschedule(int cpu)
303 {
304 if (likely(smp_ops))
305 do_message_pass(cpu, PPC_MSG_RESCHEDULE);
306 }
307 EXPORT_SYMBOL_GPL(smp_send_reschedule);
308
309 void arch_send_call_function_single_ipi(int cpu)
310 {
311 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
312 }
313
314 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
315 {
316 unsigned int cpu;
317
318 for_each_cpu(cpu, mask)
319 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
320 }
321
322 #ifdef CONFIG_NMI_IPI
323
324 /*
325 * "NMI IPI" system.
326 *
327 * NMI IPIs may not be recoverable, so should not be used as ongoing part of
328 * a running system. They can be used for crash, debug, halt/reboot, etc.
329 *
330 * NMI IPIs are globally single threaded. No more than one in progress at
331 * any time.
332 *
333 * The IPI call waits with interrupts disabled until all targets enter the
334 * NMI handler, then the call returns.
335 *
336 * No new NMI can be initiated until targets exit the handler.
337 *
338 * The IPI call may time out without all targets entering the NMI handler.
339 * In that case, there is some logic to recover (and ignore subsequent
340 * NMI interrupts that may eventually be raised), but the platform interrupt
341 * handler may not be able to distinguish this from other exception causes,
342 * which may cause a crash.
343 */
344
345 static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0);
346 static struct cpumask nmi_ipi_pending_mask;
347 static int nmi_ipi_busy_count = 0;
348 static void (*nmi_ipi_function)(struct pt_regs *) = NULL;
349
350 static void nmi_ipi_lock_start(unsigned long *flags)
351 {
352 raw_local_irq_save(*flags);
353 hard_irq_disable();
354 while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) {
355 raw_local_irq_restore(*flags);
356 spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0);
357 raw_local_irq_save(*flags);
358 hard_irq_disable();
359 }
360 }
361
362 static void nmi_ipi_lock(void)
363 {
364 while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1)
365 spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0);
366 }
367
368 static void nmi_ipi_unlock(void)
369 {
370 smp_mb();
371 WARN_ON(atomic_read(&__nmi_ipi_lock) != 1);
372 atomic_set(&__nmi_ipi_lock, 0);
373 }
374
375 static void nmi_ipi_unlock_end(unsigned long *flags)
376 {
377 nmi_ipi_unlock();
378 raw_local_irq_restore(*flags);
379 }
380
381 /*
382 * Platform NMI handler calls this to ack
383 */
384 int smp_handle_nmi_ipi(struct pt_regs *regs)
385 {
386 void (*fn)(struct pt_regs *);
387 unsigned long flags;
388 int me = raw_smp_processor_id();
389 int ret = 0;
390
391 /*
392 * Unexpected NMIs are possible here because the interrupt may not
393 * be able to distinguish NMI IPIs from other types of NMIs, or
394 * because the caller may have timed out.
395 */
396 nmi_ipi_lock_start(&flags);
397 if (!nmi_ipi_busy_count)
398 goto out;
399 if (!cpumask_test_cpu(me, &nmi_ipi_pending_mask))
400 goto out;
401
402 fn = nmi_ipi_function;
403 if (!fn)
404 goto out;
405
406 cpumask_clear_cpu(me, &nmi_ipi_pending_mask);
407 nmi_ipi_busy_count++;
408 nmi_ipi_unlock();
409
410 ret = 1;
411
412 fn(regs);
413
414 nmi_ipi_lock();
415 nmi_ipi_busy_count--;
416 out:
417 nmi_ipi_unlock_end(&flags);
418
419 return ret;
420 }
421
422 static void do_smp_send_nmi_ipi(int cpu)
423 {
424 if (smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu))
425 return;
426
427 if (cpu >= 0) {
428 do_message_pass(cpu, PPC_MSG_NMI_IPI);
429 } else {
430 int c;
431
432 for_each_online_cpu(c) {
433 if (c == raw_smp_processor_id())
434 continue;
435 do_message_pass(c, PPC_MSG_NMI_IPI);
436 }
437 }
438 }
439
440 void smp_flush_nmi_ipi(u64 delay_us)
441 {
442 unsigned long flags;
443
444 nmi_ipi_lock_start(&flags);
445 while (nmi_ipi_busy_count) {
446 nmi_ipi_unlock_end(&flags);
447 udelay(1);
448 if (delay_us) {
449 delay_us--;
450 if (!delay_us)
451 return;
452 }
453 nmi_ipi_lock_start(&flags);
454 }
455 nmi_ipi_unlock_end(&flags);
456 }
457
458 /*
459 * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS.
460 * - fn is the target callback function.
461 * - delay_us > 0 is the delay before giving up waiting for targets to
462 * enter the handler, == 0 specifies indefinite delay.
463 */
464 int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us)
465 {
466 unsigned long flags;
467 int me = raw_smp_processor_id();
468 int ret = 1;
469
470 BUG_ON(cpu == me);
471 BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS);
472
473 if (unlikely(!smp_ops))
474 return 0;
475
476 /* Take the nmi_ipi_busy count/lock with interrupts hard disabled */
477 nmi_ipi_lock_start(&flags);
478 while (nmi_ipi_busy_count) {
479 nmi_ipi_unlock_end(&flags);
480 spin_until_cond(nmi_ipi_busy_count == 0);
481 nmi_ipi_lock_start(&flags);
482 }
483
484 nmi_ipi_function = fn;
485
486 if (cpu < 0) {
487 /* ALL_OTHERS */
488 cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask);
489 cpumask_clear_cpu(me, &nmi_ipi_pending_mask);
490 } else {
491 /* cpumask starts clear */
492 cpumask_set_cpu(cpu, &nmi_ipi_pending_mask);
493 }
494 nmi_ipi_busy_count++;
495 nmi_ipi_unlock();
496
497 do_smp_send_nmi_ipi(cpu);
498
499 while (!cpumask_empty(&nmi_ipi_pending_mask)) {
500 udelay(1);
501 if (delay_us) {
502 delay_us--;
503 if (!delay_us)
504 break;
505 }
506 }
507
508 nmi_ipi_lock();
509 if (!cpumask_empty(&nmi_ipi_pending_mask)) {
510 /* Could not gather all CPUs */
511 ret = 0;
512 cpumask_clear(&nmi_ipi_pending_mask);
513 }
514 nmi_ipi_busy_count--;
515 nmi_ipi_unlock_end(&flags);
516
517 return ret;
518 }
519 #endif /* CONFIG_NMI_IPI */
520
521 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
522 void tick_broadcast(const struct cpumask *mask)
523 {
524 unsigned int cpu;
525
526 for_each_cpu(cpu, mask)
527 do_message_pass(cpu, PPC_MSG_TICK_BROADCAST);
528 }
529 #endif
530
531 #ifdef CONFIG_DEBUGGER
532 void debugger_ipi_callback(struct pt_regs *regs)
533 {
534 debugger_ipi(regs);
535 }
536
537 void smp_send_debugger_break(void)
538 {
539 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000);
540 }
541 #endif
542
543 #ifdef CONFIG_KEXEC_CORE
544 void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *))
545 {
546 int cpu;
547
548 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000);
549 if (kdump_in_progress() && crash_wake_offline) {
550 for_each_present_cpu(cpu) {
551 if (cpu_online(cpu))
552 continue;
553 /*
554 * crash_ipi_callback will wait for
555 * all cpus, including offline CPUs.
556 * We don't care about nmi_ipi_function.
557 * Offline cpus will jump straight into
558 * crash_ipi_callback, we can skip the
559 * entire NMI dance and waiting for
560 * cpus to clear pending mask, etc.
561 */
562 do_smp_send_nmi_ipi(cpu);
563 }
564 }
565 }
566 #endif
567
568 #ifdef CONFIG_NMI_IPI
569 static void nmi_stop_this_cpu(struct pt_regs *regs)
570 {
571 /*
572 * This is a special case because it never returns, so the NMI IPI
573 * handling would never mark it as done, which makes any later
574 * smp_send_nmi_ipi() call spin forever. Mark it done now.
575 *
576 * IRQs are already hard disabled by the smp_handle_nmi_ipi.
577 */
578 nmi_ipi_lock();
579 nmi_ipi_busy_count--;
580 nmi_ipi_unlock();
581
582 spin_begin();
583 while (1)
584 spin_cpu_relax();
585 }
586
587 void smp_send_stop(void)
588 {
589 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, nmi_stop_this_cpu, 1000000);
590 }
591
592 #else /* CONFIG_NMI_IPI */
593
594 static void stop_this_cpu(void *dummy)
595 {
596 hard_irq_disable();
597 spin_begin();
598 while (1)
599 spin_cpu_relax();
600 }
601
602 void smp_send_stop(void)
603 {
604 static bool stopped = false;
605
606 /*
607 * Prevent waiting on csd lock from a previous smp_send_stop.
608 * This is racy, but in general callers try to do the right
609 * thing and only fire off one smp_send_stop (e.g., see
610 * kernel/panic.c)
611 */
612 if (stopped)
613 return;
614
615 stopped = true;
616
617 smp_call_function(stop_this_cpu, NULL, 0);
618 }
619 #endif /* CONFIG_NMI_IPI */
620
621 struct thread_info *current_set[NR_CPUS];
622
623 static void smp_store_cpu_info(int id)
624 {
625 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR);
626 #ifdef CONFIG_PPC_FSL_BOOK3E
627 per_cpu(next_tlbcam_idx, id)
628 = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
629 #endif
630 }
631
632 /*
633 * Relationships between CPUs are maintained in a set of per-cpu cpumasks so
634 * rather than just passing around the cpumask we pass around a function that
635 * returns the that cpumask for the given CPU.
636 */
637 static void set_cpus_related(int i, int j, struct cpumask *(*get_cpumask)(int))
638 {
639 cpumask_set_cpu(i, get_cpumask(j));
640 cpumask_set_cpu(j, get_cpumask(i));
641 }
642
643 #ifdef CONFIG_HOTPLUG_CPU
644 static void set_cpus_unrelated(int i, int j,
645 struct cpumask *(*get_cpumask)(int))
646 {
647 cpumask_clear_cpu(i, get_cpumask(j));
648 cpumask_clear_cpu(j, get_cpumask(i));
649 }
650 #endif
651
652 void __init smp_prepare_cpus(unsigned int max_cpus)
653 {
654 unsigned int cpu;
655
656 DBG("smp_prepare_cpus\n");
657
658 /*
659 * setup_cpu may need to be called on the boot cpu. We havent
660 * spun any cpus up but lets be paranoid.
661 */
662 BUG_ON(boot_cpuid != smp_processor_id());
663
664 /* Fixup boot cpu */
665 smp_store_cpu_info(boot_cpuid);
666 cpu_callin_map[boot_cpuid] = 1;
667
668 for_each_possible_cpu(cpu) {
669 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu),
670 GFP_KERNEL, cpu_to_node(cpu));
671 zalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu),
672 GFP_KERNEL, cpu_to_node(cpu));
673 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu),
674 GFP_KERNEL, cpu_to_node(cpu));
675 /*
676 * numa_node_id() works after this.
677 */
678 if (cpu_present(cpu)) {
679 set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]);
680 set_cpu_numa_mem(cpu,
681 local_memory_node(numa_cpu_lookup_table[cpu]));
682 }
683 }
684
685 /* Init the cpumasks so the boot CPU is related to itself */
686 cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid));
687 cpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid));
688 cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid));
689
690 if (smp_ops && smp_ops->probe)
691 smp_ops->probe();
692 }
693
694 void smp_prepare_boot_cpu(void)
695 {
696 BUG_ON(smp_processor_id() != boot_cpuid);
697 #ifdef CONFIG_PPC64
698 paca[boot_cpuid].__current = current;
699 #endif
700 set_numa_node(numa_cpu_lookup_table[boot_cpuid]);
701 current_set[boot_cpuid] = task_thread_info(current);
702 }
703
704 #ifdef CONFIG_HOTPLUG_CPU
705
706 int generic_cpu_disable(void)
707 {
708 unsigned int cpu = smp_processor_id();
709
710 if (cpu == boot_cpuid)
711 return -EBUSY;
712
713 set_cpu_online(cpu, false);
714 #ifdef CONFIG_PPC64
715 vdso_data->processorCount--;
716 #endif
717 /* Update affinity of all IRQs previously aimed at this CPU */
718 irq_migrate_all_off_this_cpu();
719
720 /*
721 * Depending on the details of the interrupt controller, it's possible
722 * that one of the interrupts we just migrated away from this CPU is
723 * actually already pending on this CPU. If we leave it in that state
724 * the interrupt will never be EOI'ed, and will never fire again. So
725 * temporarily enable interrupts here, to allow any pending interrupt to
726 * be received (and EOI'ed), before we take this CPU offline.
727 */
728 local_irq_enable();
729 mdelay(1);
730 local_irq_disable();
731
732 return 0;
733 }
734
735 void generic_cpu_die(unsigned int cpu)
736 {
737 int i;
738
739 for (i = 0; i < 100; i++) {
740 smp_rmb();
741 if (is_cpu_dead(cpu))
742 return;
743 msleep(100);
744 }
745 printk(KERN_ERR "CPU%d didn't die...\n", cpu);
746 }
747
748 void generic_set_cpu_dead(unsigned int cpu)
749 {
750 per_cpu(cpu_state, cpu) = CPU_DEAD;
751 }
752
753 /*
754 * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise
755 * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(),
756 * which makes the delay in generic_cpu_die() not happen.
757 */
758 void generic_set_cpu_up(unsigned int cpu)
759 {
760 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
761 }
762
763 int generic_check_cpu_restart(unsigned int cpu)
764 {
765 return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE;
766 }
767
768 int is_cpu_dead(unsigned int cpu)
769 {
770 return per_cpu(cpu_state, cpu) == CPU_DEAD;
771 }
772
773 static bool secondaries_inhibited(void)
774 {
775 return kvm_hv_mode_active();
776 }
777
778 #else /* HOTPLUG_CPU */
779
780 #define secondaries_inhibited() 0
781
782 #endif
783
784 static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle)
785 {
786 struct thread_info *ti = task_thread_info(idle);
787
788 #ifdef CONFIG_PPC64
789 paca[cpu].__current = idle;
790 paca[cpu].kstack = (unsigned long)ti + THREAD_SIZE - STACK_FRAME_OVERHEAD;
791 #endif
792 ti->cpu = cpu;
793 secondary_ti = current_set[cpu] = ti;
794 }
795
796 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
797 {
798 int rc, c;
799
800 /*
801 * Don't allow secondary threads to come online if inhibited
802 */
803 if (threads_per_core > 1 && secondaries_inhibited() &&
804 cpu_thread_in_subcore(cpu))
805 return -EBUSY;
806
807 if (smp_ops == NULL ||
808 (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu)))
809 return -EINVAL;
810
811 cpu_idle_thread_init(cpu, tidle);
812
813 /*
814 * The platform might need to allocate resources prior to bringing
815 * up the CPU
816 */
817 if (smp_ops->prepare_cpu) {
818 rc = smp_ops->prepare_cpu(cpu);
819 if (rc)
820 return rc;
821 }
822
823 /* Make sure callin-map entry is 0 (can be leftover a CPU
824 * hotplug
825 */
826 cpu_callin_map[cpu] = 0;
827
828 /* The information for processor bringup must
829 * be written out to main store before we release
830 * the processor.
831 */
832 smp_mb();
833
834 /* wake up cpus */
835 DBG("smp: kicking cpu %d\n", cpu);
836 rc = smp_ops->kick_cpu(cpu);
837 if (rc) {
838 pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc);
839 return rc;
840 }
841
842 /*
843 * wait to see if the cpu made a callin (is actually up).
844 * use this value that I found through experimentation.
845 * -- Cort
846 */
847 if (system_state < SYSTEM_RUNNING)
848 for (c = 50000; c && !cpu_callin_map[cpu]; c--)
849 udelay(100);
850 #ifdef CONFIG_HOTPLUG_CPU
851 else
852 /*
853 * CPUs can take much longer to come up in the
854 * hotplug case. Wait five seconds.
855 */
856 for (c = 5000; c && !cpu_callin_map[cpu]; c--)
857 msleep(1);
858 #endif
859
860 if (!cpu_callin_map[cpu]) {
861 printk(KERN_ERR "Processor %u is stuck.\n", cpu);
862 return -ENOENT;
863 }
864
865 DBG("Processor %u found.\n", cpu);
866
867 if (smp_ops->give_timebase)
868 smp_ops->give_timebase();
869
870 /* Wait until cpu puts itself in the online & active maps */
871 spin_until_cond(cpu_online(cpu));
872
873 return 0;
874 }
875
876 /* Return the value of the reg property corresponding to the given
877 * logical cpu.
878 */
879 int cpu_to_core_id(int cpu)
880 {
881 struct device_node *np;
882 const __be32 *reg;
883 int id = -1;
884
885 np = of_get_cpu_node(cpu, NULL);
886 if (!np)
887 goto out;
888
889 reg = of_get_property(np, "reg", NULL);
890 if (!reg)
891 goto out;
892
893 id = be32_to_cpup(reg);
894 out:
895 of_node_put(np);
896 return id;
897 }
898 EXPORT_SYMBOL_GPL(cpu_to_core_id);
899
900 /* Helper routines for cpu to core mapping */
901 int cpu_core_index_of_thread(int cpu)
902 {
903 return cpu >> threads_shift;
904 }
905 EXPORT_SYMBOL_GPL(cpu_core_index_of_thread);
906
907 int cpu_first_thread_of_core(int core)
908 {
909 return core << threads_shift;
910 }
911 EXPORT_SYMBOL_GPL(cpu_first_thread_of_core);
912
913 /* Must be called when no change can occur to cpu_present_mask,
914 * i.e. during cpu online or offline.
915 */
916 static struct device_node *cpu_to_l2cache(int cpu)
917 {
918 struct device_node *np;
919 struct device_node *cache;
920
921 if (!cpu_present(cpu))
922 return NULL;
923
924 np = of_get_cpu_node(cpu, NULL);
925 if (np == NULL)
926 return NULL;
927
928 cache = of_find_next_cache_node(np);
929
930 of_node_put(np);
931
932 return cache;
933 }
934
935 static bool update_mask_by_l2(int cpu, struct cpumask *(*mask_fn)(int))
936 {
937 struct device_node *l2_cache, *np;
938 int i;
939
940 l2_cache = cpu_to_l2cache(cpu);
941 if (!l2_cache)
942 return false;
943
944 for_each_cpu(i, cpu_online_mask) {
945 /*
946 * when updating the marks the current CPU has not been marked
947 * online, but we need to update the cache masks
948 */
949 np = cpu_to_l2cache(i);
950 if (!np)
951 continue;
952
953 if (np == l2_cache)
954 set_cpus_related(cpu, i, mask_fn);
955
956 of_node_put(np);
957 }
958 of_node_put(l2_cache);
959
960 return true;
961 }
962
963 #ifdef CONFIG_HOTPLUG_CPU
964 static void remove_cpu_from_masks(int cpu)
965 {
966 int i;
967
968 /* NB: cpu_core_mask is a superset of the others */
969 for_each_cpu(i, cpu_core_mask(cpu)) {
970 set_cpus_unrelated(cpu, i, cpu_core_mask);
971 set_cpus_unrelated(cpu, i, cpu_l2_cache_mask);
972 set_cpus_unrelated(cpu, i, cpu_sibling_mask);
973 }
974 }
975 #endif
976
977 static void add_cpu_to_masks(int cpu)
978 {
979 int first_thread = cpu_first_thread_sibling(cpu);
980 int chipid = cpu_to_chip_id(cpu);
981 int i;
982
983 /*
984 * This CPU will not be in the online mask yet so we need to manually
985 * add it to it's own thread sibling mask.
986 */
987 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
988
989 for (i = first_thread; i < first_thread + threads_per_core; i++)
990 if (cpu_online(i))
991 set_cpus_related(i, cpu, cpu_sibling_mask);
992
993 /*
994 * Copy the thread sibling mask into the cache sibling mask
995 * and mark any CPUs that share an L2 with this CPU.
996 */
997 for_each_cpu(i, cpu_sibling_mask(cpu))
998 set_cpus_related(cpu, i, cpu_l2_cache_mask);
999 update_mask_by_l2(cpu, cpu_l2_cache_mask);
1000
1001 /*
1002 * Copy the cache sibling mask into core sibling mask and mark
1003 * any CPUs on the same chip as this CPU.
1004 */
1005 for_each_cpu(i, cpu_l2_cache_mask(cpu))
1006 set_cpus_related(cpu, i, cpu_core_mask);
1007
1008 if (chipid == -1)
1009 return;
1010
1011 for_each_cpu(i, cpu_online_mask)
1012 if (cpu_to_chip_id(i) == chipid)
1013 set_cpus_related(cpu, i, cpu_core_mask);
1014 }
1015
1016 static bool shared_caches;
1017
1018 /* Activate a secondary processor. */
1019 void start_secondary(void *unused)
1020 {
1021 unsigned int cpu = smp_processor_id();
1022
1023 mmgrab(&init_mm);
1024 current->active_mm = &init_mm;
1025
1026 smp_store_cpu_info(cpu);
1027 set_dec(tb_ticks_per_jiffy);
1028 preempt_disable();
1029 cpu_callin_map[cpu] = 1;
1030
1031 if (smp_ops->setup_cpu)
1032 smp_ops->setup_cpu(cpu);
1033 if (smp_ops->take_timebase)
1034 smp_ops->take_timebase();
1035
1036 secondary_cpu_time_init();
1037
1038 #ifdef CONFIG_PPC64
1039 if (system_state == SYSTEM_RUNNING)
1040 vdso_data->processorCount++;
1041
1042 vdso_getcpu_init();
1043 #endif
1044 /* Update topology CPU masks */
1045 add_cpu_to_masks(cpu);
1046
1047 /*
1048 * Check for any shared caches. Note that this must be done on a
1049 * per-core basis because one core in the pair might be disabled.
1050 */
1051 if (!cpumask_equal(cpu_l2_cache_mask(cpu), cpu_sibling_mask(cpu)))
1052 shared_caches = true;
1053
1054 set_numa_node(numa_cpu_lookup_table[cpu]);
1055 set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu]));
1056
1057 smp_wmb();
1058 notify_cpu_starting(cpu);
1059 set_cpu_online(cpu, true);
1060
1061 local_irq_enable();
1062
1063 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1064
1065 BUG();
1066 }
1067
1068 int setup_profiling_timer(unsigned int multiplier)
1069 {
1070 return 0;
1071 }
1072
1073 #ifdef CONFIG_SCHED_SMT
1074 /* cpumask of CPUs with asymetric SMT dependancy */
1075 static int powerpc_smt_flags(void)
1076 {
1077 int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES;
1078
1079 if (cpu_has_feature(CPU_FTR_ASYM_SMT)) {
1080 printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n");
1081 flags |= SD_ASYM_PACKING;
1082 }
1083 return flags;
1084 }
1085 #endif
1086
1087 static struct sched_domain_topology_level powerpc_topology[] = {
1088 #ifdef CONFIG_SCHED_SMT
1089 { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
1090 #endif
1091 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
1092 { NULL, },
1093 };
1094
1095 /*
1096 * P9 has a slightly odd architecture where pairs of cores share an L2 cache.
1097 * This topology makes it *much* cheaper to migrate tasks between adjacent cores
1098 * since the migrated task remains cache hot. We want to take advantage of this
1099 * at the scheduler level so an extra topology level is required.
1100 */
1101 static int powerpc_shared_cache_flags(void)
1102 {
1103 return SD_SHARE_PKG_RESOURCES;
1104 }
1105
1106 /*
1107 * We can't just pass cpu_l2_cache_mask() directly because
1108 * returns a non-const pointer and the compiler barfs on that.
1109 */
1110 static const struct cpumask *shared_cache_mask(int cpu)
1111 {
1112 return cpu_l2_cache_mask(cpu);
1113 }
1114
1115 static struct sched_domain_topology_level power9_topology[] = {
1116 #ifdef CONFIG_SCHED_SMT
1117 { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
1118 #endif
1119 { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) },
1120 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
1121 { NULL, },
1122 };
1123
1124 void __init smp_cpus_done(unsigned int max_cpus)
1125 {
1126 /*
1127 * We are running pinned to the boot CPU, see rest_init().
1128 */
1129 if (smp_ops && smp_ops->setup_cpu)
1130 smp_ops->setup_cpu(boot_cpuid);
1131
1132 if (smp_ops && smp_ops->bringup_done)
1133 smp_ops->bringup_done();
1134
1135 dump_numa_cpu_topology();
1136
1137 /*
1138 * If any CPU detects that it's sharing a cache with another CPU then
1139 * use the deeper topology that is aware of this sharing.
1140 */
1141 if (shared_caches) {
1142 pr_info("Using shared cache scheduler topology\n");
1143 set_sched_topology(power9_topology);
1144 } else {
1145 pr_info("Using standard scheduler topology\n");
1146 set_sched_topology(powerpc_topology);
1147 }
1148 }
1149
1150 #ifdef CONFIG_HOTPLUG_CPU
1151 int __cpu_disable(void)
1152 {
1153 int cpu = smp_processor_id();
1154 int err;
1155
1156 if (!smp_ops->cpu_disable)
1157 return -ENOSYS;
1158
1159 err = smp_ops->cpu_disable();
1160 if (err)
1161 return err;
1162
1163 /* Update sibling maps */
1164 remove_cpu_from_masks(cpu);
1165
1166 return 0;
1167 }
1168
1169 void __cpu_die(unsigned int cpu)
1170 {
1171 if (smp_ops->cpu_die)
1172 smp_ops->cpu_die(cpu);
1173 }
1174
1175 void cpu_die(void)
1176 {
1177 if (ppc_md.cpu_die)
1178 ppc_md.cpu_die();
1179
1180 /* If we return, we re-enter start_secondary */
1181 start_secondary_resume();
1182 }
1183
1184 #endif